High-voltage-resistant capacitance isolation device and preparation method thereof
By adopting the optimized ONO structure dielectric layer and PECVD process in digital isolation devices, the problem of cracks caused by stress in traditional dielectric layer is solved, and the stability and performance guarantee of high-voltage capacitive isolation devices are achieved.
Patent Information
- Application Number
- CN202310662466.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-06
- Publication Date
- 2024-12-06
AI Technical Summary
In traditional digital isolation devices made of CMOS, cracks are formed in the dielectric layer due to stress problems of filling metals and dielectric materials, and there is a need for improvement in high-voltage capacitive isolation devices and preparation methods.
By optimizing the dielectric layer structure, the ONO structure of silicon dioxide/silicon oxynitride/silicon nitride is adopted, and the dielectric layer is deposited through the PECVD process during the process. After filling the metal, the cracks are reduced by using the force of silicon nitrogen bonds to reduce the occurrence of cracks after being filled with metal. , designed to include a lower plate, a first dielectric layer, a second dielectric layer and a third dielectric layer, the second dielectric layer and the third dielectric layer are ONO structures, and a specific The deposition and etching steps form the capacitance upper plate.
It effectively solves the crack problem caused by stress in the high-voltage isolation device process, ensures the performance of the isolation device, and ensures the stability and thickness of the dielectric layer are not prone to cracking.
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Figure CN119095476A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a high-voltage resistant capacitor isolation device and a preparation method thereof. Background Art
[0002] A digital isolator is a device that realizes signal transmission under electrical isolation. It is widely used in various electronic system equipment such as industrial control, electric power, communication networks, instrumentation, consumer electronics, etc. Capacitive isolation is a common electrical isolation technology. It divides the circuit into two parts through a capacitor to achieve electrical isolation. The traditional isolation capacitor chip includes a substrate, an upper plate, a lower plate, and a dielectric layer between the upper plate and the lower plate.
[0003] Common digital isolators based on CMOS use thicker intermetallic dielectrics (IMDs) as the dielectric layer of the isolation capacitor. Traditional IMDs use silicon dioxide as the dielectric material and use it as the isolator dielectric. However, in actual manufacturing, cracks may occur due to stress problems between the filling metal and the dielectric material. For example, the filled metal tungsten has positive stress, and the dielectric material silicon dioxide has negative stress. After filling, stress pulling causes cracks to form in the IMD.
[0004] Therefore, there is a need in the prior art for improving high voltage resistant capacitor isolation devices and preparation methods. Summary of the invention
[0005] In view of this, the purpose of an embodiment of the present invention is to propose a high-voltage resistant capacitor isolation device and a preparation method. The device of the present invention solves the problem of cracks caused by stress in the manufacturing process of high-voltage isolation devices by optimizing the dielectric layer structure, thereby ensuring the performance of the isolation device.
[0006] Based on the above purpose, on the one hand, an embodiment of the present invention provides a high-voltage resistant capacitor isolation device, which includes, from bottom to top: a lower plate, a dielectric combination layer and an upper plate, the dielectric combination layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer is a silicon dioxide layer, the second dielectric layer and the third dielectric layer are both ONO structures, the ONO structure includes a silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer and a silicon dioxide layer, the lower plate is connected to the modulation signal circuit, and the upper plate is coupled to the isolation capacitor circuit.
[0007] In some embodiments, the electro-plasmonic combination layer is deposited using a PECVD process.
[0008] In some embodiments, the first dielectric layer has a thickness of 0.6-1 μm.
[0009] In some embodiments, the ONO structure includes a 1-3 μm silicon dioxide layer, a 0.5-0.7 μm silicon oxynitride layer, a 0.8-1.2 μm silicon nitride layer, and a 0.2-0.4 μm silicon dioxide layer.
[0010] In some embodiments, the lower electrode plate is an aluminum plate with a thickness of 0.4 to 0.6 μm, and the upper electrode plate is an aluminum plate with a thickness of 2 to 4 μm.
[0011] Another aspect of the present invention provides a method for preparing a high voltage resistant capacitor isolation device, comprising the following steps:
[0012] S1, depositing a first dielectric layer on the lower plate of the capacitor, etching a first through hole in the first dielectric layer, depositing a barrier layer in the first through hole, filling the hole with metal and removing the metal on the surface of the first dielectric layer, and depositing a metal aluminum layer again and forming an M3 plate after photolithography;
[0013] S2, sequentially depositing a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, and a silicon dioxide layer on the M3 electrode to form a second dielectric layer;
[0014] S3, etching a second through hole on the second dielectric layer, depositing a barrier layer in the second through hole, filling the second through hole with metal, and removing the metal on the surface of the second dielectric layer;
[0015] S4, depositing a metal aluminum layer again and then photolithography to form an M4 plate, repeating S2-S3 on the M4 plate, and finally depositing metal aluminum to form an upper plate of the capacitor.
[0016] In some embodiments, in S2, a USG thin film layer with a thickness of 0.8 to 1 μm is first deposited on the M3 plate, and then a low-stress silicon dioxide layer with a thickness of 2 to 3 μm is deposited. The thickness of the silicon dioxide layer is thinned to 1.5 to 2 μm by a CMP process to achieve planarization, and then a low-stress oxide layer with a thickness of 2 to 3 μm is deposited to complete the deposition of the silicon dioxide layer in contact with the M3 plate.
[0017] In some embodiments, the USG thin film layer is deposited using a HDPCVD tool, and the low stress silicon dioxide layer is deposited using a NVLSPECVD tool.
[0018] In some embodiments, the metal filled in the first through-hole and the second through-hole is tungsten.
[0019] In some embodiments, the barrier layer is Ti or TiN.
[0020] The present invention has at least the following beneficial technical effects:
[0021] The present invention provides a high-voltage resistant capacitor isolation device. By optimizing the isolation device structure, the dielectric layer is designed to be an ONO structure, specifically using silicon dioxide / silicon oxynitride + silicon nitride / silicon dioxide. After the subsequent process fills the through hole with metal, the force of the silicon-nitrogen bond is relatively large, and cracking is not likely to occur at the contact position after the metal is deposited. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.
[0023] Figure 1 A schematic diagram of an embodiment of a high voltage resistant capacitor isolation device provided by the present invention. DETAILED DESCRIPTION
[0024] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field of the present invention; the terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. For example, the directions or positions indicated by the terms "length", "width", "up", "down", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the drawings, which are only for the convenience of description and should not be understood as limitations on the present technical solution.
[0026] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions; the terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. "Multiple" means two or more, unless otherwise clearly and specifically defined.
[0027] In the specification and claims of the present invention and the above-mentioned drawings, when an element is referred to as being "fixed to" or "mounted on" or "disposed on" or "connected to" another element, it may be directly or indirectly located on the other element. For example, when an element is referred to as being "connected to" another element, it may be directly or indirectly connected to the other element.
[0028] In addition, reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0029] Ordinary digital isolators based on CMOS use thicker intermetallic dielectrics (IMD) as the dielectric layer of the isolation capacitor. Traditional IMDs use silicon dioxide as the dielectric material and use it as the isolator dielectric. However, in the actual manufacturing process, stress problems between the filling metal and the dielectric material often lead to cracks. For example, cracks are formed in the IMD due to stress pulling between metal tungsten and silicon dioxide. Therefore, the present application optimizes the structure of the capacitor isolation device, such as Figure 1 The schematic diagram of an embodiment of a high-voltage resistant capacitor isolation device provided by the present invention is shown, which includes, from bottom to top: a lower plate 1, a dielectric combination layer (2, 3, 4) and an upper plate 5, the dielectric combination layer includes a first dielectric layer 2, a second dielectric layer 3 and a third dielectric layer 4, the first dielectric layer 2 is a silicon dioxide layer, the second dielectric layer 3 and the third dielectric layer 4 are both ONO structures, the ONO structure includes a silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer and a silicon dioxide layer, the lower plate is connected to a modulation signal circuit, and the upper plate is coupled to an isolation capacitor circuit.
[0030] Further, in Figure 1 In the figure, M1 to M5 are all plates, IMD between the plates is a dielectric layer, IMD1 is between M1 and M2, IMD2 is between M2 and M3, and IMD3 is between M3 and M4 and between M4 and M5. In the present invention, the lower plate 1 is set to the same layer as the M2 plate, the upper plate 5 is set to the same layer as M5, IMD2 is the first dielectric layer of the present invention, and IMD3 is the second dielectric layer and the third dielectric layer of the present invention, which are all ONO structures.
[0031] Furthermore, a through hole 6 is provided between the plates, and the through hole 6 is an electrical path. A thin film, such as metal tungsten, is filled in the electrical path between the plates. However, in actual manufacturing, cracks may occur due to stress problems between the filled metal and the dielectric material. For example, the filled metal tungsten has positive stress, and the dielectric material silicon dioxide has negative stress. After filling, stress pulling causes cracks to form in the IMD, especially when the dielectric layer is thicker, the crack problem is more likely to occur, for example Figure 1The dielectric layer between M3 and M4 and between M4 and M5 is relatively thick, about 5 to 7 μm, while the thickness between M1 to M2 and between M2 to M3 is relatively thin, about 0.6 to 1 μm. The thinner dielectric layer is not prone to cracks caused by stress pulling in the actual process. Therefore, M1 to M2 and M2 to M3 are set as silicon dioxide layers, and between M3 to M4 and between M4 to M5 are set as the ONO structure of the present invention. After being improved to the ONO structure, since the silicon-nitrogen bond force in silicon nitride is greater than the silicon-oxygen bond force in silicon dioxide, the thicker dielectric layer film and the metal film in the through hole are not prone to cracks.
[0032] Furthermore, the dielectric combination layers of the present invention are all deposited using a PECVD process.
[0033] Furthermore, the thickness of the first dielectric layer 2 is 0.6-1 μm, ie, IMD2 in the figure.
[0034] Furthermore, the second dielectric layer 3 and the third dielectric layer 4 are both ONO structures, including from bottom to top a 1-3 μm silicon dioxide layer, a 0.5-0.7 μm silicon oxynitride layer, a 0.8-1.2 μm silicon nitride layer and a 0.2-0.4 μm silicon dioxide layer.
[0035] Furthermore, the lower electrode plate 1 is an aluminum plate with a thickness of 0.4 to 0.6 μm, and the upper electrode plate 5 is an aluminum plate with a thickness of 2 to 4 μm.
[0036] Another aspect of the present invention provides a method for preparing a high voltage resistant capacitor isolation device, comprising the following steps:
[0037] S1, depositing a first dielectric layer on the lower plate of the capacitor, etching a first through hole in the first dielectric layer, depositing a barrier layer in the first through hole, filling the hole with metal and removing the metal on the surface of the first dielectric layer, and depositing a metal aluminum layer again and forming an M3 plate after photolithography;
[0038] S2, sequentially depositing a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, and a silicon dioxide layer on the M3 electrode plate to form a second dielectric layer;
[0039] S3, etching a second through hole on the second dielectric layer, depositing a barrier layer in the second through hole, filling the second through hole with metal, and removing the metal on the surface of the second dielectric layer;
[0040] S4, depositing a metal aluminum layer again and then photolithography to form an M4 plate, repeating S2-S3 on the M4 plate, and finally depositing metal aluminum to form an upper plate of the capacitor.
[0041] Furthermore, in S2, a USG thin film layer with a thickness of 0.8 to 1 μm is first deposited on the M3 plate, and then a low-stress silicon dioxide layer with a thickness of 2 to 3 μm is deposited. The thickness of the silicon dioxide layer is thinned to 1.5 to 2 μm by a CMP process to achieve planarization, and then a low-stress oxide layer with a thickness of 2 to 3 μm is deposited to complete the deposition of the silicon dioxide layer in contact with the M3 plate.
[0042] Furthermore, the USG thin film layer is deposited using a HDPCVD machine, and the low stress silicon dioxide layer is deposited using a NVLS PECVD machine.
[0043] Further, in S4, a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, and a silicon dioxide layer are sequentially deposited on the M4 plate to form a third dielectric layer, a third through hole is etched on the second dielectric layer, a barrier layer is deposited in the third through hole, and then a metal is filled and the metal on the surface of the third dielectric layer is removed. In some embodiments, the metal filled in the first through hole, the second through hole, and the third through hole is tungsten.
[0044] Furthermore, the barrier layer is Ti or TiN.
[0045] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.
[0046] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.
[0047] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.
[0048] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.
Claims
1. A high voltage resistant capacitor isolation device, characterized in that: From bottom to top, it includes: a lower plate, a dielectric combination layer and an upper plate, the dielectric combination layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer is a silicon dioxide layer, the second dielectric layer and the third dielectric layer are both ONO structures, the ONO structure includes a silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer and a silicon dioxide layer, the lower plate is connected to a modulation signal circuit, and the upper plate is coupled to an isolation capacitor circuit.
2. The high voltage capacitor isolation device according to claim 1, characterized in that: The dielectric combination layer is deposited by using a PECVD process.
3. The high voltage capacitor isolation device according to claim 1, characterized in that: The thickness of the first dielectric layer is 0.6-1 μm.
4. The high voltage capacitor isolation device according to claim 1, characterized in that: The ONO structure includes a silicon dioxide layer of 1 to 3 μm, a silicon oxynitride layer of 0.5 to 0.7 μm, a silicon nitride layer of 0.8 to 1.2 μm and a silicon dioxide layer of 0.2 to 0.4 μm.
5. The high voltage capacitor isolation device according to claim 1, characterized in that: The lower electrode plate is an aluminum plate with a thickness of 0.4 to 0.6 μm, and the upper electrode plate is an aluminum plate with a thickness of 2 to 4 μm.
6. A method for preparing a high voltage resistant capacitor isolation device, characterized in that: include: S1, depositing a first dielectric layer on the lower plate of the capacitor, etching a first through hole in the first dielectric layer, depositing a barrier layer in the first through hole, filling the hole with metal and removing the metal on the surface of the first dielectric layer, and depositing a metal aluminum layer again and performing photolithography to form an M3 plate; S2, sequentially depositing a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, and a silicon dioxide layer on the M3 electrode plate to form a second dielectric layer; S3, etching a second through hole on the second dielectric layer, depositing a barrier layer in the second through hole, filling the second through hole with metal, and removing the metal on the surface of the second dielectric layer; S4, depositing a metal aluminum layer again and performing photolithography to form an M4 electrode plate, repeating S2-S3 on the M4 electrode plate, and finally depositing metal aluminum to form an upper electrode plate of the capacitor.
7. The method for preparing a high voltage resistant capacitor isolation device according to claim 6, characterized in that: In S2, a USG thin film layer with a thickness of 0.8 to 1 μm is first deposited on the M3 electrode plate, and then a low-stress silicon dioxide layer with a thickness of 2 to 3 μm is deposited. The thickness of the silicon dioxide layer is thinned to 1.5 to 2 μm by a CMP process to achieve planarization, and then a low-stress oxide layer with a thickness of 2 to 3 μm is deposited to complete the deposition of the silicon dioxide layer in contact with the M3 electrode plate.
8. The method for preparing a high voltage resistant capacitor isolation device according to claim 7, characterized in that: The USG thin film layer is deposited using a HDPCVD machine, and the low stress silicon dioxide layer is deposited using a NVLS PECVD machine.
9. The method for preparing a high voltage resistant capacitor isolation device according to claim 6, characterized in that: The metal filled in the first through hole and the second through hole is tungsten.
10. The method for preparing a high voltage resistant capacitor isolation device according to claim 6, characterized in that: The barrier layer is Ti or TiN.