Split gate power MOSFET with enhanced gate lock resistance and method of manufacture

Abstract

The invention discloses a split-gate power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with enhanced anti-gate-lock performance and a manufacturing method. The split-gate power MOSFET comprises a semiconductor layer of a first doping type arranged on a substrate; the two gate trenches are arranged in the semiconductor layer, and shielding gates, isolation layers and control gates are formed in the gate trenches from bottom to top; the body region of the second doping type is arranged in the semiconductor layer between the two gate grooves, the buried layer of the first doping type is arranged below the body region in a spaced mode, the impurity concentration in the buried layer is larger than that in the semiconductor layer except the buried layer, and the bottom of the buried layer is higher than the bottoms of the gate grooves in the longitudinal direction. The gate lock resistance of the device can be remarkably improved, and meanwhile, the on-resistance can be further reduced, so that the comprehensive performance of the SGT device can be improved, the application of the SGT device in the high-power field is facilitated, and the SGT device is particularly suitable for a high-inductive-reactance load scene.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a split-gate power MOSFET with enhanced anti-gate lock performance and a manufacturing method. Background Art

[0002] Split-gate MOS (SGT) has the characteristics of low on-resistance and high power density, and its dynamic anti-latch up performance enhancement has always been a research hotspot.

[0003] The most notable structural feature of the split-gate power MOSFET is that there are two layers of polycrystalline, upper and lower, in the trench, with an oxide layer between them. Among them, the upper polycrystalline serves as the control gate, and the lower polycrystalline is at zero potential and serves as the shielding gate. Under the condition of high drain potential, the epitaxial material area between the shielding gates at the bottom of adjacent trenches produces a depletion region to bear the potential drop, that is, the reverse withstand voltage utilizes the charge balance principle. Therefore, an epitaxial layer with a higher doping concentration than ordinary trench MOSFET can be used, and under the condition of obtaining the same withstand voltage, it has a lower on-resistance or a higher current density, which is conducive to high-power applications.

[0004] On the other hand, due to the increase in current density, the thermal effect of the device in working state will become prominent. The most important of these is the avalanche breakdown and potential gate lock effect caused by the voltage superimposed by the inductive load in the high-power switching state, which will cause the current to increase sharply, resulting in permanent thermal damage to the device. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a split-gate power MOSFET with enhanced anti-gate lock performance and a manufacturing method.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a split-gate power MOSFET with enhanced anti-gate lock performance, comprising:

[0008] A semiconductor layer of a first doping type disposed on the substrate;

[0009] Two gate trenches are arranged in parallel in the semiconductor layer from the surface of the semiconductor layer downward, wherein a shielding gate, an isolation layer and a control gate are formed in the gate trenches from bottom to top;

[0010] a body region of a second doping type disposed in the semiconductor layer between the two gate trenches;

[0011] A buried layer of the first doping type in the semiconductor layer disposed below the body region, wherein the impurity concentration in the buried layer is greater than the impurity concentration in the semiconductor layer outside the buried layer, and the bottom of the buried layer is higher than the bottom of the gate trench in the vertical direction.

[0012] Furthermore, it also includes: an expanded buried layer region, the buried layer is included in the expanded buried layer region, the expanded buried layer region is formed by diffusion of doped impurities in the buried layer into the surrounding semiconductor layer, the top of the expanded buried layer region is located below the bottom of the body region, the bottom of the expanded buried layer region is higher than the bottom of the gate trench in the vertical direction, and the side of the expanded buried layer region is limited to reaching the side wall of the gate trench.

[0013] Furthermore, the expanded buried layer region has an impurity concentration distribution that decreases gradually from the middle of the buried layer to the surrounding semiconductor layer.

[0014] Furthermore, the maximum impurity concentration in the expanded buried layer region is lower than the critical concentration; the critical concentration satisfies: when the maximum impurity concentration in the expanded buried layer region is in the critical concentration state, the expanded buried layer region and the corner region between the bottom and the side of the gate trench simultaneously undergo avalanche breakdown under the action of reverse pressure.

[0015] Furthermore, it also includes:

[0016] a source region of a first doping type disposed in the semiconductor layer above the body region;

[0017] An interlayer dielectric layer disposed on the surface of the semiconductor layer and covering the gate trench and the source region;

[0018] A conductive contact hole disposed on the surface of the interlayer dielectric layer and connected downward to the body region;

[0019] A metal layer is disposed on the surface of the interlayer dielectric layer and in contact with the top of the conductive contact hole.

[0020] The present invention also provides a method for manufacturing a split-gate power MOSFET with enhanced anti-gate lock performance, comprising:

[0021] providing a substrate;

[0022] Forming a semiconductor layer of a first doping type and a buried layer of the first doping type in the semiconductor layer on the substrate, and making the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer;

[0023] Forming two gate trenches in the semiconductor layer from the surface of the semiconductor layer downwards and located in parallel on both sides of the buried layer, and making the bottom of the gate trench lower than the bottom of the buried layer in the vertical direction;

[0024] forming a shielding gate, an isolation layer and a control gate from bottom to top in the gate trench;

[0025] A body region of a second doping type is formed in the semiconductor layer above the buried layer and spaced apart from the buried layer.

[0026] Further, forming a semiconductor layer of the first doping type and a buried layer of the first doping type in the semiconductor layer on the substrate, and making the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer, specifically includes:

[0027] Using an epitaxial process, forming a first portion of the semiconductor layer of a first doping type homogeneous with the substrate material on the substrate;

[0028] Implanting ions of a first doping type and annealing to form a buried layer of the first doping type below the surface of the first portion of the semiconductor layer;

[0029] Using an epitaxial process, forming a second portion of the semiconductor layer of a first doping type homogeneous with the material of the first portion of the semiconductor layer on the surface of the first portion of the semiconductor layer, thereby forming a complete semiconductor layer and the buried layer located in the semiconductor layer;

[0030] The impurity superposition effect during ion implantation is utilized to make the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer.

[0031] Furthermore, the forming of a shielding gate, an isolation layer and a control gate from bottom to top in the gate trench specifically includes:

[0032] Using a thermal oxidation process to form a first oxide layer on the inner wall of the gate trench;

[0033] forming a second oxide layer on the surface of the first oxide layer by a deposition process;

[0034] Filling a first gate material layer in the gate trench within the second oxide layer;

[0035] Partially etching back the first gate material layer, the first oxide layer, and the second oxide layer to form a shielding gate formed by the remaining first gate material layer and a shielding gate oxide layer formed by the remaining first oxide layer and the second oxide layer at the lower portion of the gate trench;

[0036] Using a thermal oxidation process, a third oxide layer is formed on the exposed upper sidewall of the gate trench and on the top of the shielding gate;

[0037] Filling a second gate material layer in the gate trench within the third oxide layer;

[0038] The redundant third oxide layer and the second gate material layer at the top of the gate trench are removed, and a control gate formed by the second gate material layer, a control gate oxide layer formed by the third oxide layer located on the sidewall of the gate trench, and an isolation layer formed by the third oxide layer located on the top of the shielding gate are formed at the upper portion of the gate trench.

[0039] Further, forming a body region of a second doping type separated from the buried layer in the semiconductor layer above the buried layer specifically includes:

[0040] Implanting ions of the second doping type and performing annealing to form a body region of the second doping type separated from the buried layer in the semiconductor layer above the buried layer;

[0041] Also includes:

[0042] Implanting ions of the first doping type and performing annealing to form a source region of the first doping type in the semiconductor layer above the body region;

[0043] forming an interlayer dielectric layer on the surface of the semiconductor layer;

[0044] forming a conductive contact hole connected to the body region on the surface of the interlayer dielectric layer;

[0045] forming a metal layer on the surface of the interlayer dielectric layer and in contact with the top of the conductive contact hole;

[0046] Wherein, through the thermal effect in the manufacturing process, the doped impurities in the buried layer are diffused into the surrounding semiconductor layers to form an expanded buried layer region containing the buried layer, and the expanded buried layer region has an impurity concentration distribution that decreases from the middle of the buried layer to the surrounding semiconductor layers, and the top of the expanded buried layer region is located below the bottom of the body region, the bottom of the expanded buried layer region is higher than the bottom of the gate trench in the vertical direction, and the side of the expanded buried layer region is limited to reaching the side wall of the gate trench.

[0047] Furthermore, the maximum impurity concentration in the enlarged buried layer region is limited to the condition that, under the action of reverse pressure, the enlarged buried layer region does not undergo avalanche breakdown before the corner region between the bottom and the side of the gate trench.

[0048] It can be seen from the above technical scheme that the present invention forms a buried layer of the same doping type in the doped semiconductor layer between the gate trenches, and utilizes the impurity superposition effect to make the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer to bear the potential drop in the region, thereby significantly improving the device's anti-gate lock capability; at the same time, since the buried layer is in the current path in the forward conduction state, the buried layer with the same doping type reduces the resistivity in the region, so the on-resistance is further reduced. In addition, by utilizing the thermal effect in the manufacturing process, the doped impurities in the buried layer diffuse into the surrounding semiconductor layer to form an expanded buried layer region including the buried layer, and the expanded buried layer region has an impurity concentration distribution that decreases from the middle of the buried layer to the surrounding semiconductor layer, which can further reduce the on-resistance in the current path and improve the ability to resist avalanche breakdown and gate lock effect. Therefore, the present invention improves the comprehensive performance of the SGT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of a split-gate power MOSFET with enhanced anti-gate lock performance according to a preferred embodiment of the present invention;

[0050] Figure 2-Figure 8 The present invention is a process flow chart of a method for manufacturing a split-gate power MOSFET with enhanced anti-gate lock performance according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0052] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials can include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate electrode material can be formed of various materials that can conduct electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate oxide layer material may be composed of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Moreover, the gate oxide layer may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for the gate oxide layer.

[0053] The first doping type may be one of N-type and P-type, and the second doping type may be the other of N-type and P-type. N-type may be formed by injecting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by injecting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0054] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0055] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a split-gate power MOSFET with enhanced anti-gate lock performance according to a preferred embodiment of the present invention. Figure 1 As shown, a split-gate power MOSFET with enhanced anti-gate lock performance of the present invention includes: a semiconductor layer 10 arranged on a substrate (Si Sub), two gate trenches 41 arranged in the semiconductor layer 10, and a body region 63 and a buried layer 20 arranged in the semiconductor layer 10 between the two gate trenches 41.

[0056] Wherein, the semiconductor layer 10 is arranged on the surface of the substrate, and the semiconductor layer 10 is a semiconductor material with a first doping type. Taking the first doping type as N-type and the second doping type as P-type as an example, two gate trenches 41 are arranged in parallel in the N-type semiconductor layer 10 from the surface of the semiconductor layer 10 downward. A shielding gate 42, an isolation layer 53 and a control gate 52 are formed from bottom to top in the gate trench 41; a shielding gate oxide layer 43 is arranged between the shielding gate 42 and the side wall of the gate trench 41, and a control gate oxide layer 51 is arranged between the control gate 52 and the side wall of the gate trench 41. The P-type body region 63 is arranged in the N-type semiconductor layer 10 between the two gate trenches 41, and is located close to the surface of the semiconductor layer 10. The N-type buried layer 20( Figure 1 The buried layer 20 (in the region indicated by the dotted ellipse) is disposed in the N-type semiconductor layer 10 between the two gate trenches 41 and is located below the body region 63, maintaining a certain distance from the body region 63. The bottom of the buried layer 20 is higher than the bottom of the gate trench 41 in the vertical direction. In addition, the N-type impurity concentration in the buried layer 20 is greater than the N-type impurity concentration in the semiconductor layer 10 outside the buried layer 20.

[0057] In some embodiments, an expanded buried region 201 is further provided in the semiconductor layer 10 between the two gate trenches 41; the expanded buried region 201 is a continuous region, and the buried layer 20 is included in the expanded buried region 201. The expanded buried region 201 is formed by diffusion of doping impurities in the original buried layer 20 into the surrounding semiconductor layer 10, thereby expanding the range of the original buried layer 20. The top of the expanded buried region 201 is located below the bottom of the body region 63, the bottom of the expanded buried region 201 is higher than the bottom of the gate trench 41 in the vertical direction, and the side of the expanded buried region 201 is limited to reaching the side wall of the gate trench 41, that is, in the horizontal direction, the left and right ends of the expanded buried region 201 can approach or reach the side wall of the gate trench 41. This diffusion of doping impurities is formed under the action of heat, that is, the expanded buried region 201 is formed by the heat generated on the semiconductor layer 10, which causes the doping impurities in the original buried layer 20 to diffuse to the surrounding area. By forming an enlarged buried layer region 201, the potential drop in this region can be taken up, thereby improving the anti-gate lock capability of the device.

[0058] Furthermore, the expanded buried layer region 201 has an impurity concentration distribution that gradually decreases from the middle of the original buried layer 20 to the surrounding semiconductor layer 10. This can further reduce the on-resistance of the current path, thereby further improving the device's ability to resist avalanche breakdown and gate lock effect.

[0059] In some embodiments, the maximum impurity concentration in the expanded buried region 201 is lower than the critical concentration and maintains a certain gap with the critical concentration. The critical concentration satisfies: when the maximum impurity concentration in the expanded buried region 201 is in the critical concentration state, the expanded buried region 201 and the corner region 411 between the bottom and the side of the gate trench 41 will simultaneously undergo avalanche breakdown under high reverse pressure. That is, the maximum impurity concentration in the expanded buried region 201 is limited to the maximum value that the expanded buried region 201 does not undergo avalanche breakdown before the corner region 411 between the bottom and the side of the gate trench 41 under reverse pressure.

[0060] See also Figure 1 In some embodiments, an N-type source region 62 is further provided in the semiconductor layer 10 above the body region 63 .

[0061] In some embodiments, an interlayer dielectric layer (ILD) 61 is further disposed on the surface of the semiconductor layer 10 . The interlayer dielectric layer 61 covers the gate trench 41 and the source region 62 .

[0062] Furthermore, the material of the interlayer dielectric layer 61 may be, for example, NSG (non-doped silicate glass) and BPSG (boron phospho-silicate glass).

[0063] In some embodiments, a conductive contact hole is further provided on the surface of the interlayer dielectric layer 61, the bottom of which is connected downward to the body region 63. For example, a tungsten plug 72 may be provided in the contact hole.

[0064] In some embodiments, a front metal layer 71 (pattern) is further provided on the surface of the interlayer dielectric layer 61. The metal layer 71 contacts the top of the tungsten plug 72 of the conductive contact hole.

[0065] Furthermore, a passivation layer (not shown) is provided on the surface of the interlayer dielectric layer 61 , and the passivation layer covers the metal layer 71 to protect the device.

[0066] In some embodiments, the semiconductor layer 10 may be formed of a material homogeneous with the substrate. For example, the substrate may be a silicon substrate (Si Sub), and the semiconductor layer 10 may be a silicon epitaxial layer of homogeneous material formed on the silicon substrate and having a certain N-type doping concentration and thickness.

[0067] The following further describes in detail a method for manufacturing a split-gate power MOSFET with enhanced anti-gate lock performance according to the present invention through specific implementation methods and in combination with the accompanying drawings.

[0068] See also Figure 2-Figure 8 , Figure 2-Figure 8 FIG. 1 is a process flow chart of a method for manufacturing a split-gate power MOSFET with enhanced anti-gate lock performance according to a preferred embodiment of the present invention. Figure 2-Figure 8As shown, a method for manufacturing a split-gate power MOSFET with enhanced gate lock resistance of the present invention can be used to manufacture, for example, Figure 1 A split-gate power MOSFET with enhanced anti-gate lock performance is shown, and may include the following steps:

[0069] Step S1: provide a substrate, form a semiconductor layer 10 of a first doping type and a buried layer 20 of the first doping type located in the semiconductor layer 10 on the substrate, and make the impurity concentration in the buried layer 20 greater than the impurity concentration in the semiconductor layer 10 outside the buried layer 20.

[0070] See also Figure 2 A highly doped silicon substrate (Si Sub) can be used, and an epitaxial process can be adopted to first form an epitaxial layer of the first part of the N-type silicon semiconductor layer 10 on the silicon substrate, which is homogeneous with the silicon substrate material and has a certain doping concentration and thickness. The thickness of the first part of the semiconductor layer 10 is less than the total designed thickness of the semiconductor layer 10.

[0071] See also Figure 3 Then, by photolithography, an ion implantation region 202 (buried layer 20 region) is defined on the surface of the first portion of the semiconductor layer 10, and an ion implantation process is used to implant N-type ions of the same doping type as the first portion of the semiconductor layer 10 into the defined ion implantation region 202, for example, N-type ions As may be used for implantation.

[0072] See also Figure 4 After the ion implantation is completed, a rapid thermal annealing is performed to activate the implanted impurity ions and form an N-type doped buried layer 20 below the surface of the first portion of the semiconductor layer 10 .

[0073] Afterwards, an epitaxial process is used to continuously form the second part of the N-type semiconductor layer 10, which is homogeneous with the material of the first part of the semiconductor layer 10, on the surface of the first part of the semiconductor layer 10 until the total designed thickness of the entire semiconductor layer 10 is reached. Thus, a complete semiconductor layer 10 is formed by the first part of the semiconductor layer 10 and the second part of the semiconductor layer 10, and the formed buried layer 20 is located in the semiconductor layer 10.

[0074] By utilizing the impurity superposition effect during ion implantation (i.e., the superposition of the doped impurities injected into the buried layer 20 and the epitaxial doped impurities of the semiconductor layer 10 ), the impurity concentration in the formed buried layer 20 can be greater than the impurity concentration in the semiconductor layer 10 outside the buried layer 20 .

[0075] According to the requirements of the device withstand voltage specification, the doping concentrations during the two epitaxial growths of the first part of the semiconductor layer 10 and the second part of the semiconductor layer 10 can be the same or different, but it is necessary to ensure that the impurity concentration in the buried layer 20 and the subsequently formed diffusion region (expanded buried layer region 201) is greater than the doping concentration during the two epitaxial growths of the semiconductor layer 10.

[0076] Step S2 : forming two gate trenches 41 in the semiconductor layer 10 from the surface of the semiconductor layer 10 downwards and located in parallel on both sides of the buried layer 20 , and making the bottom of the gate trench 41 lower than the bottom of the buried layer 20 in the vertical direction.

[0077] See also Figure 5 Photolithography and etching processes can be used to form two parallel gate trenches 41 in the semiconductor layer 10 on both sides of the buried layer 20 downward on the surface of the semiconductor layer 10, and the bottom of the formed gate trench 41 is lower than the bottom of the buried layer 20 in the vertical direction.

[0078] Step S3 : forming a shielding gate 42 , an isolation layer 53 and a control gate 52 from bottom to top in the gate trench 41 .

[0079] See also Figure 5 Then, a thermal oxidation process may be used to first form a first oxide layer on the inner wall of the gate trench 41. Then, a deposition process may be used to further form a second oxide layer on the surface of the first oxide layer.

[0080] Afterwards, a deposition process may be used to fill the gate trench 41 within the second oxide layer with the first gate material layer.

[0081] Next, the first gate material layer, the first oxide layer, and the second oxide layer are partially etched back (they may be etched back to a height position where the tops of the first oxide layer and the second oxide layer are flush with or close to the surface of the first portion of the semiconductor layer 10 (the top of the buried layer 20)). Thus, a shielding gate 42 formed of the remaining first gate material layer and a shielding gate oxide layer 43 formed of the remaining first oxide layer and the second oxide layer are formed at the lower portion of the gate trench 41.

[0082] See also Figure 6 Then, a thermal oxidation process may be used to form a third oxide layer on the exposed upper sidewall of the gate trench 41 and on the top of the shielding gate 42. A deposition process may be used to fill the gate trench 41 within the third oxide layer with a second gate material layer.

[0083] Next, a chemical mechanical polishing process may be used to remove the redundant third oxide layer and the second gate material layer at the top of the gate trench 41, so that the top surface of the third oxide layer and the second gate material layer exposed at the top of the gate trench 41 is flush with the surface of the semiconductor layer 10. Thus, a control gate 52 formed by the second gate material layer, a control gate oxide layer 51 formed by the third oxide layer located on the sidewall of the gate trench 41, and an isolation layer 53 formed by the third oxide layer located on the top of the shielding gate 42 are formed at the upper part of the gate trench 41.

[0084] The first gate material layer and the second gate material layer may be made of doped polysilicon. The first oxide layer to the third oxide layer may be made of SiO2.

[0085] Step S4 : forming a body region 63 of the second doping type separated from the buried layer 20 in the semiconductor layer 10 above the buried layer 20 .

[0086] See also Figure 7 P-type ions B may be used to perform ion implantation downward from the surface of the semiconductor layer 10 between the two gate trenches 41 , and annealing is performed to form a P-type body region 63 in the semiconductor layer 10 , and the formed body region 63 is spaced a certain distance above the buried layer 20 .

[0087] Step S5 : implanting ions of the first doping type and performing annealing to form a source region 62 of the first doping type in the semiconductor layer 10 above the body region 63 .

[0088] See also Figure 7 Next, N-type ions As may be used to perform ion implantation downward from the surface of the semiconductor layer 10 between the two gate trenches 41 , followed by annealing to form an N-type source region 62 in the semiconductor layer 10 above the body region 63 .

[0089] After that, you can continue with the following steps:

[0090] Step S6 : forming an interlayer dielectric layer 61 on the surface of the semiconductor layer 10 .

[0091] See also Figure 7 The interlayer dielectric layer 61 (ILD) may be formed by depositing NSG and BPSG on the surface of the semiconductor layer 10 and then reflowing the deposited NSG and BPSG. The interlayer dielectric layer 61 may cover the gate trench 41 and the source region 62 .

[0092] Step S7 : forming a conductive contact hole connected to the body region 63 on the surface of the interlayer dielectric layer 61 .

[0093] See also Figure 8Then, a contact hole can be formed on the surface of the interlayer dielectric layer 61 above the body region 63 and the source region 62 by using photolithography and etching processes, and the bottom of the contact hole is in contact with the top of the body region 63. Next, Ti and TiN layers can be formed on the inner wall of the contact hole in sequence, and tungsten can be filled in the contact hole within the TiN layer. Then, by chemical mechanical polishing, excess Ti, TiN and tungsten materials on the surface of the interlayer dielectric layer 61 outside the contact hole are removed, and a tungsten plug 72 is formed in the contact hole, thereby forming a conductive contact hole connected to the body region 63 at the bottom.

[0094] Step S8: forming a metal layer 71 on the surface of the interlayer dielectric layer 61 so as to contact the top of the conductive contact hole.

[0095] See also Figure 8 Finally, a sputtering process may be used to form, for example, an AlSiCu metal layer 71 on the surface of the interlayer dielectric layer 61, and the AlSiCu metal layer 71 is in contact with the top of the tungsten plug 72 of the conductive contact hole. Subsequently, the AlSiCu metal layer 71 may be patterned by photolithography and etching processes, and a passivation layer pattern (not shown) may be formed on the surface of the interlayer dielectric layer 61. The passivation layer is used to cover the metal layer 71 to protect the device.

[0096] It should be noted that, through the thermal effects of the above-mentioned epitaxial high-temperature diffusion, gate oxide layer oxidation, P-type and N-type ion implantation, annealing, ILD dielectric deposition and reflow, as well as other thermal processing processes in the device manufacturing process, the doped impurities in the buried layer 20 diffuse into the surrounding semiconductor layer 10, forming an expanded buried layer region 201 including the buried layer 20.

[0097] It can be seen that Figure 4 The buried layer 20, which was originally small in volume when it was just implanted, is subjected to thermal effects such as diffusion and annealing during the manufacturing process and develops into an expanded doping region with a certain concentration gradient and spatial distribution, such as Figure 7 , Figure 8 As shown. The expanded buried region 201 has an impurity concentration distribution that gradually decreases from the middle of the original buried layer 20 to the surrounding semiconductor layer 10, and the top of the expanded buried region 201 is located below the bottom of the body region 63, the bottom of the expanded buried region 201 is higher than the bottom of the gate trench 41 in the vertical direction, and the side of the expanded buried region 201 is limited to reaching the side wall of the gate trench 41. The maximum impurity concentration in the expanded buried region 201 is limited to the maximum that the expanded buried region 201 does not undergo avalanche breakdown before the corner region 411 between the bottom and the side of the gate trench 41 under the action of reverse pressure.

[0098] The key to the realization of the present invention lies in the close integration of manufacturing process and structural design. The structural design must be carried out first to meet the device electrical parameter requirements, and then the required structure is obtained through process integration, especially thermal budget simulation design, with the focus on the buried layer 20 doping and impurity diffusion distribution. These two processes are complementary and mutually conditional. After the structure is determined, the process manufacturing is carried out, and the necessary monitoring of the manufacturing process is implemented.

[0099] In summary, the present invention forms a buried layer 20 of the same doping type in the doped semiconductor layer 10 between the gate trenches 41, and utilizes the impurity superposition effect to make the impurity concentration in the buried layer 20 greater than the impurity concentration in the semiconductor layer 10 outside the buried layer 20, so as to bear the potential drop in the region, thereby significantly improving the device's anti-gate lock performance; at the same time, since the buried layer 20 is in the current path in the forward conduction state, the buried layer 20 with the same doping type reduces the resistivity in the region, so the on-resistance is further reduced. In addition, by utilizing the thermal effect in the manufacturing process, the doped impurities in the buried layer 20 diffuse into the surrounding semiconductor layer 10 to form an enlarged buried region 201 including the buried layer 20, and the enlarged buried region 201 has an impurity concentration distribution that decreases from the middle of the buried layer 20 to the surrounding semiconductor layer 10, which can further reduce the on-resistance on the current path and improve the ability to resist avalanche breakdown and gate lock effect. Therefore, the present invention improves the comprehensive performance of the SGT device, is beneficial to the application in the high power field, and is particularly suitable for the scene of high inductive load.

[0100] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A split-gate power MOSFET with enhanced anti-gate lock performance, It is characterized in that include: A semiconductor layer of a first doping type disposed on the substrate; Two gate trenches are arranged in parallel in the semiconductor layer from the surface of the semiconductor layer downward, wherein a shielding gate, an isolation layer and a control gate are formed in the gate trenches from bottom to top; a body region of a second doping type disposed in the semiconductor layer between the two gate trenches; A buried layer of the first doping type in the semiconductor layer disposed below the body region, wherein the impurity concentration in the buried layer is greater than the impurity concentration in the semiconductor layer outside the buried layer, and the bottom of the buried layer is higher than the bottom of the gate trench in the vertical direction.

2. The split-gate power MOSFET with enhanced gate lock resistance according to claim 1, It is characterized in that Also includes: An enlarged buried layer region, wherein the buried layer is included in the enlarged buried layer region, the enlarged buried layer region is formed by diffusion of doped impurities in the buried layer into the surrounding semiconductor layer, the top of the enlarged buried layer region is spaced below the bottom of the body region, the bottom of the enlarged buried layer region is higher than the bottom of the gate trench in the vertical direction, and the side of the enlarged buried layer region is limited to reaching the side wall of the gate trench.

3. The split-gate power MOSFET with enhanced gate lock resistance according to claim 2, It is characterized in that The expanded buried layer region has an impurity concentration distribution that decreases gradually from the middle of the buried layer toward the surrounding semiconductor layer.

4. The split-gate power MOSFET with enhanced gate lock resistance according to claim 2, It is characterized in that The maximum impurity concentration in the expanded buried layer region is lower than the critical concentration; the critical concentration satisfies: when the maximum impurity concentration in the expanded buried layer region is in the critical concentration state, the expanded buried layer region and the corner region between the bottom and the side of the gate trench simultaneously undergo avalanche breakdown under the action of reverse pressure.

5. The split-gate power MOSFET with enhanced gate lock resistance according to claim 1, It is characterized in that Also includes: a source region of a first doping type disposed in the semiconductor layer above the body region; An interlayer dielectric layer disposed on the surface of the semiconductor layer and covering the gate trench and the source region; A conductive contact hole disposed on the surface of the interlayer dielectric layer and connected downward to the body region; A metal layer is disposed on the surface of the interlayer dielectric layer and in contact with the top of the conductive contact hole.

6. A method for manufacturing a split-gate power MOSFET with enhanced anti-gate lock performance, It is characterized in that include: providing a substrate; Forming a semiconductor layer of a first doping type and a buried layer of the first doping type in the semiconductor layer on the substrate, and making the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer; Forming two gate trenches in the semiconductor layer from the surface of the semiconductor layer downwards and located in parallel on both sides of the buried layer, and making the bottom of the gate trench lower than the bottom of the buried layer in the vertical direction; forming a shielding gate, an isolation layer and a control gate from bottom to top in the gate trench; A body region of a second doping type is formed in the semiconductor layer above the buried layer and spaced apart from the buried layer.

7. The method for manufacturing a split-gate power MOSFET with enhanced gate lock resistance according to claim 6, It is characterized in that The step of forming a semiconductor layer of a first doping type and a buried layer of the first doping type in the semiconductor layer on the substrate, and making the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer, specifically includes: Using an epitaxial process, forming a first portion of the semiconductor layer of a first doping type homogeneous with the substrate material on the substrate; Implanting ions of a first doping type and annealing to form a buried layer of the first doping type below the surface of the first portion of the semiconductor layer; Using an epitaxial process, forming a second portion of the semiconductor layer of a first doping type homogeneous with the material of the first portion of the semiconductor layer on the surface of the first portion of the semiconductor layer, thereby forming a complete semiconductor layer and the buried layer located in the semiconductor layer; The impurity superposition effect during ion implantation is utilized to make the impurity concentration in the buried layer greater than the impurity concentration in the semiconductor layer outside the buried layer.

8. The method for manufacturing a split-gate power MOSFET with enhanced gate lock resistance according to claim 6, It is characterized in that The forming of a shielding gate, an isolation layer and a control gate from bottom to top in the gate trench specifically includes: Using a thermal oxidation process to form a first oxide layer on the inner wall of the gate trench; forming a second oxide layer on the surface of the first oxide layer by a deposition process; Filling a first gate material layer in the gate trench within the second oxide layer; Partially etching back the first gate material layer, the first oxide layer, and the second oxide layer to form a shielding gate formed by the remaining first gate material layer and a shielding gate oxide layer formed by the remaining first oxide layer and the second oxide layer at the lower portion of the gate trench; Using a thermal oxidation process, a third oxide layer is formed on the exposed upper sidewall of the gate trench and on the top of the shielding gate; Filling a second gate material layer in the gate trench within the third oxide layer; The redundant third oxide layer and the second gate material layer at the top of the gate trench are removed, and a control gate formed by the second gate material layer, a control gate oxide layer formed by the third oxide layer located on the sidewall of the gate trench, and an isolation layer formed by the third oxide layer located on the top of the shielding gate are formed at the upper portion of the gate trench.

9. The method for manufacturing a split-gate power MOSFET with enhanced gate lock resistance according to claim 6, It is characterized in that The forming of a body region of a second doping type separated from the buried layer in the semiconductor layer above the buried layer specifically includes: Implanting ions of the second doping type and performing annealing to form a body region of the second doping type separated from the buried layer in the semiconductor layer above the buried layer; Also includes: Implanting ions of the first doping type and performing annealing to form a source region of the first doping type in the semiconductor layer above the body region; forming an interlayer dielectric layer on the surface of the semiconductor layer; forming a conductive contact hole connected to the body region on the surface of the interlayer dielectric layer; forming a metal layer on the surface of the interlayer dielectric layer and in contact with the top of the conductive contact hole; Wherein, through the thermal effect in the manufacturing process, the doped impurities in the buried layer are diffused into the surrounding semiconductor layers to form an expanded buried layer region containing the buried layer, and the expanded buried layer region has an impurity concentration distribution that decreases from the middle of the buried layer to the surrounding semiconductor layers, and the top of the expanded buried layer region is located below the bottom of the body region, the bottom of the expanded buried layer region is higher than the bottom of the gate trench in the vertical direction, and the side of the expanded buried layer region is limited to reaching the side wall of the gate trench.

10. The method for manufacturing a split-gate power MOSFET with enhanced gate lock resistance according to claim 9, It is characterized in that The maximum impurity concentration in the expanded buried layer region is limited to the extent that, under the action of reverse pressure, the expanded buried layer region does not undergo avalanche breakdown before the corner region between the bottom and the side of the gate trench.

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