Pixel distribution method and device, equipment and storage medium

Abstract

The embodiment of the invention discloses a primitive distribution method and device, equipment and a storage medium, the method is applied to a graphics processor, and the method comprises the steps that at least one piece of primitive group data sent by a primitive distribution module is output to a corresponding partitioning device through a geometric processing pipeline; the primitive group data comprises multiple pieces of to-be-distributed data with a distribution sequence; distributing a plurality of pieces of data to be distributed in each piece of primitive group data based on the distribution sequence through each partitioning device, and generating a polygon list of each graph block; the polygon list comprises distributed data corresponding to the blocks; and for each image block, acquiring distributed data corresponding to the image block from each polygon list corresponding to the image block through a rasterization processing pipeline so as to perform rasterization processing on the image block.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the field of image processing technology, and in particular to a method, device, equipment and storage medium for distributing graphic elements. Background Art

[0002] A graphics processing unit (GPU) is a specialized graphics rendering device for processing and displaying computerized graphics. GPUs are constructed with a highly parallel structure that provides more efficient processing than a typical general-purpose central processing unit (CPU) for a range of complex algorithms. For example, the complex algorithms may correspond to the representation of two-dimensional or three-dimensional computerized graphics.

[0003] However, in the process of GPU rendering graphics, especially under the condition of power and system bandwidth limitations, a tile-based rendering (Tile Based Rendering, TBR) scheme is usually adopted, which divides the picture into image blocks (Tiles, also known as tiles, tiles) so that each Tile can fit into the on-chip cache. For example, if the on-chip cache can store 512kB of data, the picture can be divided into Tiles so that the pixel data contained in each Tile is less than or equal to 512kB. In this way, the scene can be rendered by dividing the picture into Tiles that can be rendered into the on-chip cache and rendering each Tile of the scene individually into the on-chip cache, storing the rendered Tiles from the on-chip cache into the frame buffer, and repeating the rendering and storage for each Tile of the picture. Therefore, the picture can be rendered tile by tile to render each Tile of the scene. It can be understood that the TBR scheme belongs to a mode of delayed reproduction of graphics, and is widely used in mobile devices due to its low power consumption.

[0004] In the traditional TBR processing pipeline, the tiler can determine the tile where all the metadata is located, and then store the metadata in the corresponding polygon list in the memory; because the tiler is a serialized node, when faced with a large amount of metadata, the tiler will become the bottleneck of the entire TBR processing pipeline, affecting the overall graphics processing efficiency. Summary of the invention

[0005] In view of this, embodiments of the present application at least provide a method, apparatus, device, and storage medium for distributing graphics elements.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] On the one hand, an embodiment of the present application provides a primitive distribution method, which is applied to a graphics processor, wherein the graphics processor performs primitive distribution based on at least two blockers in a tile rendering TBR architecture, and each of the blockers corresponds to one or more geometry processing pipelines; the method comprises: outputting at least one primitive group data sent by a primitive distribution module to a corresponding blocker through a geometry processing pipeline; the primitive group data comprises a plurality of to-be-distributed data having a distribution order;

[0008] Distributing the plurality of data to be distributed in each of the primitive group data based on the distribution order by each of the block dividers to generate a polygon list for each tile; the polygon list includes the distributed data corresponding to the tile;

[0009] For each of the tiles, the distributed data corresponding to the tile is obtained from each of the polygon lists corresponding to the tile through a rasterization processing pipeline to perform rasterization processing on the tile.

[0010] On the other hand, an embodiment of the present application provides a primitive distribution device, which is applied to a graphics processor, wherein the graphics processor performs a primitive distribution process based on at least two blockers in a tile rendering TBR architecture, and the device includes:

[0011] A geometry processing pipeline, configured to output at least one primitive group data sent by the primitive distribution module to each of the blockers; the primitive group data includes a plurality of to-be-distributed data with a distribution order;

[0012] A block divider, configured to distribute a plurality of to-be-distributed data in each of the primitive groups based on the distribution order, and generate a polygon list for each tile; the polygon list includes the distributed data corresponding to the tile;

[0013] The rasterization processing pipeline is used for acquiring the distributed data corresponding to each tile from each polygon list corresponding to the tile for performing rasterization processing on the tile.

[0014] On the other hand, an embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor implements some or all of the steps in the above method when executing the program.

[0015] On the other hand, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements part or all of the steps in the above method when executed by a processor.

[0016] On the other hand, an embodiment of the present application provides a graphics processor, which is used to execute part or all of the steps in the above method.

[0017] In an embodiment of the present application, multiple original primitive data in the original input order are processed in parallel by at least two geometry processing pipelines and corresponding at least two blockers, so that the early processing efficiency of the graphics processor can be improved; at the same time, since each of the blockers corresponds to one or more geometry processing pipelines, the blocker can independently process the primitive group data in the corresponding geometry processing pipeline. Compared with the solution of establishing a connection relationship between all geometry processing pipelines and each blocker, the present application does not need to add a complete interconnection network for each blocker, which reduces the area and power costs while also reducing the complexity of the physical design; at the same time, the present application sets up multiple polygon lists for the blocker to store the distributed data corresponding to each tile, and obtains the distributed data corresponding to the tile from the polygon list corresponding to the tile through the rasterization processing pipeline. In this way, the multiple polygon lists obtained by parallel processing of multiple blockers can be merged, thereby realizing the restoration of the original input order of all distributed data corresponding to the tile.

[0018] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0020] Figure 1A A schematic diagram of a typical TBR pipeline process provided in an embodiment of the present application;

[0021] Figure 1B A schematic diagram of a graphic element distribution process provided in an embodiment of the present application;

[0022] Figure 1C A schematic diagram of data flow of image metadata in a TBR architecture provided in an embodiment of the present application;

[0023] Figure 1D A schematic diagram of an implementation flow of a method for distributing graphics elements provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of an implementation flow of a method for distributing graphics elements provided in an embodiment of the present application;

[0025] Figure 3A A schematic diagram of distribution of two groups of graphic elements by a block splitter provided in an embodiment of the present application;

[0026] Figure 3BA schematic diagram of an implementation flow of a method for distributing graphics elements provided in an embodiment of the present application;

[0027] Figure 3C A schematic diagram of distribution of two graphic element groups including state change data packets by a block splitter provided in an embodiment of the present application;

[0028] Figure 4A A schematic diagram of a rasterization processing pipeline accessing a polygon list of a current tile provided by an embodiment of the present application;

[0029] Figure 4B A schematic diagram of an implementation flow of a method for distributing graphics elements provided in an embodiment of the present application;

[0030] Figure 4C A schematic diagram of a polygon list provided in an embodiment of the present application is shown in FIG. 1 ;

[0031] Figure 4D A polygon list provided in an embodiment of the present application Figure 2 ;

[0032] Figure 4E A third schematic diagram of a polygon list provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of the structure of a graphics primitive distribution device provided in an embodiment of the present application;

[0034] Figure 6 A hardware entity diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0036] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing this application and are not intended to limit this application.

[0038] TBR is a process of subdividing a computer graphics image by a regular grid in optical space and rendering each part of the grid or tile separately. The advantage of this design is that it reduces the consumption of memory and bandwidth compared to Immediate Mode Rendering (IMR) that draws the entire frame immediately, which makes TBR commonly used in low-power hardware devices.

[0039] Figure 1A A schematic diagram of a typical TBR pipeline process provided by the embodiment of the present disclosure is as follows: Figure 1A As shown, the TBR pipeline process is divided into a front-end module 110 and a back-end module 120, wherein:

[0040] The front-end module 110 includes a vertex processing module, a graphics processing module and a tiler module (also called a tiler), wherein the vertex processing module is used to perform vertex and primitive transformation (Vertexprocessing) on ​​the graphics data 150, the graphics processing module is used to perform culling, cropping and other processing on the primitives, and the tiler module is used to complete the screen segmentation, record the graphics data covered by the tiles (Tile), and write the generated information such as the tile information (Primitive List) and the vertex information (Vertex Data) into the system memory 130, wherein the Primitive List is a fixed-length array of length Tile, in which each element is a linked list, which stores pointers to all triangles intersecting with the current Tile, and the pointer points to the Vertex Data; the Vertex Data stores vertex and vertex attribute data.

[0041] The back-end module 120 includes a rasterization module, a hidden surface removal (HSR) module, a pixel shading module and an output merging module, wherein the rasterization module is used to convert a primitive into a two-dimensional image, each point in the two-dimensional image contains color, depth and texture data, and the point and related information are called a fragment; the HSR module is used to remove occluded triangles; the pixel texture number shading module is used to color pixels; and the output merging module is used to merge multiple tiles and output them to RT.

[0042] For each Tile, since the amount of data is not large, the required depth data, texture data, and color data (color) can be loaded into the static random access memory (SRAM) stored on the GPU chip, that is, the on-chip memory 140. For example, the hidden surface removal module can store depth data in the depth data buffer in the on-chip memory 140, the pixel shading module can store texture data in the texture data buffer in the on-chip memory 140, and the output merging module can store color data in the color data buffer in the on-chip memory 140.

[0043] In the rendering process, the rendering object (picture) will be divided into multiple tiles, so that all the data of this tile can be accommodated by using the on-chip memory 140. After at least one drawing instruction reaches the GPU, the front-end module 110 processes each drawing instruction in turn and stores the corresponding tile information and vertex information in the system memory 130 until the data stored in the system memory 130 reaches a preset threshold or at least one drawing instruction has been processed. The back-end module 120 will read the corresponding vertex information from the system memory 130 in units of tiles and perform subsequent processing. In this way, since the access of the back-end module 120 to the system memory 130 is changed to the access of the back-end module 120 to the on-chip memory 140, the rendering efficiency can be improved.

[0044] Among them, the above-mentioned front-end module can be called a geometry processing pipeline. In the actual processing process of the graphics processor, the geometry processing pipeline can receive the geometry data stream output by the application and process the primitives in the geometry data stream, including converting the primitives to the screen space and deleting the primitives that are not visible in the screen space. The blocker at the end of the geometry processing pipeline is used to determine which primitives overlap with which Tiles, and for each Tile, the blocker generates a polygon list data structure, which is used to store each primitive that overlaps with the Tile.

[0045] It should be understood that the tiler usually processes the input primitive data in the original order, determines the tiles that each primitive data overlaps, and then writes the primitive data into the corresponding polygon list. The primitive data must be added to the polygon list in the original order, which is the order of the primitive data in the geometry data stream received by the geometry processing pipeline.

[0046] In some scenarios, state change packets including pipeline module configuration are sent between multiple primitives. These state change packets should be output to each polygon list, and their order relative to the polygons (such as triangles) is the same as the original order.

[0047] See also Figure 1B The schematic diagram of the primitive distribution process is shown in FIG. Figure 1B Four tiles are shown as an example, namely, tile 111, tile 112, tile 113 and tile 114. Meanwhile, the geometry data stream received by the current geometry processing pipeline may be as follows: Figure 1A The polygon list 131 in the geometry data stream may include polygon 121, polygon 122, status indication package 0 and polygon 123 arranged in sequence.

[0048] Among them, the polygon 121 overlaps with the tile 111; the polygon 122 overlaps with the tile 111, the tile 112, and the tile 114; the polygon 123 overlaps with the tile 113 and the tile 114. Based on this, the blocker can obtain a polygon list 132 corresponding to the tile 111, a polygon list 133 corresponding to the tile 112, a polygon list 134 corresponding to the tile 113, and a polygon list 135 corresponding to the tile 114. Among them, the polygon list 132 includes the polygon 121, the polygon 122, and the status indication package 0 arranged in sequence; the polygon list 133 includes the polygon 122 and the status indication package 0 arranged in sequence; the polygon list 134 includes the status indication package 0 and the polygon 123 arranged in sequence; the polygon list 135 includes the polygon 122, the status indication package 0, and the polygon 123 arranged in sequence. It can be seen that the status indication package 0 exists in the polygon list corresponding to each tile. At the same time, the order of the status indication package 0 relative to other polygons in each polygon list is the same as the order of the status indication package 0 relative to other polygons in the original polygon list 131.

[0049] See also Figure 1C Schematic diagram of data flow of primitive data in the TBR architecture shown in FIG. As shown in the figure, the TBR architecture may include a primitive distribution module 141, a geometry processing pipeline 142, a blocker 143, and a rasterization processing pipeline 145, wherein the blocker 143 may write a polygon list corresponding to each tile to the memory 144. For example, when the number of tiles is M, there are M polygon lists in the memory, such as Figure 1BThe polygon lists 1441, 1441, ..., 144M in the figure correspond to one polygon list for each tile. The separator 143 is a serialization node, which converts the polygon lists from different geometry processing pipelines (such as Figure 1B Merge the primitives from the geometry processing pipelines 1 to N in the image processing pipeline, restore them to their original order, and write them to the associated polygon lists (such as Figure 1B , polygon list 1441, polygon list 1441, ..., polygon list 144M in ). For each distributed primitive, the blocker determines which tile the primitive overlaps with and appends the primitive to the polygon list corresponding to the tile. Afterwards, the polygon list of each tile is processed by a rasterization pipeline to generate all the pixels of the tile. Please note that multiple rasterization pipelines are logical. In a typical implementation, they are mapped to one or more physical rasterization pipelines in a time-shared manner.

[0050] In some embodiments, the N geometry processing pipelines may be traditional geometry processing pipelines (such as Vertex / Tessellation / Geometry Pipeline, VTG pipeline); in other embodiments, the N geometry processing pipelines may be mesh shader pipelines. It should be understood that only one type of geometry processing pipeline exists in the same architecture.

[0051] In high-performance GPU designs, the above-mentioned serialization node may be a performance limiter for the entire system because its throughput will be limited. Even if multiple serialization blockers are established in the above scheme to independently manage the output of the tiles, all metadata must be collected, sorted, and redistributed to different tiles at some point. In the current scheme, this must happen before the tile data is written to the memory, basically replicating the problems handled by on-chip interconnects in large-scale integrated circuit design. However, if another interconnect network is added to interconnect the blocker and each geometry processing pipeline, the area cost, power cost, and physical design complexity will be significantly increased. This is because the geometry data transmitted between the geometry processing stage and the blocker often consumes tens or hundreds of megabytes, so the bandwidth and latency requirements are not small.

[0052] In order to solve the above problems, the embodiment of the present application provides a method for distributing graphic elements, which can be executed by a processor of a computer device. The computer device may refer to a server, a laptop, a tablet computer, a desktop computer, a smart TV, a set-top box, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable gaming device) and other devices with data processing capabilities.

[0053] Figure 1D A schematic diagram of the implementation process of a method for distributing graphics elements provided in an embodiment of the present application is shown in FIG. Figure 1D As shown, the method includes the following steps S101 to S103:

[0054] Step S101: output at least one primitive group data sent by a primitive distribution module to a corresponding blocker through a geometry processing pipeline; the primitive group data includes a plurality of to-be-distributed data with a distribution order.

[0055] In some embodiments, the primitive distribution module is used to group multiple primitive primitive data with the original input order to obtain at least one primitive group data corresponding to each geometry processing pipeline; the primitive distribution module is connected to each geometry processing pipeline, and for each geometry processing pipeline, the primitive distribution module is also used to output the corresponding at least one primitive group data to the geometry processing pipeline. Thus, by processing the corresponding at least one primitive group data through the blocker, at least two blockers can realize parallel processing of multiple primitive primitive data.

[0056] In some embodiments, each blocker may be connected to one or more geometry processing pipelines, that is, each blocker may be connected to at least one geometry processing pipeline, for example, one blocker may be connected to every two geometry processing pipelines.

[0057] In some embodiments, the number of geometry processing pipelines corresponding to each blocker may be the same or different, for example, the first geometry processing pipeline is connected to one blocker, and the second and third geometry processing pipelines are connected to another blocker, etc. This application is not limited to this. It should be understood that the primitive group data sent by the primitive distribution module to different blockers for processing do not overlap, and will not cause waste of resources.

[0058] Those skilled in the art should understand that the technical solutions of connecting a block divider to one or more geometry processing pipelines all fall within the scope of protection claimed in this application.

[0059] In some embodiments, each geometry processing pipeline is connected to only one blocker, that is, there is a one-to-one correspondence between the geometry processing pipeline and the blocker, and different geometry processing pipelines correspond to different blockers.

[0060] In this embodiment, the above-mentioned primitive group data may include multiple data to be distributed, and the multiple data to be distributed have a distribution order. It should be understood that the distribution order of the multiple data to be distributed in the primitive group data is the same as the order of the multiple data to be distributed in the multiple original primitive data.

[0061] In some embodiments, the plurality of data to be distributed may include image metadata, may also include state change data packets, or may include image metadata and state change data packets at the same time. This application does not limit this.

[0062] Step S102: Distribute the multiple data to be distributed in each of the primitive groups based on the distribution order through each of the block dividers to generate a polygon list for each tile; the polygon list includes the distributed data corresponding to the tile.

[0063] In some embodiments, for any blocker, the blocker receives at least one primitive group data output by the geometry processing pipeline and distributes the primitive group data respectively; in detail, the blocker can distribute multiple data to be distributed in each primitive group data. In the process of distributing multiple data to be distributed in any primitive group data, the tiles corresponding to the data to be distributed can be determined in sequence according to the above distribution order, and based on the tiles corresponding to the data to be distributed, a polygon list corresponding to each tile is generated.

[0064] In some embodiments, the polygon list corresponding to each tile can be pre-generated. After determining the tile corresponding to the data to be distributed, each data to be distributed is written into the corresponding pre-generated polygon list as distributed data, and the polygon list of each tile can be obtained. That is, if the screen is divided into M tiles, M polygon lists need to be established in advance. After that, after determining the tile corresponding to the data to be distributed, the data to be distributed is written into the polygon list corresponding to the tile in the M polygon lists as distributed data.

[0065] In another embodiment, the polygon list corresponding to the above-mentioned tiles can also be generated based on the tiles corresponding to the current data to be distributed after the tiles corresponding to the data to be distributed are determined. That is to say, if the screen is divided into M tiles, there is no need to pre-establish M polygon lists. After determining the tiles corresponding to each data to be distributed, only some (or all) of the tiles need to establish polygon lists to store the corresponding data to be distributed. At this time, it is necessary to count the tiles corresponding to each data to be distributed, and determine at least one distributed data corresponding to the tile to be established; establish a polygon list corresponding to the tile to be established, and write at least one distributed data corresponding to the tile to be established into the corresponding polygon list to generate a polygon list for each tile.

[0066] For example, when a graphic element group data includes 20 data to be distributed, P1 to P20, the block divider can determine the tiles corresponding to the data to be distributed in the order from P1 to P20. For example, the data to be distributed corresponding to tile 1 includes P1 to P10 and P15; the data to be distributed corresponding to tile 2 includes P11 to P14, and the data to be distributed corresponding to tile 3 includes P16 to P20. The graphics processor divides the screen into tiles 1 to 4.

[0067] In some embodiments, a polygon list corresponding to each tile can be generated in advance, and in the process of the block divider determining the tiles corresponding to the data to be distributed in order from P1 to P20, the data to be distributed is written into the corresponding established polygon list. After completing the writing of P20, the polygon list corresponding to tile 1 is obtained, which includes the distributed data arranged in sequence (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P15); the polygon list corresponding to tile 2 includes the distributed data arranged in sequence (P11, P12, P13, P14); the polygon list corresponding to tile 3 includes the distributed data arranged in sequence (P16, P17, P18, P19, P20) and the polygon list corresponding to tile 4, which is empty.

[0068] In other embodiments, the tiles corresponding to the data to be distributed may be determined first, and based on the determined result, a polygon list corresponding to tile 1 is generated, including the distributed data arranged in order (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P15); a polygon list corresponding to tile 2 is generated, including the distributed data arranged in order (P11, P12, P13, P14); a polygon list corresponding to tile 3 is generated, including the distributed data arranged in order (P16, P17, P18, P19, P20). At this time, although the graphics processor divides the screen into tiles 1 to 4, the polygon list corresponding to tile 4 is not generated.

[0069] Step S103 : For each of the tiles, obtain the distributed data corresponding to the tile from each of the polygon lists corresponding to the tile through a rasterization processing pipeline to perform rasterization processing on the tile.

[0070] In the embodiment of the present application, since there are at least two blockers, and different blockers process at least one different primitive group data, the distributed data corresponding to a tile may be distributed in the polygon list of the current tile corresponding to each blocker. During the rasterization process of the current tile, the rasterization processing pipeline merges all polygon lists corresponding to the current tile, that is, merges the distributed data in all polygon lists of the current tile, and then obtains all distributed data corresponding to the tile.

[0071] In some embodiments, the primitive distribution data groups a plurality of original primitive data having an original input order, and in the process of obtaining at least one primitive group data corresponding to each geometry processing pipeline, the at least one primitive group data corresponding to each geometry processing pipeline can be determined in sequence according to the sequence of the primitive group data; wherein, taking the geometry processing pipelines including N as an example, at least one primitive group data corresponding to the first geometry processing pipeline is located before at least one primitive group data corresponding to the second geometry processing pipeline, at least one primitive group data corresponding to the second geometry processing pipeline is located before at least one primitive group data corresponding to the third geometry processing pipeline, and so on; In this way, since the blocker and the geometry processing pipeline correspond one to one, in the process of obtaining the distributed data corresponding to the tile from the polygon list corresponding to the tile through the rasterization processing pipeline, the polygon list corresponding to the tile in each blocker can be read in sequence based on the order of each blocker, thereby realizing the restoration of the sequence of each primitive group data, and since the multiple data to be distributed in each primitive group data are distributed and written into the polygon list according to the distribution order, therefore, when the rasterization processing pipeline reads the multiple distributed data in the primitive group data from the polygon list, the sequence between the multiple distributed data in the primitive group data can also be restored. Based on the above embodiment, the rasterization processing pipeline can realize the restoration of the original input order of all the distributed data corresponding to the tile.

[0072] Based on the above embodiments, the early processing efficiency of the graphics processor can be improved by performing parallel processing on multiple original primitive data in the original input order through at least two geometry processing pipelines and corresponding at least two blockers; at the same time, since each of the blockers corresponds to one or more geometry processing pipelines, the blocker can independently process the primitive group data in the corresponding geometry processing pipeline. Compared with the solution of establishing a connection relationship between all geometry processing pipelines and each blocker, the present application does not need to add a complete interconnection network for each blocker, which reduces the area and power costs while also reducing the complexity of the physical design; at the same time, the present application sets up multiple polygon lists for the blocker to store the distributed data corresponding to each tile, and obtains the distributed data corresponding to the tile from the polygon list corresponding to the tile through the rasterization processing pipeline, so that the multiple polygon lists obtained by parallel processing of multiple blockers can be merged, thereby realizing the restoration of the original input order of all distributed data corresponding to the tile.

[0073] In some embodiments, the primitive group data further includes a primitive group tag, and the primitive group tag is used to represent the sequence between the primitive group data. Figure 2 is an optional flow chart of the method for distributing graphics elements provided in the embodiment of the present application, and the method can be executed by a processor of a computer device. Figure 1D The method further comprises the step of grouping a plurality of original image data in the original input order, combining Figure 2 The steps shown are explained.

[0074] Step S201: Grouping a plurality of original primitive metadata in the original input order by the primitive distribution module to obtain at least one primitive group and a primitive group label corresponding to each primitive group.

[0075] The primitive group includes a plurality of to-be-distributed data in a distribution order, and the primitive group label is used to represent the positions of the plurality of to-be-distributed data in the original input order.

[0076] In this embodiment, the input of the primitive distribution module is a plurality of primitive primitive data in the original input order. The primitive distribution module is connected to at least two geometry processing pipelines at the same time, and the blocker corresponds to one or more geometry processing pipelines; based on this, the primitive distribution module can output at least one primitive group data to the geometry processing pipeline respectively, and then the blocker can obtain the corresponding at least one primitive group and primitive group label from the corresponding geometry processing pipeline.

[0077] In some embodiments, the primitive distribution module is used to group the multiple original primitive data according to the original input order to obtain the at least one primitive group; at the same time, the primitive distribution module can also assign a primitive group label to each primitive group after grouping, and the primitive group label is used to determine the order between the primitive groups. Among them, the primitive group can include multiple data to be distributed, so the primitive group is also used to represent the position of the corresponding multiple data to be distributed in the original input order.

[0078] In some embodiments, in the process of grouping the multiple original graphic element data, if it is necessary to divide them into graphic element groups with a preset number of blocks, (preset number of blocks - 1) segmentation points can be determined between the multiple original graphic element data, and the multiple original graphic element data can be grouped based on the (preset number of blocks - 1) segmentation points to obtain the at least one graphic element group.

[0079] Exemplarily, there are 100 original primitive data in the original input order, which are P1 to P100 respectively. After grouping the 100 original primitive data, 4 primitive groups are obtained. The first primitive group includes P1 to P25, the second primitive group includes P26 to P50, the third primitive group includes P51 to P75, and the third primitive group includes P76 to P100. Then, the primitive distribution module can assign a primitive group label L1 to the first primitive group, a primitive group label L2 to the second primitive group, a primitive group label L3 to the third primitive group, and a primitive group label L4 to the fourth primitive group. Among them, L1<L2<L3<L4.

[0080] In some embodiments, for each primitive group, the prior order of the plurality of data to be distributed in the primitive group is the same as the prior order of the plurality of data to be distributed in the plurality of original primitive data.

[0081] Exemplarily, there are 100 original graphic element data in the original input order, which are P1 to P100. After the 100 original graphic element data are grouped, for any graphic element group, taking the graphic element group as the third graphic element group mentioned above as an example, the order of the 25 to-be-distributed data in the third graphic element group is the same as the order of the 25 to-be-distributed data in P1 to P100.

[0082] In some embodiments, the at least one primitive group satisfies any one of the following preset grouping conditions: the number of to-be-distributed data in each of the primitive groups is the same; the number of mesh shader workgroups corresponding to each of the to-be-distributed data in each of the primitive groups is the same.

[0083] In some embodiments, the geometry processing pipeline is a traditional geometry pipeline, which may include at least one of the following: Vertex Shader (VS), Geometry Shader (GS), Hull Shader (HS), Domain Shader (DS). Accordingly, the preset grouping condition may be that the number of data to be distributed in each of the primitive groups is the same, and the step of grouping the plurality of original primitive data in the original input order by the primitive distribution module to obtain at least one primitive group and a corresponding primitive group label may be implemented by step S2011.

[0084] Step S2011: The primitive distribution module groups the plurality of original primitive metadata based on a preset block size and the original input order to obtain the at least one primitive group and a primitive group label corresponding to each primitive group.

[0085] The preset block size is used to characterize the number of data to be distributed included in the primitive groups obtained after grouping. When the data to be distributed only includes primitive data, the number of primitive data included in each primitive group obtained is the same; when the data to be distributed includes primitive data and state change data packets, the total number of primitive data and state change data packets included in each primitive group obtained is the same.

[0086] Exemplarily, the above grouping process is described by taking the preset block size of 20 as an example. In the case of 100 original primitive data with the original input order, which are P1 to P100, P1 to P20 can be first determined as the first primitive group based on the preset block size, and L1 can be assigned as the primitive group label corresponding to the first primitive group; P21 to P40 can be determined as the second primitive group, and L2 can be assigned as the primitive group label corresponding to the second primitive group, and so on, until P81 to P100 are determined as the fifth primitive group, and L5 can be assigned as the primitive group label corresponding to the fifth primitive group.

[0087] By grouping multiple original graphic element data based on the above embodiment, multiple graphic element groups of the same size can be obtained. Therefore, when each graphic element group is distributed to each geometry processing pipeline, each geometry processing pipeline can process the same amount of data to be distributed as much as possible, thereby achieving load balancing of the geometry processing pipeline.

[0088] In other embodiments, the geometry processing pipeline is a mesh shader pipeline, which includes a mesh shader for generating primitives in a workgroup, and the mesh shader pipeline may also include a task shader. Accordingly, the preset grouping condition is that the number of mesh shader workgroups corresponding to the data to be distributed in each primitive group is the same, and the steps of grouping the plurality of original primitive data with the original input order by the primitive distribution module to obtain at least one primitive group and the corresponding primitive group label may also be implemented through steps S2012 to S2013.

[0089] Step S2012: Obtain the workgroup label of the mesh shader workgroup corresponding to each of the original graphics metadata.

[0090] In some embodiments, the mesh shader workgroup is used to generate primitive metadata, wherein each primitive metadata may be generated by a different mesh shader workgroup, and therefore each primitive metadata may carry a corresponding workgroup tag, which is used to determine the mesh shader workgroup that generated the primitive metadata. Exemplarily, in the process of the mesh shader pipeline generating each primitive metadata, each mesh shader workgroup may assign a corresponding workgroup tag (also referred to as a workgroup serial number ID) to the primitive metadata generated by itself.

[0091] Exemplarily, taking the above-mentioned original graphics metadata including P1 to P100 as an example, among which P1 to P15 are generated by the first mesh shader working group, P16 to P30 are generated by the second mesh shader working group, P31 to P45 are generated by the third mesh shader working group, P46 to P70 are generated by the fourth mesh shader working group, P71 to P90 are generated by the fifth mesh shader working group, and P91 to P100 are generated by the sixth mesh shader working group.

[0092] Step S2013: The primitive distribution module groups the multiple original primitive metadata based on a preset number of workgroups, a workgroup label of each of the original primitive metadata, and the original input order to obtain at least one primitive group and a primitive group label corresponding to each primitive group.

[0093] In some embodiments, the primitive distribution module can obtain all original primitive metadata corresponding to the first workgroup label based on the original input order, and determine whether the preset workgroup number is met; if the preset workgroup number is met, all the obtained original primitive metadata are regarded as a primitive group, and a primitive group label corresponding to the current primitive group is generated; if the preset workgroup number is not met, the original primitive metadata corresponding to the second workgroup label is obtained, and it is continued to be determined whether the preset workgroup number is met, and based on the judgment result, it is determined whether to regard all the obtained original primitive metadata as a primitive group, or to continue to obtain the original primitive metadata corresponding to the next workgroup label until all workgroup labels are traversed.

[0094] Exemplarily, the explanation is based on the example that P1 to P100 correspond to 6 mesh shader workgroups respectively. When the preset number of workgroups is 2, all the original graphics data corresponding to the first mesh shader workgroup and the second mesh shader workgroup can be used as the first primitive group, and L1 is assigned as the primitive group label corresponding to the first primitive group; all the original graphics data corresponding to the third mesh shader workgroup and the fourth mesh shader workgroup can be used as the second primitive group, and L2 is assigned as the primitive group label corresponding to the second primitive group; all the original graphics data corresponding to the fifth mesh shader workgroup and the sixth mesh shader workgroup can be used as the third primitive group, and L3 is assigned as the primitive group label corresponding to the third primitive group.

[0095] By grouping multiple original primitive data based on the above embodiment, multiple primitive groups with the same number of mesh shader work groups corresponding to each data to be distributed can be obtained. Therefore, when each primitive group is distributed to each geometry processing pipeline, each geometry processing pipeline can process the same amount of data to be distributed as much as possible, thereby achieving load balancing of the geometry processing pipeline.

[0096] Step S202: Outputting a primitive group and a primitive group label corresponding to the primitive group to the geometry processing pipeline through the primitive distribution module.

[0097] In some embodiments, the primitive distribution module corresponds to at least two geometry processing pipelines. Therefore, for any one of the at least two geometry processing pipelines, when the primitive distribution module outputs W primitive groups and corresponding primitive group labels to the geometry processing pipeline, after the geometry processing pipeline completes the geometry processing process of the data to be distributed for each of the W primitive groups, the geometry processing pipeline continues to output the W primitive groups and corresponding primitive group labels to the corresponding blocker, and completes the subsequent distribution process of the data to be distributed through the blocker. Wherein, W is a positive integer.

[0098] In some embodiments, the primitive distribution module can directly output all the primitive groups obtained by grouping to each geometry processing pipeline in sequence based on the primitive group labels corresponding to each primitive group, until all the primitive groups are output to the downstream geometry processing pipeline. Exemplarily, in the case of two geometry processing pipelines, the primitive distribution module can sequentially take out the primitive groups with the front primitive group labels based on the primitive group labels corresponding to each primitive group, and output them to the first geometry processing pipeline until the processing queue of the first geometry processing pipeline is full; determine whether there are remaining primitive groups, and if there are remaining primitive groups, continue to sequentially take out the primitive groups with the front primitive group labels and output them to the second geometry processing pipeline until the processing queue of the second geometry processing pipeline is full; if there are remaining primitive groups, continue to perform the above process until all the primitive groups are output to the downstream geometry processing pipeline.

[0099] It should be understood that before the primitive distribution module outputs the primitive group to the geometry processing pipeline, the primitive group label corresponding to the primitive group can be output to the geometry processing pipeline first to determine the boundary between the current primitive group and the previous primitive group. It can be understood that the primitive group is actually a plurality of to-be-distributed data belonging to the same primitive group. The method of sending the primitive group label before sending the primitive group can make the plurality of to-be-distributed data corresponding to different primitive groups have obvious boundaries, and at the same time, it is also convenient for the subsequent order recovery of the to-be-distributed data located in different primitive groups.

[0100] It should be understood that when the number of primitive groups is small and the number of geometry processing pipelines is large, primitive groups are not enough to be allocated to each geometry processing pipeline. At this time, the above-mentioned primitive distribution module can output primitive groups and primitive group labels corresponding to the primitive groups to some geometry processing pipelines.

[0101] In some embodiments, primitive groups and corresponding primitive group tags may be output to the geometry processing pipeline through the primitive distribution module based on a load balancing strategy.

[0102] In this embodiment, after the primitive distribution module groups the multiple original primitive data and obtains at least one primitive group and the primitive group label corresponding to each primitive group, it can output the at least one primitive group and the corresponding primitive group label to the subsequent at least two parallel geometry processing pipelines. In order to avoid the situation where some geometry processing pipelines have a high load and some geometry processing pipelines have a low load, the primitive distribution module can use a load balancing strategy to determine the primitive group corresponding to each geometry processing pipeline, and then output the primitive group and the primitive group label corresponding to the primitive group for each geometry processing pipeline. Since the geometry processing pipeline will output the data to be distributed in the primitive group to the blocker connected to the geometry processing management after processing it, the process of outputting the primitive group can also be described as outputting at least one primitive group and the corresponding primitive group label to the geometry processing pipeline.

[0103] Based on the above embodiment, when the primitive distribution module outputs at least one primitive group to the downstream geometry processing pipeline, at least two geometry processing pipelines can be in a load-balanced state. Therefore, when each geometry processing pipeline processes all original primitive data (i.e., processes all primitive groups) in parallel, it can fully utilize the computing resources of each geometry processing pipeline, and at the same time, improve the overall processing efficiency of the geometry processing pipeline.

[0104] In some embodiments, the above-mentioned step of outputting primitive groups and primitive group labels corresponding to the primitive groups to the geometry processing pipeline through the primitive distribution module based on the load balancing strategy can be implemented through steps S2021 to S2022.

[0105] Step S2021: Based on the primitive group label corresponding to the primitive group and the number of the geometry processing pipelines, determine the label to be assigned corresponding to each of the geometry processing pipelines.

[0106] Step S2022: For each of the geometry processing pipelines, output the to-be-assigned labels and the primitive groups corresponding to the to-be-assigned labels to the geometry processing pipeline through the primitive distribution module.

[0107] In some embodiments, when there are M primitive groups and N geometry processing pipelines, the following method can be used to evenly distribute these primitive groups to each geometry processing pipeline: first, the number of primitive groups that each geometry processing pipeline needs to process is calculated as m=ceil(M / N), that is, the number of primitive groups that each geometry processing pipeline needs to process is the value obtained by dividing M by N and rounding to positive infinity. M primitive group labels are randomly selected from the M primitive group labels as at least one label to be distributed that the first geometry processing pipeline needs to process, and then m primitive group labels are randomly selected from the remaining primitive group labels as at least one label to be distributed that the second processing pipeline needs to process, and so on, until all the remaining primitive group labels are used as at least one label to be distributed for the last geometry processing pipeline.

[0108] Based on the above embodiment, it can be ensured that the number of primitive groups obtained by each geometry processing pipeline is as uniform as possible, and no primitive group is ignored or processed repeatedly. When the primitive groups are randomly assigned to the geometry processing pipelines, it can be ensured that the algorithm has a certain randomness, thereby improving the plasticity of the algorithm. In addition, it should be noted that when M is not divisible by N, the last geometry processing pipeline may need to process a different number of primitive groups than other geometry processing pipelines.

[0109] In some other embodiments, the above-mentioned load balancing strategy can also be implemented through steps S2023 to S2024, and the primitive distribution module outputs the primitive group and the corresponding primitive group label to the geometry processing pipeline.

[0110] Step S2023: Obtain load information of each of the geometry processing pipelines.

[0111] In some embodiments, the load information of the geometry processing pipeline may include at least one of the following: the number of primitive groups being processed in the geometry processing pipeline, the number of primitive groups waiting to be processed, the ratio of the number of primitives being processed to the maximum load number, the ratio of the number of primitive groups waiting to be processed to the maximum waiting number, and the like.

[0112] Step S2024: Based on the load information of each of the geometry processing pipelines, output primitive groups and corresponding primitive group labels to the geometry processing pipelines through the primitive distribution module.

[0113] In some embodiments, when the load information includes the ratio of the number of primitives being processed to the maximum load number, the current load information of each geometry processing pipeline is obtained, which is measured by the ratio of the number of primitives being processed to the maximum load number. If the load ratio of a geometry processing pipeline is lower than a preset load threshold, such as 0.8, it is marked as "idle state"; if the load ratio of a geometry processing pipeline is equal to or higher than the preset load threshold, it is marked as "busy state"; according to the number of geometry processing pipelines in the current idle state, the number of primitive groups that each geometry processing pipeline in the idle state needs to process is calculated m=ceil(M / N), that is, the number of primitive groups that each geometry processing pipeline in the idle state needs to process is the value obtained by rounding M divided by N to zero; all unprocessed primitive groups are randomly assigned to all geometry processing pipelines in the idle state; at the same time, the unassigned primitive groups are randomly assigned to the geometry processing pipelines in the busy state, and at this time, the distribution process of all primitive groups can be completed. It should be understood that the number of primitive groups processed by each geometry processing pipeline in the above allocation process does not exceed its maximum load number.

[0114] In an embodiment of the present application, the set of primitive groups processed by each geometry processing pipeline and the primitive group identifiers corresponding to them are sent to the corresponding geometry processing pipeline for processing. During the output process, it is ensured that each primitive group identifier matches the corresponding primitive group so that each primitive group can be correctly rendered and processed. In this way, primitive groups can be evenly and efficiently allocated to each geometry processing pipeline based on load information. It can ensure that the load ratio of each geometry processing pipeline is as close as possible, and can avoid the problem of reduced processing performance due to excessive load on the geometry processing pipeline. At the same time, it can also improve processing efficiency and make the geometry processing pipeline processing more stable, thereby helping to optimize the effect of the entire rendering process.

[0115] In another embodiment, the ratio of the number of graphic element groups waiting to be processed to the maximum waiting number can also be used as the load information, and then used in the distribution and output process of the graphic element groups. Since it is similar to the above-mentioned implementation process of using the ratio of the number of graphic elements being processed to the maximum carrying number as the load information, this application will not provide a detailed description here.

[0116] In some embodiments, for each of the blockers, when there is target primitive group data in at least one primitive group data of the blocker, the polygon list of the target tile corresponding to the blocker includes a primitive group tag of the target primitive group data and each target distribution data belonging to the target tile in the target primitive group data;

[0117] Among them, the target primitive group data is primitive group data in which there is at least one target distribution data belonging to the target block; the order of each target distribution data in the polygon list is the same as the distribution order; the primitive group label of the target primitive group data is located before each target distribution data.

[0118] In some embodiments, for each blocker, the blocker receives at least one primitive group data output by all corresponding geometry processing pipelines, that is, the blocker receives at least one primitive group and a corresponding primitive group label corresponding to each geometry processing pipeline, wherein each primitive group includes multiple data to be distributed (including at least one primitive data).

[0119] In this embodiment, in the process of distributing the target primitive group data in at least one primitive group data, for the target tile in multiple tiles, if there is at least one target distribution data belonging to the target tile among the multiple data to be distributed (which can also be understood as multiple primitive data) corresponding to the current target primitive group data, then it is necessary to write the primitive group tag of the target primitive group data and each of the target distribution data into the polygon list corresponding to the target tile. The order of each of the target distribution data in the polygon list is the same as the distribution order; the primitive group tag of the target primitive group data is located before each of the target distribution data.

[0120] See also Figure 3A , which shows a schematic diagram of a blocker distributing two primitive groups. For ease of explanation, the following embodiments will be described by taking one blocker corresponding to one geometry processing pipeline as an example, without limiting the number of geometry processing pipelines corresponding to the blocker. The present application can also be applied to a scenario where one blocker corresponds to multiple geometry processing pipelines. Figure 3A In the example, the blocker 312 receives two primitive groups 311 outputted by the corresponding geometry processing pipeline, whose corresponding primitive group labels are L1 and L2, and the primitive group L1 includes four primitive data, namely, P1, P2, P3, and P4, arranged in sequence, and the primitive group L2 includes three primitive data, namely, P5, P6, and P7, arranged in sequence. The blocker 312 can determine the tile to which the primitive data in each primitive group belongs, and write the primitive data into the polygon list corresponding to the tile in the system memory 313.

[0121] For ease of understanding, take the example that a graphics processor divides the screen into M tiles. Figure 3AThe polygon list in may include M polygon lists, and one polygon list is used to store the data corresponding to one tile. For the polygon list 3131 corresponding to the first tile, since the primitive data P2 and P3 in the primitive group L1 and the primitive data P5 in the primitive group L2 overlap with the first tile, it is necessary to write P2, P3 and P5 into the polygon list 3131. At the same time, before writing the primitive data P2 and P3, it is necessary to write the primitive group tag L1 of the first tile into the polygon list 3131, and before writing the primitive data P5, it is necessary to write the primitive group tag L2 of the second tile into the polygon list 3131.

[0122] It should be noted that for the polygon list 3132 corresponding to the second tile, since the primitive data P1 and P4 in primitive group L1 overlap with the second tile, it is necessary to write P1 and P4 into the polygon list 3132. At the same time, before writing the primitive data P1 and P4, it is necessary to write the primitive group label L1 of the first tile into the polygon list 3131. Since there is no primitive data in primitive group L2 that overlaps with the second tile, the polygon list 3132 corresponding to the second tile does not have the primitive group label L2 corresponding to the second primitive group compared to polygon 3131. The polygon list 313M corresponding to the Mth tile is similar to the polygon list 3131 corresponding to the first tile, and the present application will not repeat the description here.

[0123] It can be seen that the order between P2 and P3 in the polygon list 3131 corresponding to the first tile is the same as the order between P2 and P3 in the primitive group L1, and the primitive group label L1 corresponding to the first primitive group is before P2 and P3; the order between P5 to P7 in the polygon list 313M corresponding to the Mth tile is the same as the order between P5 to P7 in the primitive group L2, and the primitive group label L2 corresponding to the second primitive group is before P5 to P7.

[0124] Based on the above embodiments, for any blocker, by setting a polygon list for each tile for the blocker, the rasterization processing pipeline can be facilitated to uniformly extract the metadata of a tile, that is, the rasterization processing pipeline can directly merge the polygon lists corresponding to the current tile in each blocker during the process of rendering the current tile, and thus obtain all the metadata corresponding to the current tile; at the same time, the primitive group label of the primitive group corresponding to the target distribution data in the polygon list provided in the present application is located before the target distribution data, so that in the process of the rasterization processing pipeline merging all polygon lists corresponding to the current tile, the order of the target distribution data can be clarified, thereby effectively restoring the original input order.

[0125] Figure 3B is an optional flow chart of the method for distributing graphics elements provided in the embodiment of the present application, and the method can be executed by a processor of a computer device. Figure 1D , Figure 1D The plurality of data to be distributed includes at least one primitive data; wherein the step of distributing the plurality of data to be distributed in each primitive group data based on the distribution order by the block divider to generate a polygon list for each tile is combined with Figure 3B The steps shown are explained.

[0126] Step S301 : The block splitter sequentially processes the distribution process of each of the primitive group data based on the primitive group label corresponding to each of the primitive group data.

[0127] Among them, for the distribution process of the target primitive group data, the block divider determines the block corresponding to each primitive element in the target primitive group data in turn based on the distribution order; and writes each primitive element in the target primitive group data into the polygon list of the corresponding block.

[0128] In some embodiments, for any blocker, the blocker has obtained at least one primitive group data and a corresponding primitive group label output by the geometry processing pipeline. In step S301, since the primitive group label can represent the prior order between the primitive group data, the blocker needs to process the distribution process of each primitive group data in sequence based on the primitive group label corresponding to each primitive group data.

[0129] Among them, since the multiple data to be distributed in the primitive group data include at least one primitive element, at this time, in the process of the blocker sequentially processing the distribution of each primitive group data, for the target primitive group data currently being processed, the distribution process includes: determining the order corresponding to the at least one primitive element based on the distribution order of the multiple data to be distributed corresponding to the target primitive group data; based on the order, the blocker sequentially determines the block corresponding to each primitive element, and writes each primitive element into the corresponding polygon list.

[0130] In some embodiments, a polygon list corresponding to each tile is pre-initialized in the system memory. In the process of determining the tile corresponding to each metadata based on the order of precedence in the above-mentioned primitive group, the metadata of the tile can be written into the polygon list corresponding to the tile initialized in the system memory. The order of precedence between the metadata in the polygon list is the same as the order of precedence of the metadata in the distribution order.

[0131] Based on the above embodiment, since the block corresponding to each of the primitive data in the target primitive group data is determined in sequence by the block divider based on the distribution order; each of the primitive data in the target primitive group data is written into the polygon list of the corresponding block, in this way, the relative order between at least two distributed data belonging to a primitive group in the polygon list is the same as the previous distribution order.

[0132] In some embodiments, when writing the primitive data, it is also necessary to write the primitive group tag into the polygon list. To facilitate understanding of this solution, the following embodiments will take a primitive data as an example to illustrate the writing process of the primitive data and the primitive group tag. The above-mentioned step of writing each primitive data in the target primitive group data into the polygon list of the corresponding tile can be implemented by steps S3011 to S3012.

[0133] Step S3011: In response to determining that the primitive data belongs to a target tile and the primitive group tag of the target primitive group data does not exist in the polygon list of the target tile, write the primitive group tag of the target primitive group data into the polygon list of the target tile.

[0134] In some embodiments, when the blocker determines that the current primitive data belongs to a target tile among multiple tiles, it is also necessary to determine whether the primitive group label of the target primitive group data already exists in the polygon list corresponding to the target tile. The purpose of determining whether the primitive group label of the target primitive group data already exists in the polygon list is to determine whether the target primitive group data corresponding to the current primitive data has completed the writing of the primitive group label, that is, to determine whether the target primitive group data corresponding to the current primitive data is already in the writing process of the data to be distributed.

[0135] Among them, when the pixel group label of the target pixel group data already exists in the polygon list corresponding to the target tile, it means that the target pixel group data already has target distribution data written into the polygon list corresponding to the target tile; at this time, the pixel data can continue to be written into the polygon list corresponding to the target tile.

[0136] Among them, when the primitive group label of the target primitive group data does not exist in the polygon list corresponding to the target tile, it means that the primitive group data of the target primitive group data has not yet been written into the polygon list corresponding to the target tile, and the primitive group labels and primitive data of other primitive group data may exist in the polygon list corresponding to the target tile. If the current primitive data is directly written into the polygon list corresponding to the target tile, it will cause the current primitive data to be mistakenly regarded as belonging to other primitive group data, and then the order of the current primitive data cannot be restored normally, affecting the subsequent rendering process. Therefore, it is necessary to write the primitive group label of the target primitive group data into the polygon list of the target tile to form a boundary with other primitive group data.

[0137] Step S3012: write at least one target distribution data belonging to the target tile in sequence after the primitive group tag of the target primitive group data in the polygon list of the target tile.

[0138] In some embodiments, since the primitive group tag of the target primitive group data has been written in the polygon list of the target tile, in the subsequent distribution process of the target primitive group data, if there is still primitive data belonging to the target tile, the primitive data is directly written into the polygon list of the target tile without writing the primitive group tag of the target primitive group data again.

[0139] It should be understood that in the process of distributing a new primitive group data through the block splitter, the new primitive group tag corresponding to the new primitive group data will not exist in any polygon list. That is to say, in the embodiment of the present application, after the primitive group tag of the target primitive group data is written into the polygon list of the target tile, all target distribution data belonging to the target tile will be written into the polygon list of the target tile in sequence; at the same time, different primitive group data correspond to different primitive group tags, and the primitive group tag is the unique identifier of the primitive group data (the data to be distributed included in the primitive group data).

[0140] In an embodiment of the present application, the primitive group label of the primitive group corresponding to the target distribution data in the polygon list provided by the present application is located before the target distribution data. At the same time, only one primitive group label is set for the target distribution data belonging to the same primitive group. In this way, the list length of the polygon list can be reduced. At the same time, by setting the primitive group label of the primitive group corresponding to the target distribution data, in this way, in the process of the rasterization processing pipeline merging the polygon lists corresponding to the current tiles in each blocker, the order of the target distribution data can be clarified, thereby effectively restoring the original input order.

[0141] In some embodiments, the method further includes: for each of the blockers, when there is tuple group data including a state change data packet in at least one tuple group data of the blocker, writing the state change data packet into a polygon list of each of the tiles corresponding to the blocker; wherein the order of the state change data packets in the polygon list of each of the tiles is the same as the distribution order of the state change data packets in the corresponding tuple group data.

[0142] The plurality of data to be distributed may include, in addition to a plurality of graphic elements, a state change data packet, and the state change data packet is used to control the pipeline state of a subsequent rasterization processing pipeline.

[0143] In some embodiments, for each blocker, the blocker receives at least one primitive group data output by the geometry processing pipeline, i.e., at least one primitive group and a corresponding primitive group label, wherein each primitive group includes multiple data to be distributed (including at least one primitive data and possibly including a state change data packet).

[0144] In this embodiment, when the blocker distributes the primitive group data in sequence, if there is a state change data packet in multiple data to be distributed in the current primitive group data, it is necessary to write the state change indication packet in the target primitive group data into the polygon list corresponding to all the tiles corresponding to the blocker.

[0145] See also Figure 3C , which shows a schematic diagram of a blocker distributing two primitive groups including state change data packets. Among them, the blocker 322 receives two primitive groups 311 output by the corresponding geometry processing pipeline, and the corresponding primitive group labels are L1 and L2. The primitive group L1 includes 4 primitive data, P1, P2, P3, S0, P4, arranged in sequence, and 1 state change data packet. The primitive group L2 includes 3 primitive data, P5, P6, P7, arranged in sequence. The blocker 322 can determine the tile to which the primitive data in each primitive group belongs, and write the primitive data into the polygon list corresponding to the tile in the system memory 323. The method of writing the primitive data is the same as that in the above-mentioned embodiment. Figure 3A Similarly, the detailed writing method can refer to the description in the above embodiment.

[0146] With the above Figure 3A The difference is that the first primitive group L1 also carries a state change data packet S0. At this time, the blocker 322 needs to write the state change data packet S0 into the polygon list corresponding to each tile corresponding to the blocker 322, such as Figure 3CThe polygon list 3231, polygon list 3232, ..., polygon 323M all contain the state change data packet S0. It can be seen that the order of the state change data packet S0 in each polygon list is the same as the distribution order of the state change data packet S0 in the primitive group data L1.

[0147] It should be understood that if there is a tile that does not overlap with any primitive data in the first primitive group, the block splitter still needs to write the state change data packet S0 into the polygon list corresponding to the tile, and write the primitive group label L1 before the state change data packet S0.

[0148] Based on the above embodiment, since the state change data packet is output to the polygon list of each tile corresponding to the block splitter, in this way, during the process of rendering the current tile in the rasterization processing pipeline, the state change data packet can still be obtained by merging all polygon lists of the current tile, thereby completing the state update of the rasterization processing pipeline; at the same time, since the primitive group label of the primitive group where the state change data packet is located is written before writing the state change data packet, it can be ensured that the rasterization processing pipeline can complete the pipeline state update at the exact time point.

[0149] In some embodiments, the polygon list ends with a terminator; in the process of the rasterization processing pipeline taking out the data to be distributed from the polygon list, the terminator is used to indicate whether the data to be distributed in the polygon list is completely taken out.

[0150] In some embodiments, in the process of initializing the polygon list of each tile corresponding to each blocker in the system memory, a terminator is pre-set at the end of the polygon list. In the process of the rasterization processing pipeline processing the rendering task of the current tile, the polygon list corresponding to the current tile can be accessed in the system memory, and then all the data to be distributed corresponding to the current tile can be extracted. The above terminator can be used to indicate whether the data to be distributed in the polygon list is completely taken out. Exemplarily, the terminator can be embodied in the form of "end".

[0151] See also Figure 4A , which shows a schematic diagram of a rasterization processing pipeline accessing a polygon list of a current tile. The current graphics processing pipeline includes N blockers, namely blockers 411 to 41N, and the blockers correspond to M polygon lists in the system memory, that is, the current graphics processing pipeline divides the screen into M tiles; the polygon list corresponding to the first blocker includes 4211 to 421M; the polygon list corresponding to the second blocker includes 4221 to 422M; and so on, the polygon list corresponding to the Nth blocker includes 42N1 to 42NM.

[0152] It can be seen that the end of the polygon list is the terminator "end", which is used to determine the end of the current polygon list. Taking polygon list 4211 as an example, in the process of the rasterization processing pipeline taking out the primitive data from the polygon list 4211, the three primitive data "P" after L1 can be taken out in sequence. At this time, due to the extraction of the primitive group label and primitive data, the terminator "end" in the polygon list has been moved to the head of the polygon list 4211, that is, there is only one element "end" in the polygon list 4211, and the rasterization processing pipeline can determine that the data to be distributed in the polygon list 4211 has been completely taken out.

[0153] Figure 4B is an optional flow chart of the method for distributing graphics elements provided in the embodiment of the present application, and the method can be executed by a processor of a computer device. Figure 1D , Figure 1D The step of obtaining the distributed data corresponding to the tile from the polygon list corresponding to the tile through the rasterization processing pipeline will be combined with Figure 4B The steps shown are explained.

[0154] Step S401, traverse the primitive group tag in the header of each polygon list corresponding to the tile through the rasterization processing pipeline, and take out the distributed data corresponding to the target primitive group tag from the polygon list corresponding to the target primitive group tag until the distributed data does not exist in each polygon list.

[0155] The target primitive group label is determined based on the sequence of primitive group labels in the headers of the polygon lists.

[0156] In some embodiments, when the rasterization pipeline processes the rendering task of the tile, it is necessary to obtain the distributed data corresponding to the tile from each of the polygon lists corresponding to the tile.

[0157] At this time, the rasterization processing pipeline can traverse the primitive group tags in the header of each polygon list corresponding to the tile; based on the order of the primitive group tags, determine the primitive group tag with the first order as the target primitive group tag; and take out the distributed data corresponding to the target primitive group tag from the polygon list corresponding to the target primitive group tag, wherein, in the process of taking out the distributed data corresponding to the target primitive group tag from the polygon list, in response to the header of the polygon list being other primitive group tags, it is determined that the distributed data corresponding to the target primitive group tag has been completely taken out; or, in response to the header of the polygon list being a preset terminator (or the polygon list is empty), it is determined that the distributed data corresponding to the target primitive group tag has been completely taken out. The rasterization processing pipeline repeatedly executes the steps of determining the target primitive group tag and taking out the distributed data corresponding to the target primitive group tag based on the latest polygon lists until the distributed data does not exist in all polygon lists corresponding to the tile.

[0158] In some embodiments, the above-mentioned traversal of the primitive group tag in the header of each polygon list corresponding to the tile through the rasterization processing pipeline can be implemented through steps S4011 to S4013, and the distributed data corresponding to the target primitive group tag is taken out from the polygon list corresponding to the target primitive group tag until the distributed data does not exist in each polygon list.

[0159] Step S4011: Obtain, through the rasterization processing pipeline, a primitive group tag located at the header of each polygon list corresponding to the tile.

[0160] Step S4012: When there is at least one primitive group tag in each of the polygon lists, determine the target primitive group tag based on the order of the acquired primitive group tags, take out the target primitive group tag and the distributed data corresponding to the target primitive group tag in turn in the polygon list where the target primitive group tag is located, and return to execute the primitive group tag at the header of each polygon list corresponding to the tile obtained through the rasterization processing pipeline.

[0161] Step S4013: When there are no primitive group labels and distributed data in each of the polygon lists, it indicates that the distribution process of each of the distributed data has been completed.

[0162] For example, see Figure 4ATaking the rendering task of the first tile processed by the rasterization processing pipeline as an example, the rasterization processing pipeline 145 needs to merge the polygon lists corresponding to N tiles from polygon list 4211 to polygon list 42NM. To facilitate understanding of this solution, the polygon list corresponding to the third tile to the polygon list corresponding to the N-1th tile do not contain the distributed data corresponding to the first tile. During the first traversal of the rasterization processing pipeline, it can be determined that the distributed data corresponding to the tile exists in polygon list 4211, polygon list 4221 and polygon list 42NM, and three primitive group labels L1, L3 and L4 are obtained. Based on the order of the primitive group labels, L1 is used as the target primitive group label, and three primitive data "P" are taken out from polygon list 4211 in sequence. At this time, please refer to Figure 4C In the polygon list schematic diagram 1 shown, the end symbol "end" of polygon list 4211 is already at the head of the table, indicating that the distributed data corresponding to the tile no longer exists in polygon list 4211; at this time, during the second traversal of the rasterization processing pipeline, it can be determined that the distributed data corresponding to the tile exists in polygon list 4221 and polygon list 42NM, and two primitive group labels L3 and L4 are obtained. Based on the order of the primitive group labels, L3 is used as the target primitive group label, and one primitive data "P" is taken out from polygon list 4221 in turn, see Figure 4D The polygon list shown is schematic Figure 2 At this time, the primitive group tag "L7" of polygon list 4221 is already at the head of the table, indicating that the distributed data corresponding to the tile still exists in polygon list 4211; during the third traversal of the rasterization processing pipeline, it can be determined that the distributed data corresponding to the tile exists in polygon list 4221 and polygon list 42NM, and two primitive group tags L7 and L4 are obtained. Based on the order of the primitive group tags, L4 is used as the target primitive group tag, and one primitive data "P" is taken out from polygon list 42N1 in turn, see Figure 4E In the polygon list schematic diagram 3 shown, at this time, the primitive group label "L8" of polygon list 42N1 is already at the header, indicating that the distributed data corresponding to the tile still exists in polygon list 42N1; and so on, until the header of each polygon list from polygon list 4211 to polygon list 42NM is the end symbol "end", ending the rasterization processing pipeline's reading process of the distributed data of the tile.

[0163] In an embodiment of the present application, by setting the primitive group label of each primitive group corresponding to each distributed data before the distributed data in the polygon list, in this way, in the process of the rasterization processing pipeline merging the polygon list corresponding to the current tile, the order between the various distributed data can be clarified, thereby effectively restoring the original input order.

[0164] Based on the foregoing embodiments, an embodiment of the present application provides a graphic element distribution device, which includes the units included and the modules included in the units, and can be implemented by a processor in a computer device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0165] Figure 5 A schematic diagram of the composition structure of a primitive distribution device provided in an embodiment of the present application, wherein the primitive distribution device is applied to a graphics processor, wherein the graphics processor performs primitive distribution based on at least two blockers in a tile rendering TBR architecture, wherein each blocker corresponds to one or more geometry processing pipelines, such as Figure 5 As shown, the primitive distribution device 500 includes: a geometry processing pipeline 510, a blocker 520, and a rasterization processing pipeline 530, wherein:

[0166] The geometry processing pipeline 510 is used to output at least one primitive group data sent by the primitive distribution module to each of the blockers; the primitive group data includes a plurality of to-be-distributed data with a distribution order;

[0167] A block divider 520 is used to distribute the multiple data to be distributed in each of the primitive groups based on the distribution order, and generate a polygon list for each tile; the polygon list includes the distributed data corresponding to the tile;

[0168] The rasterization processing pipeline 530 is used for acquiring, for each of the tiles, the distributed data corresponding to the tile from each of the polygon lists corresponding to the tile, so as to perform rasterization processing on the tile.

[0169] In some embodiments, the primitive group data further includes a primitive group tag, and the primitive group tag is used to represent the sequence between the primitive group data.

[0170] In some embodiments, the graphic element distribution device 500 includes: a graphic element distribution module.

[0171] The primitive distribution module is used to group multiple original primitive data in the original input order to obtain at least one primitive group and a primitive group label corresponding to each primitive group; the primitive group includes multiple to-be-distributed data in the distribution order, and the primitive group label is used to represent the position of the multiple to-be-distributed data in the original input order;

[0172] The primitive distribution module is used to output a primitive group and a primitive group label corresponding to the primitive group to the geometry processing pipeline.

[0173] In some embodiments, the at least one primitive group satisfies at least one of the following preset grouping conditions:

[0174] The amount of data to be distributed in each of the graphic element groups is the same;

[0175] The number of mesh shader working groups corresponding to the data to be distributed in each of the primitive groups is the same.

[0176] In some embodiments, the primitive distribution module is further used to group the plurality of original primitive metadata based on a preset block size and the original input order to obtain the at least one primitive group and a primitive group label corresponding to each primitive group.

[0177] In some embodiments, the primitive distribution module is also used to obtain the workgroup label of the mesh shader workgroup corresponding to each of the primitive primitive metadata; based on a preset number of workgroups, the workgroup label of each of the primitive primitive metadata and the original input order, the multiple primitive primitive metadata are grouped to obtain the at least one primitive group and the primitive group label corresponding to each of the primitive groups.

[0178] In some embodiments, the primitive distribution module is further used to output primitive groups and primitive group labels corresponding to the primitive groups to the geometry processing pipeline based on a load balancing strategy.

[0179] In some embodiments, the primitive distribution module is further used to determine the label to be assigned corresponding to each of the geometry processing pipelines based on the primitive group label corresponding to the primitive group and the number of the geometry processing pipelines; for each of the geometry processing pipelines, output the label to be assigned and the primitive group corresponding to the label to be assigned to the geometry processing pipeline.

[0180] In some embodiments, the primitive distribution module is further used to obtain load information of each of the geometry processing pipelines; and based on the load information of the geometry processing pipelines, output primitive groups and primitive group labels corresponding to the primitive groups to the geometry processing pipelines.

[0181] In some embodiments, for each of the blockers, when there is target primitive group data in at least one primitive group data of the blocker, the polygon list of the target tile corresponding to the blocker includes the primitive group label of the target primitive group data and each target distribution data belonging to the target tile in the target primitive group data; wherein the target primitive group data is primitive group data in which there is at least one target distribution data belonging to the target tile; the order of each target distribution data in the polygon list is the same as the distribution order; and the primitive group label of the target primitive group data is located before each target distribution data.

[0182] In some embodiments, the blocker is also used to process the distribution process of each of the primitive group data in sequence based on the primitive group label corresponding to each of the primitive group data; wherein, for the distribution process of the target primitive group data, the blocker is also used to determine the tiles corresponding to each of the primitive data in the target primitive group data in sequence based on the distribution order; and write each of the primitive data in the target primitive group data into the polygon list of the corresponding tile.

[0183] In some embodiments, the blocker is further used to, in response to determining that the primitive data belongs to a target tile and that the primitive group tag of the target primitive group data does not exist in the polygon list of the target tile, write the primitive group tag of the target primitive group data into the polygon list of the target tile; and write at least one target distribution data belonging to the target tile in sequence after the primitive group tag of the target primitive group data in the polygon list of the target tile.

[0184] In some embodiments, the blocker is further used to, when there is tuple group data including a state change data packet in at least one tuple group data of the blocker, write the state change data packet into a polygon list of each of the tiles corresponding to the blocker; wherein the order of the state change data packets in the polygon list of each of the tiles is the same as the distribution order of the state change data packets in the corresponding tuple group data.

[0185] In some embodiments, each polygon list ends with a terminator; in the process of the rasterization processing pipeline taking out the data to be distributed from the polygon list, the terminator is used to indicate whether the data to be distributed in the polygon list is completely taken out.

[0186] In some embodiments, the rasterization processing pipeline is also used to traverse the primitive group tag located at the header of each of the polygon lists corresponding to the tile, and take out the distributed data corresponding to the target primitive group tag from the polygon list corresponding to the target primitive group tag until the distributed data does not exist in each of the polygon lists; wherein the target primitive group tag is determined based on the order of the primitive group tags in the headers of each of the polygon lists.

[0187] In some embodiments, the rasterization processing pipeline is also used to obtain the primitive group tag located at the header of each polygon list corresponding to the tile; when there is at least one primitive group tag in each polygon list, the target primitive group tag is determined based on the order of the obtained primitive group tags, and the target primitive group tag and the distributed data corresponding to the target primitive group tag are sequentially taken out from the polygon list where the target primitive group tag is located, and the process of obtaining the primitive group tag located at the header of each polygon list corresponding to the tile through the rasterization processing pipeline is returned; when there is no primitive group tag and distributed data in each polygon list, it indicates that the distribution process of each distributed data has been completed.

[0188] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the device provided in the embodiment of the present application can be used to execute the method described in the above method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0189] It should be understood that in the embodiments of the present application, if the above-mentioned primitive distribution method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific hardware, software or firmware, or any combination of hardware, software, and firmware.

[0190] An embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0191] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above method are implemented. The computer-readable storage medium can be transient or non-transient.

[0192] An embodiment of the present application provides a graphics processor, which is used to execute part or all of the steps in the above method.

[0193] An embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0194] The embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, some or all of the steps in the above method are implemented. The computer program product can be implemented specifically by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0195] It should be noted here that the description of the various embodiments above tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. The description of the above device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the embodiments of the device, storage medium, computer program and computer program product of this application, please refer to the description of the method embodiment of this application for understanding.

[0196] Figure 6 A hardware entity diagram of a computer device provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the hardware entity of the computer device 600 includes: a processor 601 and a memory 602, wherein the memory 602 stores a computer program that can be run on the processor 601, and the processor 601 implements the steps in the method of any of the above embodiments when executing the program.

[0197] The memory 602 stores computer programs that can be run on the processor. The memory 602 is configured to store instructions and applications executable by the processor 601. It can also cache data to be processed or processed by the processor 601 and various modules in the computer device 600 (for example, image data, audio data, voice communication data, and video communication data). This can be achieved through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0198] When the processor 601 executes the program, the steps of any of the above primitive distribution methods are implemented. The processor 601 generally controls the overall operation of the computer device 600.

[0199] An embodiment of the present application provides a computer storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the steps of the primitive distribution method of any of the above embodiments.

[0200] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0201] The processor may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understandable that the electronic device that implements the functions of the processor may also be other, and the embodiments of the present application are not specifically limited.

[0202] The above-mentioned computer storage medium / memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and the like; it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0203] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The serial numbers of the embodiments of the present application mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0204] It should be understood that, in this article, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0205] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0206] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0207] In addition, all functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. A person of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by hardware related to program instructions, and the above program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above method embodiments are executed; and the above storage medium includes: mobile storage devices, read-only memory (ROM), disks or optical disks, etc. Various media that can store program codes.

[0208] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0209] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for distributing graphic elements, characterized in that: Applied to a graphics processor, the graphics processor performs primitive distribution based on at least two blockers in a tile rendering TBR architecture, each of the blockers corresponding to one or more geometry processing pipelines, the method comprising: Outputting at least one primitive group data sent by the primitive distribution module to a corresponding blocker through a geometry processing pipeline; the primitive group data includes a plurality of to-be-distributed data with a distribution order; Distributing the plurality of data to be distributed in each of the primitive group data based on the distribution order by each of the block dividers to generate a polygon list for each tile; the polygon list includes the distributed data corresponding to the tile; For each of the tiles, the distributed data corresponding to the tile is obtained from each of the polygon lists corresponding to the tile through a rasterization processing pipeline to perform rasterization processing on the tile.

2. The method according to claim 1, characterized in that The primitive group data further includes a primitive group tag, and the primitive group tag is used to represent the sequence between the primitive group data.

3. The method according to claim 2, characterized in that The method further comprises: The primitive distribution module groups a plurality of original primitive data in an original input order to obtain at least one primitive group and a primitive group label corresponding to each primitive group; the primitive group includes a plurality of to-be-distributed data in a distribution order, and the primitive group label is used to represent the position of the plurality of to-be-distributed data in the original input order; The primitive group and the primitive group label corresponding to the primitive group are output to the geometry processing pipeline through the primitive distribution module.

4. The method according to claim 3, characterized in that The step of grouping a plurality of original graphic element data having an original input order by the graphic element distribution module to obtain at least one graphic element group and a graphic element group label corresponding to each graphic element group includes: The primitive distribution module groups the plurality of original primitive data based on a preset block size and the original input order to obtain the at least one primitive group and a primitive group label corresponding to each primitive group.

5. The method according to claim 3, characterized in that: The step of grouping a plurality of original graphic element data having an original input order by the graphic element distribution module to obtain at least one graphic element group and a graphic element group label corresponding to each graphic element group includes: Obtaining a workgroup tag of a mesh shader workgroup corresponding to each of the original graphics metadata; The primitive distribution module groups the multiple original primitive data based on a preset number of workgroups, a workgroup label of each of the original primitive data and the original input order to obtain at least one primitive group and a primitive group label corresponding to each of the primitive groups.

6. The method according to claim 3, characterized in that Outputting the primitive group and the primitive group label corresponding to the primitive group to the geometry processing pipeline through the primitive distribution module includes: Based on a load balancing strategy, the primitive group and the primitive group label corresponding to the primitive group are output to the geometry processing pipeline through the primitive distribution module.

7. The method according to claim 3, characterized in that Outputting the primitive group and the primitive group label corresponding to the primitive group to the geometry processing pipeline through the primitive distribution module includes: Determine a to-be-allocated label corresponding to each of the geometry processing pipelines based on the primitive group label corresponding to the primitive group and the number of the geometry processing pipelines; For each of the geometry processing pipelines, the to-be-assigned labels and the primitive groups corresponding to the to-be-assigned labels are output to the geometry processing pipeline through the primitive distribution module.

8. The method according to claim 3, characterized in that Outputting the primitive group and the primitive group label corresponding to the primitive group to the geometry processing pipeline through the primitive distribution module includes: Obtaining load information of each of the geometry processing pipelines; Based on the load information of each of the geometry processing pipelines, the primitive group and the primitive group tag corresponding to the primitive group are output to the geometry processing pipeline through the primitive distribution module.

9. The method according to claim 2, characterized in that: For each of the blockers, when there is target primitive group data in at least one primitive group data of the blocker, the polygon list of the target tile corresponding to the blocker includes the primitive group label of the target primitive group data and each target distribution data belonging to the target tile in the target primitive group data; Among them, the target primitive group data is primitive group data in which there is at least one target distribution data belonging to the target block; the order of each target distribution data in the polygon list is the same as the distribution order; the primitive group label of the target primitive group data is located before each target distribution data.

10. The method according to claim 9, characterized in that The plurality of data to be distributed include at least one primitive data; the plurality of data to be distributed in each primitive group data is distributed by the block divider based on the distribution order to generate a polygon list for each tile, including: Processing the distribution process of each of the primitive group data in sequence based on the primitive group label corresponding to each of the primitive group data by the block divider; Among them, for the distribution process of the target primitive group data, the block divider determines the block corresponding to each primitive element in the target primitive group data in turn based on the distribution order; and writes each primitive element in the target primitive group data into the polygon list of the corresponding block.

11. The method according to claim 10, characterized in that The step of writing each primitive data in the target primitive group data into a polygon list of a corresponding tile comprises: In response to determining that the primitive data belongs to a target tile and the primitive group tag of the target primitive group data does not exist in the polygon list of the target tile, writing the primitive group tag of the target primitive group data into the polygon list of the target tile; After the primitive group tag of the target primitive group data in the polygon list of the target tile, the at least one target distribution data belonging to the target tile is written in sequence.

12. The method according to any one of claims 9 to 11, characterized in that: The method further comprises: For each of the blockers, when there is a primitive group data including a state change data packet in at least one primitive group data of the blocker, write the state change data packet into a polygon list of each of the tiles corresponding to the blocker; The order of the state change data packets in the polygon list of each tile is the same as the distribution order of the state change data packets in the corresponding primitive group data.

13. The method according to any one of claims 9 to 11, characterized in that: Each polygon list ends with a terminator; in the process of the rasterization processing pipeline taking out the data to be distributed from the polygon list, the terminator is used to indicate whether the data to be distributed in the polygon list is completely taken out.

14. The method according to any one of claims 9 to 11, characterized in that: The obtaining the distributed data corresponding to the tile from each polygon list corresponding to the tile through the rasterization processing pipeline includes: Traversing the primitive group tag at the head of each polygon list corresponding to the tile through the rasterization processing pipeline, and taking out the distributed data corresponding to the target primitive group tag from the polygon list corresponding to the target primitive group tag, until the distributed data does not exist in each polygon list; The target primitive group label is determined based on the sequence of primitive group labels in the headers of the polygon lists.

15. The method according to claim 14, characterized in that The step of traversing the primitive group tag at the header of each polygon list corresponding to the tile through the rasterization processing pipeline, and taking out the distributed data corresponding to the target primitive group tag from the polygon list corresponding to the target primitive group tag until the distributed data does not exist in each polygon list, comprises: Acquire, through the rasterization processing pipeline, a primitive group tag located at the header of each polygon list corresponding to the tile; In the case that there is at least one primitive group tag in each of the polygon lists, the target primitive group tag is determined based on the order of the primitive group tags obtained, the target primitive group tag and the distributed data corresponding to the target primitive group tag are sequentially taken out from the polygon list where the target primitive group tag is located, and the primitive group tag located at the head of each polygon list corresponding to the tile is obtained through the rasterization processing pipeline and returned to execute; When the primitive group label and the distributed data do not exist in each of the polygon lists, it indicates that the distribution process of each of the distributed data has been completed.

16. A graphic element distribution device, characterized in that: Applied to a graphics processor, the graphics processor performs primitive distribution based on at least two blockers in a tile rendering TBR architecture, each of the blockers corresponding to one or more geometry processing pipelines; the device comprises: A geometry processing pipeline, configured to output at least one primitive group data sent by the primitive distribution module to a corresponding blocker; the primitive group data includes a plurality of to-be-distributed data with a distribution order; A block divider, configured to distribute a plurality of to-be-distributed data in each of the primitive groups based on the distribution order, and generate a polygon list for each tile; the polygon list includes the distributed data corresponding to the tile; The rasterization processing pipeline is used for acquiring the distributed data corresponding to each tile from each polygon list corresponding to the tile for performing rasterization processing on the tile.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, wherein: When the processor executes the program, the steps in the method according to any one of claims 1 to 15 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 1 to 15 are implemented.

19. A graphics processor, characterized in that: Used to perform the method according to any one of claims 1 to 15.

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