Method for realizing effective release of ferroelectric charges based on bit line segmentation and storage array

Abstract

The invention discloses a method for realizing effective release of ferroelectric charges based on bit line segmentation and a storage array, and the method comprises the steps: segmenting a column address through a transmission gate, dividing a bit line into at least two bit line segments, and when data reading is carried out on a storage unit far away from a global amplifier, carrying out data reading on the storage unit; the read memory cell is disconnected from the memory cell close to one side of the global amplifier by using the transmission gate, and the bit line is shortened, so that the parasitic capacitance of the bit line is also reduced, the voltage difference between two ferroelectric capacitors can be increased, and the data reading accuracy is further improved.

Description

Technical Field

[0001] The invention belongs to the field of storage technology, and in particular relates to a method for realizing effective release of ferroelectric charges based on bit line segmentation and a storage array. Background Art

[0002] Ferroelectric RAM (FRAM) is a type of random access memory that combines the fast read and write access of dynamic random access memory (DRAM) with the ability to retain data after power is turned off.

[0003] DRAM is the most common storage technology at present, but the process requirements of DRAM are very high. In order to reduce costs and simplify the process, researchers have invested a lot of research and development efforts. For example, considering that DRAM capacitors are difficult to make, there is currently a technology that uses a ferromagnetic structure as an information storage medium (MRAM), and another technology that uses a piece of ferroelectric material as a storage medium (FRAM), which is the ferroelectric memory mentioned in this solution. However, it is still very difficult for FRAM to achieve the density of DRAM. Since the current ferroelectric memory (FRAM) cannot be as dense as dynamic random access memory (DRAM) and static random access memory (SRAM) (that is, it cannot store as much data as them in the same space), it is impossible to completely replace DRAM and SRAM in a short time. However, since FRAM can store quickly with very low power requirements, it still has a very broad application prospect in small devices, such as personal digital assistants (PDAs), mobile phones, power meters, smart cards, etc.

[0004] There are generally two types of basic storage cells of ferroelectric memory, namely 1T1C structure and 2T2C structure. The former uses one transistor and one ferroelectric capacitor, while the latter uses two transistors and two ferroelectric capacitors. Although the 2T2C structure uses a larger area, since each storage cell contains two ferroelectric capacitors, the voltage difference between the two bit lines in the array will be larger, so the accuracy is higher when reading. Taking the storage cell of 2T2C structure as an example, the storage cell is a 2T2C structure composed of two ferroelectric capacitors and two NMOS tubes. WL is the word line, PL is the plate line, BLE and BLO are a pair of complementary bit lines used to transmit data, and the data is connected to the local amplifier LSA for amplification. The storage cell is composed of multiple storage array areas, and the LSA output data of multiple storage array areas is connected to the global amplifier GSA. The data comes out of GSA and passes through the data buffer BUFFER to input and output data. When the memory is read, PL is pulled to a high level to apply an external electric field to the ferroelectric capacitor. The external electric field will interact with the internal electric field of the ferroelectric material, changing the polarization in the material, thereby generating charges in the capacitor. The voltage of the bit line with more stored charge is greater than the voltage of the bit line with less stored charge. In the design of large-capacity memory, the bit line is generally longer, and the parasitic resistance and capacitance of the bit line corresponding to the memory array farthest from the GSA is relatively large. If the parasitic capacitance of the bit line is too large, the voltage difference between BLE and BLO will become smaller after the ferroelectric capacitor releases the charge. LSA pulls the higher voltage to a high level and the lower voltage to a low level based on the voltage difference between BLE / BLO. If the voltage difference is too small, the sensitivity of LSA is not high, which will directly lead to inaccurate data read by the memory. Summary of the invention

[0005] The object of the present invention is to provide a method and a storage array for effectively releasing ferroelectric charges based on bit line segmentation in order to solve the above problems.

[0006] A memory array based on bit line segmentation to achieve effective release of ferroelectric charge, comprising a plurality of memory cells constituting the memory array, each memory cell comprising a ferroelectric capacitor and a transistor, each memory cell being connected to a word line WL, a plate line PL and a bit line, each memory cell being connected to a global amplifier GSA through a bit line, the bit line comprising a trunk bit line GBL and a branch bit line BL corresponding to each memory cell respectively, the branch bit line BL being connected to a local amplifier LSA, data of the memory cell being transmitted to the local amplifier LSA through the branch bit line BL for amplification, and then transmitted to the global amplifier GSA through the trunk bit line GBL to achieve data output of the memory array;

[0007] At least one group of transmission gates is inserted into the main bit line GBL to divide the storage array into at least two sections in the column direction. Each group of transmission gates corresponds to a bit line segment UBL away from the global amplifier GSA. When reading data from the storage unit corresponding to the bit line segment UBL, the corresponding transmission gate is turned off until the corresponding local amplifier LSA amplifies the voltage difference of the branch bit line BL and then restores the transmission gate to the on state.

[0008] By segmenting the bit line through a transmission gate and proposing a corresponding control method, the parasitic capacitance of the bit line is reduced when reading data from a storage unit, the reading accuracy of the local amplifier LSA is improved, and the sensitivity requirement for the local amplifier can be reduced.

[0009] In the above-mentioned memory array for effectively releasing ferroelectric charge based on bit line segmentation, each bit line segment UBL has a pre-discharge transistor for pre-discharging the corresponding bit line segment before reading data from the memory cell. The voltage of the bit line segment in the suspended state is discharged to zero in advance through the pre-discharge action, so that when the data is started to be read, the voltage on the bit line segment UBL is the high level and low level of the corresponding branch bit line BLE / BLO after LSA amplification, avoiding being affected by the original voltage of the bit line segment UBL.

[0010] The pre-discharge process is: GNDUBL is pulled to a high level, the two NMOSs M1 and M2 are turned on, and UBLE / UBLO is pulled to a low level (VSS). The pre-discharge transistor is also connected to the peripheral drive circuit. When discharge is required, the peripheral drive circuit controls the pre-discharge transistor to pre-discharge the bit line segment.

[0011] In the above-mentioned memory array for realizing effective release of ferroelectric charge based on bit line segmentation, a first group of transmission gates is provided on the main bit line GBL, and the transmission gates in the group divide the memory array into two sections in the column direction.

[0012] This solution divides the storage array into two halves. When the memory selects to read the upper half of the storage array, the transmission gate is turned off until the local amplifier amplifies the data. By disconnecting the bit line, the parasitic capacitance of the bit line is reduced, the bit line voltage difference is increased, and the accuracy of data reading is improved.

[0013] In the above-mentioned memory array for realizing effective release of ferroelectric charge based on bit line segmentation, the main bit line GBL also has second to Nth groups of transmission gates, N being greater than or equal to 2;

[0014] Each group of transmission gates divides the bit line segment where it is located into two segments again, so that the column direction of the memory array is divided into N+1 segments through N groups of transmission gates.

[0015] This solution further divides the storage array into multiple segments, which is suitable for longer storage array scenarios.

[0016] In the above-mentioned memory array for realizing effective release of ferroelectric charge based on bit line segmentation, each memory cell adopts a 2T2C structure including two transistors and two ferroelectric capacitors;

[0017] Each storage unit corresponds to two branch bit lines BLE and BLO. The local amplifier LSA is used to amplify the voltage difference between the two branch bit lines BLE and BLO, and pull the relatively higher voltage of the two branch bit lines to a high level and the relatively lower voltage to a low level.

[0018] A column of memory cells shares a trunk bit line GBL, each column of memory cells corresponds to two trunk bit lines GBLE and GBLO, and a set of transmission gates is composed of two sets of transistors correspondingly arranged on the two trunk bit lines GBLE and GBLO;

[0019] The two groups of transistors in the transmission gate group work together to divide the corresponding segment of the bit line into two segments. For example, if there is only one group of transmission gates, the group of transmission gates divides a segment of the main bit line GBL into two segments. If there is a second group of transmission gates, the first group of transmission gates divides a segment of the main bit line GBL into two segments, and the second group of transmission gates further divides one segment of the segmented bit line into two segments.

[0020] In the above-mentioned memory array for realizing effective release of ferroelectric charge based on bit line segmentation, each memory cell adopts a 1T1C structure including a transistor and a ferroelectric capacitor;

[0021] Alternatively, each memory cell adopts a 1T2C structure including one transistor and two ferroelectric capacitors;

[0022] Each storage unit corresponds to a branch bit line, and the local amplifier LSA is used to amplify the voltage difference between the branch bit line and the reference voltage;

[0023] Each column of storage cells corresponds to a main bit line, and a group of transmission gates is composed of a group of transistors that divide a corresponding segment of the bit line into two segments.

[0024] In the above-mentioned storage array based on bit line segmentation to realize effective release of ferroelectric charge, each group of transistors includes two MOS tubes arranged opposite to each other, the input and output ends of the MOS tubes are connected in series to the corresponding trunk bit lines, and the control end is connected to the peripheral driving circuit.

[0025] In the above-mentioned memory array based on bit line segmentation to realize effective release of ferroelectric charge,

[0026] Each group of transistors has two MOS tubes, one is an NMOS tube and the other is a PMOS tube;

[0027] When reading data from the storage unit corresponding to the bit line segment, the peripheral driving circuit determines whether the corresponding transmission gate needs to be turned off according to the preset, and when it needs to be turned off, controls the corresponding transmission gate to be turned off, and restores the transmission gate to the on state after a set time according to the control timing.

[0028] A method for effectively releasing ferroelectric charge based on bit line segmentation, wherein a storage array of a ferroelectric memory is divided into N+1 segments by transmission gates in a column direction to obtain N+1 bit line segments, where N represents the number of transmission gate groups;

[0029] The method includes:

[0030] When reading the storage cell data corresponding to the non-first bit line segment UBL, the corresponding transmission gate is turned off and the corresponding bit line segment is pre-discharged;

[0031] Pull the corresponding word line WL to a high level to turn on the transistor of the memory cell, pull the corresponding plate line PL to a high level to apply an external electric field to the ferroelectric capacitor of the memory cell, so that the ferroelectric capacitor generates charge and outputs data to the corresponding branch bit line BL;

[0032] The local amplifier LSA amplifies the voltage difference of the branch bit line BL;

[0033] After the local amplifier LSA amplifies the voltage difference of the branch bit line, the corresponding transmission gate is restored to the on state.

[0034] In the above-mentioned method for realizing effective release of ferroelectric charge based on bit line segmentation,

[0035] When reading the storage unit data corresponding to the non-first bit line segment UBL, it is determined whether to turn off the corresponding transmission gate according to the preset, and when the corresponding transmission gate is turned off, the transmission gate is restored to the on state after the set time according to the control timing;

[0036] Each storage cell in the storage array is a 2T2C structure, each storage cell corresponds to two branch bit lines BLE and BLO, and the local amplifier LSA amplifies the voltage difference between the two branch bit lines BLE and BLO;

[0037] Alternatively, each memory cell in the memory array is of 1T1C structure or 1T2C structure, each memory cell corresponds to a branch bit line BL, and the local amplifier LSA amplifies the voltage difference between the branch bit line BL and the reference voltage ref.

[0038] The advantages of the present invention are:

[0039] This solution uses transmission gates to segment the column address and divide the bit line into at least two bit line segments. When reading data from a storage unit far away from the global amplifier, the transmission gate is used to disconnect the storage unit to be read from the storage unit close to the global amplifier. Since the bit line is shortened, the parasitic capacitance of the bit line is also reduced, which can increase the voltage difference between the two ferroelectric capacitors, thereby improving the accuracy of data reading.

[0040] The general state of the transmission gate is the normally-on state. The corresponding transmission gate is turned off for a short time when the corresponding storage unit is read, which will not cause any impact on the use of the memory.

[0041] A transmission gate is designed to consist of two transistors, an NMOS tube and a PMOS tube. While the transmission gate is realized by the MOS tube to increase the branch bit line voltage difference, the problem of single transistor conduction voltage drop is well solved, thereby ensuring the accuracy of data transmission and avoiding the influence of the MOS tube on data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a 2T2C structure array of a ferroelectric memory having a group of transmission gates of the present invention;

[0043] Figure 2 A schematic diagram of a 2T2C structure array of a ferroelectric memory device of the present invention having two groups of transmission gates;

[0044] Figure 3 A schematic diagram of a 1T1C structure array of a ferroelectric memory having a group of transmission gates of the present invention;

[0045] Figure 4 A schematic diagram of a 1T2C structure array of a ferroelectric memory having a group of transmission gates of the present invention;

[0046] Figure 5 for Figure 1 The transmission gate circuit structure diagram in the array structure shown;

[0047] Figure 6 for Figure 1 The pre-discharge circuit structure diagram in the array structure shown.

[0048] Branch bit line BL; trunk bit line GBL; bit line segment UBL; word line WL; plate line PL; local amplifier LSA; global amplifier GSA. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] like Figure 1As shown, the present scheme proposes a memory array based on bit line segmentation to realize effective release of ferroelectric charge, including a plurality of memory cells constituting the memory array, each memory cell including a ferroelectric capacitor and a transistor, each memory cell being connected to a word line WL, a plate line PL and a bit line, and each memory cell being connected to a global amplifier GSA through a bit line.

[0051] Among them, the bit lines include a main bit line GBL and a branch bit line BL corresponding to each storage cell respectively. The branch bit line BL is connected to a local amplifier LSA. The data of the storage cell is transmitted to the local amplifier LSA through the branch bit line BL for amplification and then transmitted to the global amplifier GSA through the main bit line GBL to realize data output of the storage array.

[0052] In particular, at least one group of transmission gates is inserted into the main bit line GBL to divide the memory array into at least two sections in the column address direction, and each group of transmission gates corresponds to a bit line segment UBL away from the global amplifier GSA. Figure 1 In the example, there is a group of transmission gates on the main bit line GBL, and the storage array is divided into two sections by the transmission gates in the group. The transmission gates correspond to the upper bit line segment UBL. Figure 1 It is a 2T2C structure, so each trunk bit line GBL has two bit lines, GBLE and GBLO, and each segment bit line UBL has two bit lines, UBLE and UBLO.

[0053] When data is read from a storage unit corresponding to a bit line segment, the corresponding transmission gate is turned off until the corresponding local amplifier LSA amplifies the voltage difference of the branch bit line and then restores the transmission gate to the on state.

[0054] Figure 1 The example of a main bit line having a group of transmission gates is taken as an example. In actual implementation, the main bit line may also have the second to Nth groups of transmission gates, N is greater than or equal to 2, and each group of transmission gates divides the bit line segment UBL where it is located into two segments again, so that the column direction of the storage array is divided into N+1 segments through N groups of transmission gates. Figure 2 As shown, when there are two groups of transmission gates in the circuit, the storage array will be divided into three sections. The lower group of transmission gates corresponds to the middle bit line segment (UBLE2, UBLO2), and the upper group of transmission gates divides the upper bit line segment (UBLE 1+UBLE2, UBLO1+UBLO2) into two sections again. The upper group of transmission gates corresponds to the uppermost bit line segment (UBLE1, UBLO1). The specific number of transmission gates is not limited here, but it is less than the number of rows of the storage array. It is preferred that the transmission gates are evenly arranged in the array. For example, when there is one group of transmission gates, they are set in the middle of the bit line to evenly divide the array into two sections in the column direction. If there is no condition for even distribution, it can be as even as possible.

[0055] like Figure 1 and Figure 2 Each storage unit adopts a 2T2C structure including two transistors (NMOS tubes) and two ferroelectric capacitors; each storage unit corresponds to two branch bit lines BL, BLE and BLO, and the local amplifier LSA is used to amplify the voltage difference between the two branch bit lines BLE and BLO. Specifically, the local amplifier LSA pulls the relatively higher voltage of the two branch bit lines to a high level and the relatively lower voltage to a low level.

[0056] A column of memory cells shares a main bit line GBL, and each column of memory cells corresponds to two main bit lines GBLE and GBLO. A set of transmission gates is composed of two sets of transistors correspondingly arranged on the two main bit lines GBLE and GBLO; the two sets of transistors in the transmission gate set work together to divide the corresponding bit line into two sections. If Figure 1 The set of transmission gates shown in the figure divides the main bit line into two sections. Figure 2 Also shown is a second set of transfer gates, which further divide the bit line segment into two segments.

[0057] In another embodiment, if Figure 3 , Figure 4 As shown, each memory cell adopts a 1T1C structure including a transistor and a ferroelectric capacitor; or, each memory cell adopts a 1T2C structure including a transistor and two ferroelectric capacitors. In this example, each memory cell corresponds to a branch bit line BL, and the local amplifier LSA is used to amplify the voltage difference between the branch bit line BL and the reference voltage ref; specifically, the local amplifier LSA amplifies the voltage difference between the bit line voltage and the reference voltage. Each column of memory cells corresponds to a main bit line GBL, and a group of transmission gates is composed of a group of transistors that divide the corresponding bit line into two sections.

[0058] Specifically, using Figure 1 Take the 2T2C structure and a set of transmission gates shown in the figure as an example. Figure 5 As shown, each group of transistors includes two MOS tubes M3, M4, M5, M6 arranged oppositely. Since each column in the 2T2C structure has two trunk bit lines GBLE and GBLO, a group of transmission gates includes two groups of transistors, and one group of transistors corresponds to one trunk bit line. Figure 5In the embodiment, two MOS transistors M3 and M4 form a group of transistors connected in series on the main bit line GBLE and corresponding to the bit line segment UBLE, and two MOS transistors M5 and M6 form a group of transistors connected in series on the main bit line GBLO and corresponding to the bit line segment UBLO. The input and output ends of the MOS transistors are connected in series to the corresponding main bit line, and the control end is connected to the peripheral drive circuit, so that when reading data from the storage unit of the corresponding bit line segment, the peripheral drive circuit controls the corresponding transmission gate to be turned off until the voltage difference of the branch bit line of the local amplifier LSA is restored to the on state of the transmission gate. In addition, Figure 5 As shown, each group of transistors has two MOS tubes, one is an NMOS tube and the other is a PMOS tube. This design can solve the problem of MOS tube conduction voltage drop and avoid the influence of the MOS tube itself set on the bit line on data transmission, that is, while achieving the purpose, overcome the influence of the means used to achieve the purpose on the original circuit.

[0059] Furthermore, if Figure 6 As shown, each bit line segment UBL is connected in series with a pre-discharge transistor for pre-discharging the corresponding bit line segment before reading data from the storage cell. The pre-discharge process is: GNDUBL is pulled to a high level, the two NMOSs M1 and M2 are turned on, and UBLE / UBLO is pulled to a low level (VSS). The pre-discharge transistor is also connected to the peripheral drive circuit. When discharge is required, the peripheral drive circuit controls the pre-discharge transistor to pre-discharge the corresponding bit line segment.

[0060] Specifically, the method for effectively releasing ferroelectric charges based on bit line segmentation implemented based on the above array is as follows:

[0061] When reading the storage cell data corresponding to the non-first bit line segment, the corresponding transmission gate is turned off and the corresponding bit line segment is pre-discharged; the first bit line segment is the bit line segment closest to the global amplifier, such as Figure 1 The lower segment line of the middle transmission gate.

[0062] The corresponding word line WL is pulled high to turn on the transistor NMOS of the memory cell, and the corresponding plate line PL is pulled high to apply an external electric field to the ferroelectric capacitor of the memory cell, so that the ferroelectric capacitor generates charge and outputs data (generates a voltage difference) to the corresponding branch bit line BL;

[0063] The local amplifier LSA amplifies the voltage difference of the branch bit line BL; if a 2T2C structure is adopted, the local amplifier LSA amplifies the voltage difference between the two branch bit lines BLE and BLO; if a 1T1C structure or a 1T2C structure is adopted, the local amplifier LSA amplifies the voltage difference between the branch bit line BL and the reference voltage;

[0064] After the local amplifier LSA amplifies the voltage difference of the branch bit line, the corresponding transmission gate is restored to the on state.

[0065] After being turned on, the data of the local amplifier LSA will be transmitted to the global amplifier GSA through the trunk bit line GBL, and the data will be output through the data buffer after secondary amplification from the GSA.

[0066] Furthermore, when reading data from a storage unit corresponding to a certain bit line segment, the peripheral driving circuit controls the corresponding transmission gate to be turned off, and restores the transmission gate to the on state after a set time according to the control timing. Figure 1 The upper middle storage unit reads data, and the peripheral drive circuit controls a group of two transmission gates to turn off and restore them after a set time according to the control timing.

[0067] Furthermore, the storage array of the ferroelectric memory is designed as described in this scheme, that is, a transmission gate controlled by a peripheral driving circuit is designed in the array, and the general state of the transmission gate is the on state. Before the ferroelectric memory is given to the customer, it is tested to determine whether the bit line voltage difference generated by the ferroelectric capacitor inside each storage unit is sufficient. Taking the 2T2C structure as an example, it is determined whether the corresponding BLE and BLO voltage differences are sufficient when reading data from the storage unit. If they are sufficient, it means that when reading data from the corresponding storage unit, there is no need to turn off the transmission gate. If they are not sufficient, it means that when reading data from the corresponding storage unit, the transmission gate needs to be turned off first. According to the test results, the peripheral driving circuit is designed, and the storage array with sufficient voltage difference is preset to not need to turn off the corresponding transmission gate, and the storage array with insufficient voltage difference is preset to need to turn off the corresponding transmission gate. Of course, the above preset is for the storage unit corresponding to the non-first bit line segment UBL. Thus, when reading data from the bit line segment, the peripheral driving circuit first determines whether the memory cell being read is the memory cell corresponding to the first bit line segment UBL. If so, no transmission gate needs to be controlled. If not, it determines whether the corresponding transmission gate needs to be turned off according to the actual voltage difference generated by the ferroelectric capacitor inside the memory cell. Figure 1 As shown in the figure, a set of transmission gates divides the memory array into two halves. When the transmission gate is turned on, the memory cell corresponding to the top word line has the longest bit line and the largest parasitic capacitance. When the transmission gate is turned off, the bit line is divided into two halves, and the parasitic capacitance is reduced by half.

[0068] Specifically, since the parasitic capacitance of the memory cell is larger the farther away, the voltage difference is most likely to be insufficient. In this embodiment, the voltage difference of the branch bit line of the memory cell farthest from each group of transmission gates is tested when the data is read. If the voltage difference is sufficient, the corresponding transmission gate is preset to be normally connected, that is, the transmission gate will not be closed when the data is read from the memory cell of this segment. If the voltage difference is insufficient, the corresponding transmission gate is preset to be very connected, that is, the general state is connected, and when the data is read from the memory cell of this segment, the transmission gate will be controlled to be closed according to the control timing and restored after a set time. Figure 1 As shown, the voltage difference of the branch bit line when the data of the top storage unit is read is tested. If it is sufficient, the transmission gate is preset to be normally connected, and the transmission gate will not be closed when the storage unit above the transmission gate is read; if the voltage difference is insufficient, the transmission gate is preset to be very connected, and when the data of the two storage units above the transmission gate is read, the transmission gate will be closed according to the control timing and restored after the set time.

[0069] In another embodiment, the voltage difference of the branch bit line when the data is read is tested for the farthest storage unit in each group of transmission gates. If the voltage difference is sufficient, the corresponding transmission gate is preset to be always on, that is, the transmission gate will not be closed when the data is read from the storage unit of the segment. If the voltage difference is insufficient, the storage units are further tested from far to near in sequence until the voltage difference of a certain storage unit is sufficient or all the storage units of the segment are tested. The storage units with insufficient voltage difference in the segment are preset to need to turn off the corresponding transmission gates, and the others are preset or defaulted to not need to turn off the corresponding transmission gates. Figure 1 As shown, during the test, if the voltage difference of the topmost storage unit is insufficient, the second storage unit above is further tested. If the test result of the second storage unit above is that the voltage difference is sufficient, there is no need to further test the closer storage unit. At this time, the transmission gate is preset to read the data of the topmost storage unit (only read the data of the topmost storage unit or read the data of the topmost storage unit and other storage units at the same time), the transmission gate needs to be turned off, and when reading other storage units except the topmost storage unit, the transmission gate does not need to be turned off. At this time, when reading data from the storage unit above the transmission gate, the transmission gate is controlled to close according to the control timing and restored after the set time, and when reading data from the storage unit above the transmission gate except the topmost storage unit, the transmission gate does not act.

[0070] The farther away the storage unit is, the greater the parasitic capacitance is, and the voltage difference is most likely to be insufficient. For a design with two or more groups of transmission gates, when the voltage difference of the storage unit in the farther group of transmission gates is sufficient, there is no need to test the storage unit in the closer group of transmission gates, and they can be directly preset to be normally on, such as Figure 2As shown, when the voltage difference of the second storage unit above in the segment corresponding to the upper group of transmission gates is sufficient, there is no need to test the storage units in the segment corresponding to the lower group of transmission gates, and the lower group of transmission gates can be directly designed to be normally connected.

[0071] This embodiment designs whether to turn off the corresponding transmission gate according to a method determined by a prior test. For storage cells with sufficient voltage difference, there is no need to turn off the transmission gate. For storage cells with insufficient voltage difference, when reading data from them, the corresponding transmission gate is turned off to achieve the purpose of reducing parasitic capacitance and increasing the voltage difference. Whether to turn off the transmission gate is selectively determined according to the specific situation. There is no need to turn off the transmission gate for each reading, which reduces the switching action frequency of the switch tube and the shutdown time of the switch tube, thereby reducing the loss of the switch tube and extending the service life of the entire memory.

[0072] Specifically, the above control timing can be determined by those skilled in the art according to actual conditions, so as to achieve the purpose of amplification while minimizing the impact on the reading speed.

[0073] This solution increases transmission gates in the array and cooperates with corresponding control methods. When reading data of storage cells far away from the global amplifier, the transmission gates are used to segment the bit lines, thereby reducing the parasitic capacitance of the bit lines and improving the reading accuracy.

[0074] The principle that this scheme can achieve the purpose is that the bit line has a parasitic capacitance to ground. Figure 1 Taking the structure as an example, the longer the bit line GBLE / GBLO is, the greater the load and the greater the parasitic capacitance. In the traditional case where there is no transmission gate, the parasitic capacitance is larger for the storage unit at a farther position of the GBLE / GBLO line. If the charges generated by the two ferroelectric capacitors of the storage unit under a certain plate line voltage are Q1 and Q2 (Q1>Q2), respectively. The voltage of BLE is U1=Q1 / C, and the voltage of BLO is U2=Q2 / C. Among them, C is the parasitic capacitance. The voltage difference between BLE and BLO=U1-U2=(Q1-Q2) / C. Q1-Q2 is a constant. The larger C is, the smaller the voltage difference is. By reducing the parasitic capacitance by segmenting the bit line, the voltage difference between BLE and BLO is increased, thereby achieving the purpose of improving the reading accuracy.

[0075] The specific embodiments described in this embodiment are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the attached claims.

Claims

1. A memory array for effectively releasing ferroelectric charge based on bit line segmentation, comprising a plurality of memory cells constituting the memory array, each memory cell comprising a ferroelectric capacitor and a transistor, each memory cell being connected to a word line WL, a plate line PL and a bit line, each memory cell being connected to a global amplifier GSA via a bit line, characterized in that: The bit lines include a trunk bit line GBL and a branch bit line BL corresponding to each storage cell. The branch bit line BL is connected to a local amplifier LSA. The data of the storage cell is transmitted to the local amplifier LSA through the branch bit line BL for amplification and then transmitted to the global amplifier GSA through the trunk bit line GBL to realize data output of the storage array. At least one group of transmission gates is inserted into the main bit line GBL to divide the storage array into at least two sections in the column direction. Each group of transmission gates corresponds to a bit line segment UBL away from the global amplifier GSA. When reading data from the storage unit corresponding to the bit line segment UBL, the corresponding transmission gate is turned off until the corresponding local amplifier LSA amplifies the voltage difference of the branch bit line BL and then restores the transmission gate to the on state.

2. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 1, characterized in that: Each bit line segment UBL has a pre-discharge transistor for pre-discharging the corresponding bit line segment before reading data from the memory cell.

3. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 1, characterized in that: A first group of transmission gates is provided on the main bit line GBL, and the transmission gates in the group divide the memory array into two sections in the column direction.

4. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 3, characterized in that: The main bit line GBL also has second to N-th groups of transmission gates, where N is greater than or equal to 2; Each group of transmission gates divides the bit line segment where it is located into two segments again, so that the column direction of the memory array is divided into N+1 segments through N groups of transmission gates.

5. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 3, characterized in that: Each memory cell adopts a 2T2C structure including two transistors and two ferroelectric capacitors; Each storage cell corresponds to two branch bit lines BLE and BLO, and the local amplifier LSA is used to amplify the voltage difference between the two branch bit lines BLE and BLO; A column of memory cells shares a trunk bit line GBL, each column of memory cells corresponds to two trunk bit lines GBLE and GBLO, and a set of transmission gates is composed of two sets of transistors correspondingly arranged on the two trunk bit lines GBLE and GBLO; The two groups of transistors in the transmission gate group work together to divide the corresponding section of the bit line into two sections.

6. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 3, characterized in that: Each memory cell adopts a 1T1C structure including a transistor and a ferroelectric capacitor; Alternatively, each memory cell adopts a 1T2C structure including one transistor and two ferroelectric capacitors; Each storage unit corresponds to a branch bit line, and the local amplifier LSA is used to amplify the voltage difference between the branch bit line and the reference voltage; Each column of storage cells corresponds to a main bit line, and a group of transmission gates is composed of a group of transistors that divide a corresponding segment of the bit line into two segments.

7. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 5 or 6, characterized in that: Each group of transistors includes two MOS tubes arranged opposite to each other, the input and output ends of the MOS tubes are connected in series to the corresponding trunk bit lines, and the control end is connected to the peripheral driving circuit.

8. The memory array for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 7, characterized in that: Each group of transistors has two MOS tubes, one is an NMOS tube and the other is a PMOS tube; When reading data from the storage unit corresponding to the bit line segment, the peripheral driving circuit determines whether the corresponding transmission gate needs to be turned off according to the preset, and when it needs to be turned off, controls the corresponding transmission gate to be turned off, and restores the transmission gate to the on state after a set time according to the control timing.

9. A method for effectively releasing ferroelectric charge based on bit line segmentation, characterized in that: The storage array of the ferroelectric memory is divided into N+1 segments by transmission gates in the column direction to obtain N+1 bit line segments, where N represents the number of transmission gate groups; The method includes: When reading the storage cell data corresponding to the non-first bit line segment UBL, the corresponding transmission gate is turned off and the corresponding bit line segment is pre-discharged; Pull the corresponding word line WL to a high level to turn on the transistor of the memory cell, pull the corresponding plate line PL to a high level to apply an external electric field to the ferroelectric capacitor of the memory cell, so that the ferroelectric capacitor generates charge and outputs data to the corresponding branch bit line BL; The local amplifier LSA amplifies the voltage difference of the branch bit line BL; After the local amplifier LSA amplifies the voltage difference of the branch bit line, the corresponding transmission gate is restored to the on state.

10. The method for realizing effective release of ferroelectric charge based on bit line segmentation according to claim 9, characterized in that: When reading the storage unit data corresponding to the non-first bit line segment UBL, it is determined whether to turn off the corresponding transmission gate according to the preset, and when the corresponding transmission gate is turned off, the transmission gate is restored to the on state after the set time according to the control timing; Each storage cell in the storage array is a 2T2C structure, each storage cell corresponds to two branch bit lines BLE and BLO, and the local amplifier LSA amplifies the voltage difference between the two branch bit lines BLE and BLO; Alternatively, each memory cell in the memory array is of 1T1C structure or 1T2C structure, each memory cell corresponds to a branch bit line BL, and the local amplifier LSA amplifies the voltage difference between the branch bit line BL and the reference voltage ref.

Images