Metal gate high-voltage device and process method thereof

Abstract

The invention provides a metal gate high-voltage device and a process method thereof. A first STI region wrapped by a first high-voltage region N-type diffusion region is formed on a substrate; etching back the first STI region to form a first groove; covering a gate oxide layer and a high dielectric layer in the first groove; depositing a polycrystalline silicon layer to fill the first groove; sequentially depositing a silicon nitride hard mask and a silicon oxide hard mask on the polycrystalline silicon layer of the first groove to form a second groove formed by stacking the polycrystalline silicon layer, the silicon nitride hard mask and the silicon oxide hard mask; removing the silicon oxide hard mask, the silicon nitride hard mask and the polycrystalline silicon layer outside the second groove, and reserving the polycrystalline silicon layer in the first groove; injecting a high-voltage region P-type source drain at two sides of the second groove to form refractory silicide on the polycrystalline silicon layer; forming an interlayer dielectric layer to cover the secondary gate region and the second groove on the secondary gate region; and forming a contact hole penetrating through the interlayer dielectric layer on the indissolvable silicide.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a metal gate high voltage device and a process method thereof. Background Art

[0002] As the third generation of display technology, OLED (organic light emitting diode) is a current injection composite light-emitting type. Its main advantages are high brightness, high contrast, wide viewing angle, fast response speed, low operating voltage, strong adaptability, high energy conversion efficiency, simple manufacturing process, etc. Due to the huge technical advantages and application prospects of OLED, it has received widespread attention from academia and industry.

[0003] OLED is a current-driven type. The current density of OLED depends on the driving voltage at both ends. The higher the voltage, the greater the current density. During long-term use, the OLED device itself will age, and the relationship between its voltage, current density and luminous brightness will not always remain constant. The most direct manifestation of OLED device aging is the increase in OLED turn-on voltage and the decrease in luminous efficiency. In order to maintain the same luminous brightness, the OLED current flowing through must be increased, so high-voltage devices are required in OLED to achieve the function of high current. On the other hand, the internal storage module of OLED is limited, and external memory must be selected to store image data. Static RAM (SRAM) has become a commonly used memory in OLED due to its high read and write speed and the ability to maintain data without refresh operation when powered on. With the advancement of logic device technology nodes, OLED technology combined with advanced technology nodes is being continuously developed. The most advanced mass production technology node is the technology combined with 28nm high dielectric material metal gate (28HV metal Gate), which can utilize the high performance and low voltage of advanced nodes. In 28HVMG technology, it is necessary to integrate low-voltage SRAM and high-voltage driver devices, and high voltage requires thick silicon oxide gate, which affects the subsequent process of Metalgate. In order to be compatible with the Metal Gate technology, the high voltage region (HV) will be etched back (Recess) of the active area, and then thick silicon oxide will be grown to make it as consistent as possible with the height of the active area to facilitate subsequent process development.

[0004] The 28nm process high voltage device (HV) uses the field diffusion process (Field Diffusion Drain) structure. In the symmetrical structure, the source and drain both contain shallow trench isolation (STI). When the device is turned on, the current is transmitted through the STI. When high voltage is applied to the gate and drain at the same time, the STI corner under the gate is easy to capture holes in the channel in the early stage of operation, which increases the current and reduces the on-state resistance. As the working time increases, the STI corner close to the drain traps electrons, which reduces the corresponding current and increases the on-state resistance, making the device unstable. Jone F. Chen (On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region; IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008) proposed that this effect is mainly caused by the impact ionization and vertical electric field distribution caused by the current being closer to the Si / SiO2 interface when the gate and drain are at high voltage. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a metal gate high voltage device and a process method thereof, so as to solve the reliability problem of the gate and drain of the high voltage device under high voltage at the same time in the prior art.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a metal gate high voltage device, comprising at least:

[0007] Step 1, providing a substrate, on which a first STI region is formed, the first STI region is surrounded by a first high-voltage region N-type diffusion region; a second high-voltage region N-type diffusion region is located on one side of the first high-voltage region N-type diffusion region and is spaced apart from the first high-voltage region N-type diffusion region;

[0008] Step 2: Carve back the first STI region to form a first groove on the first STI region; the region where the first groove is located is the auxiliary gate region; the region on the upper surface of the substrate between the first high-voltage region N-type diffusion region and the second high-voltage region N-type diffusion region is the metal gate region;

[0009] Step 3, covering the first groove in the auxiliary gate region with a gate oxide layer and a high dielectric layer; and then depositing a polysilicon layer to fill the first groove;

[0010] Step 4: depositing a silicon nitride hard mask and a silicon oxide hard mask in sequence on the polysilicon layer of the first groove to form a second groove stacked by the polysilicon layer, the silicon nitride hard mask and the silicon oxide hard mask;

[0011] Step 5: etching the silicon oxide hard mask, the silicon nitride hard mask and the polysilicon layer in sequence, removing the silicon oxide hard mask, the silicon nitride hard mask and the polysilicon layer outside the second groove, and retaining the polysilicon layer in the first groove;

[0012] Step 6, injecting a high-voltage region P-type source and drain into the auxiliary gate region on both sides of the second groove to form a refractory silicide on the polysilicon layer;

[0013] Step 7: forming an interlayer dielectric layer to cover the auxiliary gate region and the second groove thereon;

[0014] Step eight: forming a contact hole penetrating the interlayer dielectric layer on the insoluble silicide.

[0015] Preferably, in step 2, the etching thickness of the first STI region is

[0016] Preferably, a medium voltage device region is further provided on the semiconductor structure in step one, and the medium voltage device region is provided with an oxide layer.

[0017] Preferably, after etching back the first STI region in step 2, the medium voltage device region is then etched back, and the oxide layer of the medium voltage device region is removed; during the etching back of the medium voltage device region, the first groove of the first STI region is etched to a thickness of During the process of removing the oxide layer in the medium voltage device region, the first groove in the first STI region is etched to a thickness of

[0018] Preferably, in step three, while the gate oxide layer and the high dielectric layer are covered in the first groove of the sub-gate region, the gate oxide layer and the high dielectric layer are also formed in the metal gate region; while the polysilicon layer is deposited to fill the first groove, the polysilicon layer is also deposited on the high dielectric layer in the metal gate region.

[0019] Preferably, before forming the interlayer dielectric layer in step seven, the sub-gate region is covered with photoresist to etch back the polysilicon in the metal gate region.

[0020] Preferably, the substrate in step one also has a second STI region and a third STI region located on one side of the first STI region; and a fourth STI region located on the other side of the first STI region; wherein a first high-voltage region P-type diffusion region is formed between the second STI region and the third STI region.

[0021] Preferably, the second high voltage region N-type diffusion region in step 2 is located on a side of the first high voltage region N-type diffusion region away from the first high voltage region P-type diffusion region; a second high voltage region P-type diffusion region is provided between the second high voltage region N-type diffusion region and the fourth STI region.

[0022] Preferably, the substrate in step one is also provided with a high-voltage P-type potential well enveloping the first high-voltage region P-type diffusion region, the first high-voltage region N-type diffusion region, the second high-voltage region N-type diffusion region and the second high-voltage region P-type diffusion region.

[0023] Preferably, step six also includes: forming source and drain regions P-type doping on the first high voltage region P-type diffusion region and the second high voltage region P-type diffusion region, respectively; forming source and drain regions N-type doping on the first high voltage region N-type diffusion region and the second high voltage region N-type diffusion region, respectively.

[0024] The present invention also provides a metal gate high voltage device, comprising at least:

[0025] A substrate, a high-voltage P-type potential well located on the substrate; a first high-voltage region N-type diffusion region, a second high-voltage region N-type diffusion region, a first high-voltage region P-type diffusion region and a second high-voltage region P-type diffusion region are formed on the high-voltage P-type potential well and are wrapped by the high-voltage P-type potential well;

[0026] A first STI region wrapped by the first high-voltage region N-type diffusion region is provided on the first high-voltage region N-type diffusion region; a second STI region and a third STI region are provided on one side of the first STI region; a fourth STI region is provided on the other side of the first STI region; the first high-voltage region P-type diffusion region is located between the second STI region and the third STI region; the second high-voltage region N-type diffusion region is located on the side of the first high-voltage region N-type diffusion region away from the first high-voltage region P-type diffusion region; a second high-voltage region P-type diffusion region is provided between the second high-voltage region N-type diffusion region and the fourth STI region;

[0027] A gate oxide layer and a high dielectric layer on the gate oxide layer, and a metal gate on the high dielectric layer are formed in the region between the first high voltage region N-type diffusion region and the second high voltage region N-type diffusion region on the substrate; a sidewall of the metal gate is provided with a sidewall;

[0028] A first groove is formed on the first STI region; the area where the first groove is located is a sub-gate area; the first groove is covered with a gate oxide layer and a high dielectric layer located on the gate oxide layer; a polysilicon layer filling the first groove; a second groove located on the polysilicon layer and stacked by a silicon nitride hard mask and a silicon oxide hard mask; refractory silicide on the polysilicon layer on both sides of the second groove; an interlayer dielectric layer covering the sub-gate area and the second groove thereon; and a contact hole located on the refractory silicide and passing through the interlayer dielectric layer.

[0029] As described above, the metal gate high voltage device and its process method of the present invention have the following beneficial effects: the present invention forms a polysilicon gate by opening the high voltage active area back-etching area and the medium voltage back-etching area in the shallow trench isolation area of ​​the original high voltage device, and leads the polysilicon gate in the area through refractory silicide, thereby realizing a voltage-controllable high voltage area channel. By adjusting the voltage of the auxiliary gate, the on-current is kept away from the silicon oxide and silicon interface when the high voltage device is working, thereby improving the reliability problem caused by the high current of the high voltage device and improving the instability problem of the device at the initial operation and long-term operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 8 It shows the structural schematic diagram of each stage of the process method of the metal gate high voltage device of the present invention;

[0031] Fig. 9 Shown is a schematic diagram of the structure of the metal gate high voltage device of the present invention. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0034] The present invention provides a process method for a metal gate high voltage device, such as Figures 1 to 9 As shown, including at least:

[0035] Step 1, providing a substrate, on which a first STI region is formed, the first STI region is surrounded by a first high-voltage region N-type diffusion region; a second high-voltage region N-type diffusion region is located on one side of the first high-voltage region N-type diffusion region and is spaced apart from the first high-voltage region N-type diffusion region; Fig. 9 As shown, the substrate (p-sub) is a P-type substrate, which is formed with a first STI region 02, and the first STI region 02 is surrounded by a first high-voltage region N-type diffusion region 01; the second high-voltage region N-type diffusion region 15 is located on one side of the first high-voltage region N-type diffusion region 01 and is spaced apart from the first high-voltage region N-type diffusion region 01.

[0036] Furthermore, in the present invention, a medium voltage device region is provided on the semiconductor structure in step 1 of this embodiment, and the medium voltage device region is provided with an oxide layer. Fig. 9 The medium voltage device region is not shown. In step 1 of this embodiment, the substrate (p-sub) is also provided with a second STI region 12 and a third STI region 13 located on one side of the first STI region 02; and a fourth STI region 14 located on the other side of the first STI region 02; wherein a first high voltage region P-type diffusion region 16 is formed between the second STI region 12 and the third STI region 13.

[0037] The present invention further provides a high-voltage P-type potential well (HVPW) on the substrate (p-sub) in step one of this embodiment, which wraps the first high-voltage region P-type diffusion region 16, the first high-voltage region N-type diffusion region 01, the second high-voltage region N-type diffusion region 15 and the second high-voltage region P-type diffusion region 17. Figure 1 The first STI region 02 is surrounded by the first high voltage region N-type diffusion region 01 . Figure 1 The first STI region 02 in has not been etched back. Fig. 9 The first STI region 02 in has been etched back.

[0038] like Figure 2 As shown, step 2, the first STI region 02 is etched back to form a first groove 03 on the first STI region 02; the area where the first groove 03 is located is the auxiliary gate area, such as Fig. 9 As shown, the sub-gate region is used as a region for forming a sub-gate; Fig. 9 In the embodiment, the area on the substrate located on the upper surface between the first high voltage area N-type diffusion area 01 and the second high voltage area N-type diffusion area 15 (i.e., the upper surface of the area between the first high voltage area N-type diffusion area 01 and the second high voltage area N-type diffusion area 15) is a metal gate area, and the metal gate area serves as an area for forming a metal gate.

[0039] The present invention further, as Figure 2As shown, in step 2, the etching thickness of the first STI region is like Figure 3 As shown, the present invention further includes engraving back in step 2 of this embodiment Figure 2 After the first STI region 02 in the middle, the medium voltage device region is then etched back and the oxide layer of the medium voltage device region is removed; during the process of etching back the medium voltage device region, Figure 2 The groove 03 of the first STI region in the embodiment is etched to a thickness of During the process of removing the oxide layer in the medium voltage device area, the groove in the first STI area is etched to a thickness of After etching, the Figure 3 The structure shown, it can be seen that Figure 2 The first groove 03 in the embodiment is further etched twice, and its depth becomes deeper, forming a Figure 3 The structure in .

[0040] like Fig. 9 As shown, the present invention further comprises that the second high voltage region N-type diffusion region 15 in step two of this embodiment is located on a side of the first high voltage region N-type diffusion region 01 away from the first high voltage region P-type diffusion region 16; a second high voltage region P-type diffusion region 17 is provided between the second high voltage region N-type diffusion region 15 and the fourth STI region 14.

[0041] like Figure 4 As shown, step three, covering the first groove in the auxiliary gate region with a gate oxide layer and a high dielectric layer 04; then depositing a polysilicon layer 05 to fill the first groove; Figure 4 The gate oxide layer is not shown.

[0042] The present invention further, in step three of this embodiment, while covering the gate oxide layer and the high dielectric layer 04 in the first groove of the sub-gate region, the gate oxide layer and the high dielectric layer are also formed in the metal gate region; while depositing the polysilicon layer to fill the first groove, the polysilicon layer is also deposited on the high dielectric layer in the metal gate region.

[0043] like Figure 5 As shown, step 4, depositing a silicon nitride hard mask 06 and a silicon oxide hard mask 07 in sequence on the polysilicon layer 05 of the first groove to form a second groove 08 stacked by the polysilicon layer, the silicon nitride hard mask and the silicon oxide hard mask;

[0044] like Figure 6 As shown, step five, etching the silicon oxide hard mask, silicon nitride hard mask and polysilicon layer in sequence, removing the silicon oxide hard mask, silicon nitride hard mask and polysilicon layer outside the second groove, and retaining the polysilicon layer 05 in the first groove;

[0045] like Figure 7 As shown, step six, a high voltage region P-type source and drain are implanted into the auxiliary gate region on both sides of the second groove 08 to form a refractory silicide 09 located on the polysilicon layer;

[0046] like Fig. 9 As shown, the present invention further, step six of this embodiment also includes: forming a source and drain region P-type doped SDP on the first high voltage area P-type diffusion area 16 and the second high voltage area P-type diffusion area 17 respectively; forming a source and drain region N-type doped SDN on the first high voltage area N-type diffusion area 01 and the second high voltage area N-type diffusion area 15 respectively.

[0047] like Figure 8 As shown, step seven, forming an interlayer dielectric layer 10 to cover the auxiliary gate region and the second groove 08 thereon;

[0048] The present invention further provides that before forming the interlayer dielectric layer in step seven of this embodiment, the auxiliary gate region is covered with photoresist to etch back the polysilicon in the metal gate region.

[0049] like Figure 8 As shown, in step eight, a contact hole 11 penetrating the interlayer dielectric layer 10 is formed on the insoluble silicide 09 .

[0050] like Fig. 9 As shown, the present invention also provides a metal gate high voltage device, comprising at least:

[0051] A substrate (p-sub), a high-voltage P-type potential well (HVPW) located on the substrate (p-sub); a first high-voltage region N-type diffusion region 01, a second high-voltage region N-type diffusion region 15, a first high-voltage region P-type diffusion region 16 and a second high-voltage region P-type diffusion region 17 are formed on the high-voltage P-type potential well (HVPW);

[0052] A first STI region 02 wrapped by the first high-voltage region N-type diffusion region 01 is provided on the first high-voltage region N-type diffusion region 01; a second STI region 12 and a third STI region 13 are provided on one side of the first STI region 02; a fourth STI region 14 is provided on the other side of the first STI region 02; the first high-voltage region P-type diffusion region 16 is located between the second STI region 12 and the third STI region 13; the second high-voltage region N-type diffusion region 15 is located on the side of the first high-voltage region N-type diffusion region 01 away from the first high-voltage region P-type diffusion region 16; a second high-voltage region P-type diffusion region 17 is provided between the second high-voltage region N-type diffusion region 15 and the fourth STI region 14;

[0053] A gate oxide layer (GOX) and a high dielectric layer (HK) on the gate oxide layer (GOX) and a metal gate on the high dielectric layer (HK) are formed in the region between the first high voltage region N-type diffusion region 01 and the second high voltage region N-type diffusion region 15 on the substrate (p-sub); a sidewall 18 is provided on the sidewall of the metal gate;

[0054] Fig. 9 The secondary gate in Figure 5 The second groove 08 (i.e., the structure formed in step 4) in which the silicon nitride hard mask 06 and the silicon oxide hard mask 07 are stacked is shown in a simplified manner. A first groove is formed on the first STI region 02; the area where the first groove is located is the secondary gate area; the first groove is covered with a gate oxide layer and a high dielectric layer ( Fig. 9 The polysilicon layer 05 filled in the first groove; a second groove (such as a silicon nitride hard mask and a silicon oxide hard mask stacked on the polysilicon layer 05) Figure 5 as shown); refractory silicide on the polysilicon layer on both sides of the second groove; an interlayer dielectric layer covering the sub-gate region and the second groove thereon; and a contact hole located on the refractory silicide and passing through the interlayer dielectric layer.

[0055] In summary, the present invention opens the high-voltage active area back-etching area and the medium-voltage back-etching area in the shallow trench isolation area of ​​the original high-voltage device, so that a polysilicon gate is formed therein, and the polysilicon gate in the area is led out through refractory silicide, thereby realizing a voltage-controllable high-voltage area channel. By adjusting the voltage of the auxiliary gate, the on-current is kept away from the silicon oxide and silicon interface when the high-voltage device is working, thereby improving the reliability problem caused by the high current of the high-voltage device and improving the instability problem of the device at the beginning of operation and long-term operation. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A process method for a metal gate high voltage device, It is characterized in that At least: Step 1, providing a substrate, on which a first STI region is formed, the first STI region is surrounded by a first high-voltage region N-type diffusion region; a second high-voltage region N-type diffusion region is located on one side of the first high-voltage region N-type diffusion region and is spaced apart from the first high-voltage region N-type diffusion region; Step 2: Carve back the first STI region to form a first groove on the first STI region; the region where the first groove is located is the auxiliary gate region; the region on the upper surface of the substrate between the first high-voltage region N-type diffusion region and the second high-voltage region N-type diffusion region is the metal gate region; Step 3, covering the first groove in the auxiliary gate region with a gate oxide layer and a high dielectric layer; and then depositing a polysilicon layer to fill the first groove; Step 4: depositing a silicon nitride hard mask and a silicon oxide hard mask in sequence on the polysilicon layer of the first groove to form a second groove stacked by the polysilicon layer, the silicon nitride hard mask and the silicon oxide hard mask; Step 5: etching the silicon oxide hard mask, the silicon nitride hard mask and the polysilicon layer in sequence, removing the silicon oxide hard mask, the silicon nitride hard mask and the polysilicon layer outside the second groove, and retaining the polysilicon layer in the first groove; Step 6, injecting a high-voltage region P-type source and drain into the auxiliary gate region on both sides of the second groove to form a refractory silicide on the polysilicon layer; Step 7: forming an interlayer dielectric layer to cover the auxiliary gate region and the second groove thereon; Step eight: forming a contact hole penetrating the interlayer dielectric layer on the insoluble silicide.

2. The process of metal gate high voltage device according to claim 1, Features: In step 2, the etching thickness of the first STI region is 3. The process of the metal gate high voltage device according to claim 1, Features: A medium voltage device region is also provided on the semiconductor structure in step 1, and an oxide layer is provided in the medium voltage device region.

4. The process for producing a metal gate high voltage device according to claim 3, Features: After the first STI region is etched back in step 2, the medium voltage device region is then etched back and the oxide layer of the medium voltage device region is removed; during the process of etching back the medium voltage device region, the first groove of the first STI region is etched to a thickness of During the process of removing the oxide layer in the medium voltage device region, the first groove in the first STI region is etched to a thickness of 5. The process for producing a metal gate high voltage device according to claim 1, Features: In step three, while the gate oxide layer and the high dielectric layer are covered in the first groove of the sub-gate region, the gate oxide layer and the high dielectric layer are also formed in the metal gate region; while the polysilicon layer is deposited to fill the first groove, the polysilicon layer is also deposited on the high dielectric layer in the metal gate region.

6. The process for producing a metal gate high voltage device according to claim 5, Features: Before forming the interlayer dielectric layer in step seven, the auxiliary gate region is covered with photoresist to etch back the polysilicon in the metal gate region.

7. The process for producing a metal gate high voltage device according to claim 1, Features: The substrate in step 1 also has a second STI region and a third STI region located on one side of the first STI region; and a fourth STI region located on the other side of the first STI region; wherein a first high voltage region P-type diffusion region is formed between the second STI region and the third STI region.

8. The process for producing a metal gate high voltage device according to claim 7, Features: The second high voltage region N-type diffusion region in step 2 is located on a side of the first high voltage region N-type diffusion region away from the first high voltage region P-type diffusion region; a second high voltage region P-type diffusion region is provided between the second high voltage region N-type diffusion region and the fourth STI region.

9. The process for producing a metal gate high voltage device according to claim 8, Features: The substrate in step one is also provided with a high-voltage P-type potential well that wraps the first high-voltage region P-type diffusion region, the first high-voltage region N-type diffusion region, the second high-voltage region N-type diffusion region and the second high-voltage region P-type diffusion region.

10. The process for producing a metal gate high voltage device according to claim 8, Features: Step six also includes: forming P-type doping of source and drain regions on the first high voltage area P-type diffusion area and the second high voltage area P-type diffusion area respectively; forming N-type doping of source and drain regions on the first high voltage area N-type diffusion area and the second high voltage area N-type diffusion area respectively.

11. A metal gate high voltage device, It is characterized in that At least: A substrate, a high-voltage P-type potential well located on the substrate; a first high-voltage region N-type diffusion region, a second high-voltage region N-type diffusion region, a first high-voltage region P-type diffusion region and a second high-voltage region P-type diffusion region are formed on the high-voltage P-type potential well and are wrapped by the high-voltage P-type potential well; A first STI region wrapped by the first high-voltage region N-type diffusion region is provided on the first high-voltage region N-type diffusion region; a second STI region and a third STI region are provided on one side of the first STI region; a fourth STI region is provided on the other side of the first STI region; the first high-voltage region P-type diffusion region is located between the second STI region and the third STI region; the second high-voltage region N-type diffusion region is located on the side of the first high-voltage region N-type diffusion region away from the first high-voltage region P-type diffusion region; a second high-voltage region P-type diffusion region is provided between the second high-voltage region N-type diffusion region and the fourth STI region; A gate oxide layer and a high dielectric layer on the gate oxide layer, and a metal gate on the high dielectric layer are formed in the region between the first high voltage region N-type diffusion region and the second high voltage region N-type diffusion region on the substrate; a sidewall of the metal gate is provided with a sidewall; A first groove is formed on the first STI region; the area where the first groove is located is a sub-gate area; the first groove is covered with a gate oxide layer and a high dielectric layer located on the gate oxide layer; a polysilicon layer filling the first groove; a second groove located on the polysilicon layer and stacked by a silicon nitride hard mask and a silicon oxide hard mask; refractory silicide on the polysilicon layer on both sides of the second groove; an interlayer dielectric layer covering the sub-gate area and the second groove thereon; and a contact hole located on the refractory silicide and passing through the interlayer dielectric layer.

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