Manufacturing method for integrating BCD and SGT devices through selective epitaxy

Abstract

The invention provides a manufacturing method for integrating a BCD device and an SGT device by using selective epitaxy, which comprises the following steps of: providing a highly doped substrate of a first conduction type, forming a hard mask layer on the substrate, etching the substrate on the formation region of the BCD device to form a groove, forming an oxide layer on the exposed substrate, and forming an SGT device on the oxide layer, etching to remove the oxide layer at the bottom of the groove, forming a low-doped epitaxial layer which fills the groove and is of the second conductive type, and grinding the epitaxial layer and the hard mask layer to the substrate; forming a partial structure of the SGT device on the substrate on the forming region of the SGT device; forming a shallow trench isolation structure to define an active region of the BCD device; forming a first well of the SGT device by ion implantation, wherein the first well is of a second conductive type; a well region and a drift region of the BCD device are formed by ion implantation. According to the invention, BCD and SGT processes are integrated, single-chip integration can be realized, the manufacturing cost is reduced, and the product competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing BCD and SGT devices by utilizing selective epitaxial integration. Background Art

[0002] See also Figure 1 IPD is the abbreviation of Intelligent Power Device, which refers to a high-performance semiconductor power switch with a built-in protection circuit that can absorb energy from inductive loads, etc. It is also called a smart switch, high-side / low-side switch, etc. With the rise of software, autonomous driving, and functional safety, high-side switches are rapidly replacing fuses that have no software configuration function, low reliability, and no diagnostic function.

[0003] The BCD process can complete the control of analog and digital signals and the processing of high-power power on a single chip. The SGT device can meet the higher performance requirements of MOSFET for in-vehicle intelligent high-side switches due to its extremely low parasitic resistance, high-temperature reliability and saturation zone working reliability. However, there are contradictions in the requirements of the two devices for the substrate, making the single-chip integration of the two devices a technical challenge.

[0004] At present, the industry usually manufactures BCD and SGT devices separately on two chips, and then integrates the two together through subsequent packaging. BCD and SGT are connected by bonding wires, and the parasitic Rs (resistance) and Rc (capacitance) are large, and the performance matching between the two is not high. This method not only increases the manufacturing cost, but also limits the further improvement of chip performance.

[0005] There are also some manufacturing processes in the industry that can realize the simultaneous manufacture of BCD and SGT devices on a single chip. However, these processes cannot solve the different requirements of BCD and SGT devices for substrate doping type and concentration, and need to sacrifice performance parameters such as parasitic resistance and breakdown voltage, and cannot fully explore the performance potential of these two devices.

[0006] In order to solve the above problems, it is necessary to propose a new manufacturing method of integrating BCD and SGT devices using selective epitaxy. Summary of the invention

[0007] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a manufacturing method for integrating BCD and SGT devices using selective epitaxial growth, so as to solve the problem that BCD and SGT devices in the prior art have different requirements for substrate doping type and concentration, and performance parameters such as parasitic resistance and breakdown voltage need to be sacrificed, and the performance potential of these two devices cannot be fully explored.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing BCD and SGT devices by selective epitaxy integration, comprising:

[0009] Step 1, providing a highly doped substrate of a first conductivity type, the substrate including a formation area of ​​a BCD device and a formation area of ​​an SGT device, forming a hard mask layer on the substrate, etching the substrate on the BCD device formation area to form a groove, forming an oxide layer on the exposed substrate, etching and removing the oxide layer on the bottom of the groove, forming a low-doped epitaxial layer of a second conductivity type filling the groove, and grinding the epitaxial layer and the hard mask layer onto the substrate;

[0010] Step 2: forming a partial structure of the SGT device on the substrate in the formation area of ​​the SGT device, which includes:

[0011] A first trench formed on the epitaxial layer and a second trench located at a side of the first trench;

[0012] forming a first dielectric layer and a first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench;

[0013] an isolation dielectric layer formed on the first gate polysilicon layer in the first;

[0014] a second dielectric layer formed in the first trench and on the epitaxial layer;

[0015] a second gate polysilicon layer filling the remaining first trench;

[0016] Step 3: forming a shallow trench isolation structure to define an active area of ​​the BCD device;

[0017] Step 4: forming a first well of the SGT device by ion implantation, wherein the first well is of the second conductivity type;

[0018] The well region and drift region of the BCD device are formed by ion implantation;

[0019] Step 5: forming a gate structure of a BCD device, and forming heavily doped regions of the BCD device and the SGT device by ion implantation;

[0020] Step 6: forming a metal interconnection structure for leading out the BCD device and the SGT device on the front side of the substrate; and forming a metal layer as a drain terminal of the SGT device on the back side of the substrate.

[0021] Preferably, the material of the hard mask layer in step 1 is silicon dioxide.

[0022] Preferably, in step one, the oxide layer is formed by thermal oxidation.

[0023] Preferably, the grinding method in step one is chemical mechanical planarization grinding.

[0024] Preferably, the method for forming a partial structure of the SGT device in step 2 includes: forming the first dielectric layer and the first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench; forming the isolation dielectric layer filling the remaining first trench, grinding the isolation dielectric layer onto the epitaxial layer, etching the isolation dielectric layer in the first trench so that part of it remains on the first gate polysilicon layer therein; forming a second dielectric layer on the epitaxial layer and in the first trench, and then forming the second gate polysilicon layer filling the remaining first trench.

[0025] Preferably, the BCD device in step three includes at least one of a MOS device, a bipolar device, and an LDMOS device.

[0026] Preferably, the BCD device in step three includes a CMOS device and a LDMOS device.

[0027] Preferably, the method of forming the well region and drift region of the BCD device by ion implantation in step four includes: forming the body region and drift region of the LDMOS device by ion implantation, the body region is of the first conductivity type, and the drift region is of the second conductivity type; and forming a second well of the CMOS device, the second well is of the first conductivity type.

[0028] Preferably, step four also includes forming an isolation ring structure, which is used to isolate the SGT device and the BCD device and the internal devices of the BCD.

[0029] Preferably, the gate structure in step five comprises: a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer; and sidewalls of the gate dielectric layer and the gate polysilicon layer are formed with sidewalls.

[0030] Preferably, the gate structure of the BCD device in step five includes a first gate structure of an LDMOS device and a second gate structure of a CMOS device, one end of the first gate structure extends to the body region, and the other end thereof extends to the shallow trench isolation on the adjacent drift region, and the second gate structure is located on the third well.

[0031] Preferably, the method of forming heavily doped regions of BCD devices and SGT devices by ion implantation in step five includes: forming heavily doped regions located on the body region, the drift region, and the first and second wells; the heavily doped region on the first well serves as the source of the SGT device; the heavily doped region on the drift region serves as the drain of the LDMOS device, and the heavily doped region on the body region serves as the source of the LDMOS device; the heavily doped region on the second well serves as the source and drain of the CMOS device.

[0032] Preferably, step five also includes the step of forming a substrate lead-out region on the body region and the second well.

[0033] Preferably, step six further includes thinning the back side of the substrate before forming the metal layer on the back side of the substrate.

[0034] Preferably, in step six, the substrate is thinned by chemical mechanical planarization grinding.

[0035] Preferably, the first conductivity type is N type, and the second conductivity type is P type.

[0036] Preferably, the first conductivity type is P type, and the second conductivity type is N type.

[0037] As described above, the method for manufacturing BCD and SGT devices by selective epitaxy integration of the present invention has the following beneficial effects:

[0038] The present invention integrates BCD and SGT processes, can achieve single-chip integration, reduce manufacturing costs, and improve product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Shown is a schematic diagram of a high-side switch of the prior art;

[0040] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0041] Figure 3 Shown is a schematic diagram of a substrate of the present invention;

[0042] Figure 4 It is a schematic diagram showing the formation of a hard mask layer according to the present invention;

[0043] Figure 5 It is a schematic diagram showing the formation of an oxide layer on the groove according to the present invention;

[0044] Figure 6 Shown is a schematic diagram of forming an epitaxial layer of the present invention;

[0045] Figure 7 Shown is a schematic diagram of a polished isolation dielectric layer of the present invention;

[0046] Figure 8 It is a schematic diagram of etching the isolation dielectric layer of the present invention;

[0047] Fig. 9 It shows a partial structure of forming an SGT device and a schematic diagram of shallow trench isolation according to the present invention;

[0048] Fig.10 It is a schematic diagram showing the formation of the body region, the drift region, the first well of the SGT device and the second well of the CMOS device of the present invention;

[0049] Fig.11 It is a schematic diagram of forming a heavily doped region and a gate structure according to the present invention. DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] See also Figure 2 The present invention provides a method for manufacturing a BCD device (capable of manufacturing bipolar, CMOS and DMOS devices on the same chip) and a SGT device by selective epitaxial integration, comprising:

[0052] Step 1: Please refer to Figure 3 , providing a highly doped substrate 101 of a first conductivity type, which can reduce the parasitic resistance Rsp of the SGT device and improve the device performance, the substrate 101 includes a formation area of ​​a BCD device and a formation area of ​​an SGT device, and a hard mask layer 102 is formed on the substrate 101 to form a Figure 4 The structure shown in FIG. 1 is formed by etching the substrate 101 on the BCD device forming area to form a groove, and forming an oxide layer 103 on the exposed substrate 101 to form a Figure 5 The structure shown in FIG. 1 is etched to remove the oxide layer 103 on the bottom of the groove to form a low-doped epitaxial layer 104 of the second conductivity type filling the groove. The epitaxial layer 104 serves as a substrate of the BCD device to provide a suitable withstand voltage and Ion to form a structure as shown in FIG. Figure 6 In the structure shown, the epitaxial layer 104 and the hard mask layer 102 are ground onto the substrate 101;

[0053] In some embodiments, the material of the hard mask layer 102 in step 1 is silicon dioxide.

[0054] In some embodiments, in step 1, the oxide layer 103 is formed by thermal oxidation.

[0055] In some embodiments, the polishing method in step 1 is chemical mechanical planarization polishing.

[0056] Step 2: forming a partial structure of the SGT device on the substrate 101 on the formation area of ​​the SGT device, which includes:

[0057] A first trench formed on the epitaxial layer 104 and a second trench located at a side of the first trench;

[0058] forming a first dielectric layer 105 and a first gate polysilicon layer 106 in the first and second trenches, wherein the first dielectric layer 105 and the first gate polysilicon layer 106 are located at the lower end of the first trench and in the second trench;

[0059] An isolation dielectric layer 107 formed on the first gate polysilicon layer 106;

[0060] a second dielectric layer 108 formed in the first trench and on the epitaxial layer 104;

[0061] A second gate polysilicon layer 120 filling the remaining first trench;

[0062] In some embodiments, the method of forming a partial structure of the SGT device in step 2 includes: forming a first dielectric layer 105 and a first gate polysilicon layer 106 in the first and second trenches, wherein the first dielectric layer 105 and the first gate polysilicon layer 106 are located at the lower end of the first trench and in the second trench; forming an isolation dielectric layer 107 filling the remaining first trench, grinding the isolation dielectric layer 107 onto the epitaxial layer 104, and forming Figure 7 The structure shown in FIG. 1 is formed by etching the isolation dielectric layer 107 in the first trench so that a portion of the isolation dielectric layer 107 remains on the first gate polysilicon layer 106 therein. Figure 8 The structure shown; a second dielectric layer 108 is formed on the epitaxial layer 104 and in the first trench, and then a second gate polysilicon layer 120 is formed to fill the remaining first trench.

[0063] Step 3: forming a shallow trench isolation 109 structure to define the active area of ​​the BCD device, forming Fig. 9 The structure shown;

[0064] In some embodiments, the BCD device in step three includes at least one of a MOS device, a bipolar device, and an LDMOS device.

[0065] In some embodiments, the BCD device in step three includes a CMOS device and a LDMOS device.

[0066] Step 4: forming a first well 110 of the SGT device by ion implantation, wherein the first well 110 is of the second conductivity type;

[0067] The well region and drift region 113 of the BCD device are formed by ion implantation, forming Fig.10 The structure shown;

[0068] In some embodiments, the method of forming the well region and drift region 113 of the BCD device by ion implantation in step four includes: forming the body region 112 and the drift region 113 of the LDMOS device by ion implantation, the body region 112 being of the first conductivity type, and the drift region 113 being of the second conductivity type; and forming the second well 114 of the CMOS device, the second well 114 being of the first conductivity type.

[0069] In some embodiments, step 4 also includes forming an isolation ring structure, which is used to isolate the SGT device from the BCD device and the internal device of the BCD. For example, the isolation ring structure can be a doped well 111 formed by ion implantation and a doped well lead-out region 117 thereon.

[0070] Step 5: Form the gate structure of the BCD device, and use ion implantation to form the heavily doped regions of the BCD device and the SGT device, forming Fig.11 The structure shown;

[0071] In some embodiments, the gate structure in step five includes: a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer; and sidewalls of the gate dielectric layer and the gate polysilicon layer are formed with sidewall spacers.

[0072] In some embodiments, the gate structure of the BCD device in step five includes a first gate structure 115 of the LDMOS device and a second gate structure 116 of the CMOS device, one end of the first gate structure 115 extends to the body region 112, and the other end thereof extends to the shallow trench isolation 109 on the adjacent drift region 113, and the second gate structure 116 is located on the third well.

[0073] In some embodiments, the method of forming heavily doped regions of BCD devices and SGT devices by ion implantation in step five includes: forming heavily doped regions located on the body region 112, the drift region 113, and the first and second wells; the heavily doped region 121 on the first well 110 serves as the source of the SGT device; the heavily doped region 110 on the drift region 113 serves as the drain of the LDMOS device, and the heavily doped region 119 on the body region 112 serves as the source of the LDMOS device; and the heavily doped regions (118, 119) on the second well 114 serve as the source and drain of the CMOS device.

[0074] In some embodiments, step five further includes the step of forming a substrate lead-out region ( 118 , 122 ) on the body region 112 and the second well 114 .

[0075] Step 6: Form a metal interconnection structure for leading out the BCD device and the SGT device on the front side of the substrate 101; and form a metal layer as a drain terminal of the SGT device on the back side of the substrate 101.

[0076] The interconnect structure includes various conductive components to connect various IC devices to the integrated circuit. The interconnect structure also includes an interlayer dielectric (ILD) layer to separate and isolate various conductive components. For example, the interconnect structure includes contacts; metal lines; and through holes. The metal lines are distributed in multiple metal layers. For example, the metal lines may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The through holes may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The contacts may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some instances, the various conductive components may further include barrier layers such as tantalum and tantalum nitride, titanium and titanium nitride.

[0077] The ILD layer includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive components (such as metal lines, contacts and vias). The ILD layer includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials or combinations thereof. In some instances, low-k dielectric materials include fluorinated silicon glass (FSG), carbon-doped silicon oxide, xerogels, aerogels, amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene), polyimide and / or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide. For example, the formation of the ILD layer includes deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques or combinations thereof. The ILD layer may include multiple layers and may be formed together with various conductive components with appropriate procedures (such as damascene processes).

[0078] In some embodiments, the interconnect structure or its part is formed by deposition and patterning. For example, a metal (or metal alloy) such as aluminum copper is deposited by physical vapor deposition (PVD), and then patterned by photolithography and etching. Then the ILD layer is set by deposition (and CMP). In some embodiments, the interconnect structure uses a damascene process to form a metal line. In the damascene process, the ILD layer is deposited, the ILD layer is further flattened by CMP, and then patterned by photolithography and etching to form a groove. One or more conductive materials are deposited to fill the groove, and another CMP process is applied to remove excess conductive materials and flatten the top surface, thereby forming a conductive component. The damascene process can be used to form a metal line, a through hole and a contact. A dual damascene process can be applied to form a layer of metal line and a through hole adjacent to the metal line. In this case, the ILD layer is deposited and patterned twice to form a groove and a through hole respectively. Then metal is deposited to fill both the groove and the through hole to form a metal line and a through hole.

[0079] In some embodiments, before forming the metal layer on the back side of the substrate 101 in step six, the back side of the substrate 101 is further thinned.

[0080] In some embodiments, in step six, the substrate 101 is thinned by chemical mechanical planarization.

[0081] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0082] In some embodiments, the first conductivity type is P type, and the second conductivity type is N type.

[0083] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0084] In summary, the present invention integrates BCD and SGT processes, can achieve single chip integration, reduce manufacturing costs, and improve product competitiveness. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a BCD and SGT device by selective epitaxy integration, characterized in that: At least: Step 1, providing a highly doped substrate of a first conductivity type, the substrate including a formation area of ​​a BCD device and a formation area of ​​an SGT device, forming a hard mask layer on the substrate, etching the substrate on the BCD device formation area to form a groove, forming an oxide layer on the exposed substrate, etching and removing the oxide layer on the bottom of the groove, forming a low-doped epitaxial layer of a second conductivity type filling the groove, and grinding the epitaxial layer and the hard mask layer onto the substrate; Step 2: forming a partial structure of the SGT device on the substrate in the formation area of ​​the SGT device, which includes: A first trench formed on the epitaxial layer and a second trench located at a side of the first trench; forming a first dielectric layer and a first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench; an isolation dielectric layer formed on the first gate polysilicon layer in the first; a second dielectric layer formed in the first trench and on the epitaxial layer; a second gate polysilicon layer filling the remaining first trench; Step 3: forming a shallow trench isolation structure to define an active area of ​​the BCD device; Step 4: forming a first well of the SGT device by ion implantation, wherein the first well is of the second conductivity type; The well region and drift region of the BCD device are formed by ion implantation; Step 5: forming a gate structure of a BCD device, and forming heavily doped regions of the BCD device and the SGT device by ion implantation; Step 6: forming a metal interconnection structure for leading out the BCD device and the SGT device on the front side of the substrate; and forming a metal layer as a drain terminal of the SGT device on the back side of the substrate.

2. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: The material of the hard mask layer in step 1 is silicon dioxide.

3. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: In step one, the oxide layer is formed by thermal oxidation.

4. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: The grinding method in step 1 is chemical mechanical planarization grinding.

5. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: The method for forming a partial structure of the SGT device in step 2 includes: forming the first dielectric layer and the first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench; forming the isolation dielectric layer filling the remaining first trench, grinding the isolation dielectric layer onto the epitaxial layer, etching the isolation dielectric layer in the first trench so that part of it remains on the first gate polysilicon layer therein; forming a second dielectric layer on the epitaxial layer and in the first trench, and then forming the second gate polysilicon layer filling the remaining first trench.

6. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: The BCD device in step three includes at least one of a MOS device, a bipolar device, and an LDMOS device.

7. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 6, characterized in that: The BCD device in step three includes a CMOS device and a LDMOS device.

8. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 7, characterized in that: The method of forming the well region and drift region of the BCD device by ion implantation in step 4 includes: forming the body region and drift region of the LDMOS device by ion implantation, the body region is of the first conductivity type, and the drift region is of the second conductivity type; and forming a second well of the CMOS device, the second well being of the first conductivity type.

9. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: Step 4 also includes forming an isolation ring structure, which is used to isolate the SGT device and the BCD device and the internal devices of the BCD.

10. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: The gate structure in step 5 includes: a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer; Sidewalls of the gate dielectric layer and the gate polysilicon layer are formed with sidewall spacers.

11. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 7, characterized in that: The gate structure of the BCD device in step five includes a first gate structure of an LDMOS device and a second gate structure of a CMOS device, one end of the first gate structure extends to the body region, and the other end thereof extends to the shallow trench isolation on the adjacent drift region, and the second gate structure is located on the third well.

12. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 8, characterized in that: The method of forming heavily doped regions of BCD devices and SGT devices by ion implantation in step five includes: forming heavily doped regions located on the body region, the drift region, and the first and second wells; the heavily doped region on the first well serves as the source of the SGT device; the heavily doped region on the drift region serves as the drain of the LDMOS device, and the heavily doped region on the body region serves as the source of the LDMOS device; the heavily doped region on the second well serves as the source and drain of the CMOS device.

13. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 8, characterized in that: Step five also includes the step of forming a substrate lead-out region on the body region and the second well.

14. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 1, characterized in that: Step six also includes thinning the back side of the substrate before forming the metal layer on the back side of the substrate.

15. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to claim 14, characterized in that: In step six, the substrate is thinned by chemical mechanical planarization and polishing.

16. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to any one of claims 1 to 15, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

17. The method for manufacturing a BCD and SGT device by selective epitaxy integration according to any one of claims 1 to 15, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

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