Three-dimensional detector and preparation method thereof

Abstract

The invention discloses a three-dimensional detector and a preparation method thereof, and relates to the field of semiconductor devices.The preparation method comprises the steps that a semiconductor substrate is provided and comprises a semiconductor base and a semiconductor device layer located on the surface of one side of the semiconductor base; forming a central electrode and a trench electrode surrounding the central electrode in the semiconductor device layer, wherein the doping types of the central electrode and the trench electrode are different; a metal interconnection layer is formed on the surface of the semiconductor device layer, the metal interconnection layer comprises a first metal electrode and a second metal electrode, the first metal electrode is connected with the central electrode, and the second metal electrode is connected with the trench electrode; the bottoms, facing the semiconductor substrate, of the trench electrodes are located on the same closed equipotential electric field plane, and the depth of the central electrode in the semiconductor device layer does not exceed the equipotential electric field plane; the equipotential electric field plane is a bottom surface of the semiconductor device layer facing the semiconductor substrate. The stability and reliability of the three-dimensional detector can be improved, and the performance of the three-dimensional detector can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and more specifically, to a three-dimensional detector and a method for preparing the same. Background Art

[0002] Due to their unique design and detector capabilities, three-dimensional detectors are widely used in high-precision and high-resolution application scenarios, such as lidar detectors, medical diagnosis, large scientific detection equipment, aerospace and other strong radiation fields.

[0003] At present, the radiation resistance and charge collection efficiency of conventional three-dimensional detectors still need to be further improved. Summary of the invention

[0004] In view of this, the present application provides a three-dimensional detector and a method for preparing the same, the scheme is as follows:

[0005] The first aspect of the present application provides a method for preparing a three-dimensional detector, the preparation method comprising:

[0006] Providing a semiconductor substrate, the semiconductor substrate comprising a semiconductor base and a semiconductor device layer located on a surface of one side of the semiconductor base;

[0007] forming a central electrode and a trench electrode surrounding the central electrode in the semiconductor device layer, wherein the central electrode and the trench electrode have different doping types;

[0008] forming a metal interconnection layer on the surface of the semiconductor device layer, wherein the metal interconnection layer comprises a first metal electrode and a second metal electrode, wherein the first metal electrode is connected to the central electrode, and the second metal electrode is connected to the trench electrode;

[0009] The bottom of the trench electrodes facing the semiconductor substrate is located in the same closed equipotential electric field plane, and the depth of the central electrode in the semiconductor device layer does not exceed the equipotential electric field plane; the equipotential electric field plane is the bottom surface of the semiconductor device layer facing the semiconductor substrate.

[0010] Optionally, in the above preparation method, the semiconductor substrate is a silicon-on-insulator, the semiconductor device layer is a top silicon layer of the silicon-on-insulator, the semiconductor base is a bottom silicon layer of the silicon-on-insulator, and an insulating buried layer is provided between the top silicon layer and the bottom silicon layer;

[0011] The equipotential electric field plane is the interface between the top silicon layer and the buried insulating layer.

[0012] Optionally, in the above-mentioned preparation method, the bottoms of the groove electrode and the central electrode both extend and stop at the interface;

[0013] Alternatively, the trench electrode extends and stops at the interface, and the central electrode stops above the interface.

[0014] Optionally, in the above preparation method, the semiconductor device layer is a semiconductor epitaxial layer on the surface of the semiconductor substrate; the doping concentration of the semiconductor epitaxial layer is less than the doping concentration of the semiconductor substrate;

[0015] The equipotential electric field plane is the interface between the semiconductor epitaxial layer and the semiconductor substrate.

[0016] Optionally, in the above preparation method, the bottom of the trench electrode extends to the interface;

[0017] The bottom of the central electrode stops above the interface and has a preset distance from the interface.

[0018] Optionally, in the above preparation method, forming a central electrode and a trench electrode surrounding the central electrode in the semiconductor device layer comprises:

[0019] forming a central columnar hole in the semiconductor device layer, wherein the depth of the central columnar hole does not exceed the equipotential electric field plane;

[0020] Filling the first semiconductor material in the central columnar hole to form a central electrode;

[0021] forming a trench around the central electrode in the semiconductor device layer, wherein the bottom of the trench extends to the equipotential electric field plane;

[0022] The second semiconductor material is filled in the trench to form a trench electrode.

[0023] or,

[0024] forming a trench in the semiconductor device layer;

[0025] Filling the first semiconductor material in the trench to form a trench electrode;

[0026] Forming a central columnar hole in the semiconductor device layer surrounded by the trench electrode, wherein the depth of the central columnar hole does not exceed the equipotential electric field plane;

[0027] The central columnar hole is filled with a second semiconductor material to form a central electrode.

[0028] Optionally, in the above preparation method, it further includes: forming an isolation ring in the semiconductor device layer, the isolation ring including at least one first isolation ring and at least one second isolation ring;

[0029] The depths of the first isolation ring and the second isolation ring are both less than the depth of the central electrode; the first isolation ring surrounds the groove electrode; and the second isolation ring is located between the central electrode and the groove electrode.

[0030] A second aspect of the present application provides a three-dimensional detector formed by the above-mentioned preparation method, the three-dimensional detector comprising:

[0031] A semiconductor substrate, the semiconductor substrate comprising a semiconductor base and a semiconductor device layer located on a surface of one side of the semiconductor base;

[0032] A central electrode and a trench electrode surrounding the central electrode are arranged in the semiconductor device layer, and the central electrode and the trench electrode have different doping types;

[0033] A metal interconnection layer is arranged on the surface of the semiconductor device layer, the metal interconnection layer comprises a first metal electrode and a second metal electrode, the first metal electrode is connected to the central electrode, and the second metal electrode is connected to the trench electrode;

[0034] The bottom of the trench electrodes facing the semiconductor substrate is located in the same closed equipotential electric field plane, and the depth of the central electrode in the device layer does not exceed the equipotential electric field plane; the equipotential electric field plane is the bottom surface of the semiconductor device layer facing the semiconductor substrate.

[0035] Optionally, in the above-mentioned three-dimensional detector, the semiconductor substrate is silicon on insulator, the semiconductor device layer is the top silicon layer of silicon on insulator, the semiconductor base is the bottom silicon layer of silicon on insulator, and there is an insulating buried layer between the top silicon layer and the bottom silicon layer; the equipotential electric field plane is the interface between the top silicon layer and the insulating buried layer; the bottom of the trench electrode and the central electrode both extend and stop at the interface; or, the trench electrode extends and stops at the interface, and the central electrode stops above the interface.

[0036] Or, the semiconductor device layer is a semiconductor epitaxial layer on the surface of the semiconductor substrate; the doping concentration of the semiconductor epitaxial layer is less than the doping concentration of the semiconductor substrate; the equipotential electric field plane is the interface between the semiconductor epitaxial layer and the semiconductor substrate; the bottom of the trench electrode extends to the interface; the bottom of the central electrode stops above the interface and has a preset distance from the interface.

[0037] Optionally, in the above three-dimensional detector, an isolation ring is arranged in the semiconductor device layer, and the isolation ring includes at least one first isolation ring and / or at least one second isolation ring;

[0038] The depths of the first isolation ring and the second isolation ring are both less than the depth of the central electrode; the first isolation ring surrounds the groove electrode; and the second isolation ring is located between the central electrode and the groove electrode.

[0039] It can be seen from the above description that in the three-dimensional detector and its preparation method provided by the present application, the groove electrode is arranged to be located in the same closed equipotential electric field plane toward the bottom of the semiconductor substrate, and the depth of the central electrode in the semiconductor device layer is arranged not to exceed the equipotential electric field plane. In this way, the bottom of the groove electrode can form a uniform electric field distribution based on the equipotential electric field plane, thereby improving the irradiation performance and charge collection efficiency of the three-dimensional detector. In addition, the bottom of the groove electrode has a uniform electric field distribution, and the signal distortion and delay problems caused by the non-uniformly distributed electric field can also be avoided, and a clearer signal output can be obtained, which improves the resolution of the three-dimensional detector. Therefore, the technical solution of the present application can improve the stability and reliability of the three-dimensional detector, and can further improve the performance of the three-dimensional detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0042] Figure 1 A process flow chart of a method for preparing a three-dimensional detector provided in an embodiment of the present application;

[0043] Figure 2 A cross-sectional view of a three-dimensional detector provided in an embodiment of the present application;

[0044] Figure 3 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application;

[0045] Figure 4 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application;

[0046] Figure 5 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application;

[0047] Figure 6 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application;

[0048] Figure 7 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application;

[0049] Figure 8-Figure 29 A product structure diagram of a three-dimensional detector manufacturing method at different process stages provided in an embodiment of the present application;

[0050] Figure 30-Figure 44 A product structure diagram of a three-dimensional detector manufacturing method at different process stages provided in an embodiment of the present application;

[0051] Figure 45-Figure 48 The front electrode layout structures of four different three-dimensional detectors provided in the embodiments of the present application;

[0052] Fig.49 A three-dimensional schematic diagram of a groove electrode and a central electrode in a three-dimensional detector provided in an embodiment of the present application;

[0053] Fig.50 A three-dimensional schematic diagram of a groove electrode and a central electrode in another three-dimensional detector provided in an embodiment of the present application.

[0054] Reference numerals:

[0055] 11-semiconductor substrate; 111-semiconductor base; 112-semiconductor device layer; 113-insulating buried layer; 12-central electrode; 120-central columnar hole; 121-first doping type polysilicon; 13-trench electrode; 130-trench; 131-second doping type polysilicon; 14-metal interconnect layer; 141-first metal electrode; 142-second metal electrode; 15-equipotential electric field plane; 16-target doping region; 171-first isolation ring; 172-second isolation ring; 18-conductive hole; 19-top silicon oxide layer; 21-second mask layer; 22-first mask layer; 23-passivation layer; 25-third mask layer; 24-fourth mask layer. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0057] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0058] refer to Figure 1 and Figure 2, Figure 1 A process flow chart of a method for preparing a three-dimensional detector provided in an embodiment of the present application, Figure 2 A cross-sectional view of a three-dimensional detector provided in an embodiment of the present application.

[0059] like Figure 1 and Figure 2 As shown, the method for preparing the three-dimensional detector provided in the embodiment of the present application includes:

[0060] Step S11 : providing a semiconductor substrate 11 , wherein the semiconductor substrate 11 comprises a semiconductor base 111 and a semiconductor device layer 112 located on a surface of one side of the semiconductor base 111 .

[0061] Step S12 : forming a central electrode 12 and a trench electrode 13 surrounding the central electrode 12 in the semiconductor device layer 112 , wherein the central electrode 12 and the trench electrode 13 have different doping types.

[0062] In the embodiment of the present application, the different doping types of two objects indicate that one is P-type doped and the other is N-type doped.

[0063] Step S13 : forming a metal interconnection layer 14 on the surface of the semiconductor device layer 112 , wherein the metal interconnection layer includes a first metal electrode 141 and a second metal electrode 142 . The first metal electrode 141 is connected to the central electrode 12 , and the second metal electrode 142 is connected to the trench electrode 13 .

[0064] Among them, the trench electrode 13 is located on the same closed equipotential electric field plane 15 towards the bottom of the semiconductor substrate 111, and the depth of the central electrode 12 in the semiconductor device layer 112 does not exceed the equipotential electric field plane 15; the equipotential electric field plane 15 is the bottom surface of the semiconductor device layer 112 facing the semiconductor substrate 111.

[0065] In the three-dimensional detector formed by the preparation method provided in the embodiment of the present application, the trench electrodes 13 are located on the same closed equipotential electric field plane 15 toward the bottom of the semiconductor substrate 111, and the depth of the central electrode 12 in the semiconductor device layer 112 does not exceed the equipotential electric field plane 15. In this way, the bottom of the trench electrode 13 can form a uniform electric field distribution based on the equipotential electric field plane 15, thereby improving the irradiation performance and charge collection efficiency of the three-dimensional detector.

[0066] In addition, the bottom of the groove electrode 13 has a uniform electric field distribution, which can also avoid signal distortion and delay problems caused by non-uniform electric field distribution, obtain clearer signal output, and improve the resolution of the three-dimensional detector.

[0067] It can be seen from the above description that the preparation method provided in the embodiment of the present application can improve the stability and reliability of the three-dimensional detector and can further improve the performance of the three-dimensional detector.

[0068] In one implementation of the present application, the Figure 2 As shown, the bottoms of the groove electrode 13 and the central electrode 12 are both extended and stopped at the equipotential electric field plane 15 .

[0069] refer to Figure 3 , Figure 3 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application, Figure 2 The difference between the methods shown is that Figure 3 In the three-dimensional detector shown, the groove electrode 13 extends and stops at the equipotential electric field plane 15 , and the central electrode 12 stops above the equipotential electric field plane 15 and has a preset distance from the equipotential electric field plane 15 .

[0070] exist Figure 3 In the manner shown, the groove electrode 13 extends and stops at the equipotential electric field plane 15, and based on the equipotential electric field plane 15, the bottom of the groove electrode 13 can form a uniform electric field distribution based on the equipotential electric field plane 15, thereby improving the irradiation performance and charge collection efficiency of the three-dimensional detector. In addition, the central electrode 12 stops above the equipotential electric field plane 15 and has a preset distance from the equipotential electric field plane 15, which can optimize and adjust the electric field and resistance characteristics at the bottom of the central electrode 12, thereby preventing the breakdown problem caused by the electric field concentration of the central electrode 12, and improving the reliability and stability of the three-dimensional detector.

[0071] exist Figure 3 In the shown manner, the central electrode 12 stops above the equipotential electric field plane 15 and has a preset distance from the equipotential electric field plane 15. Based on the preset distance, a portion of the semiconductor device layer 112 is retained between the central electrode 12 and the equipotential electric field plane 15 to adjust and optimize the electric field and resistance characteristics at the bottom of the central electrode 12.

[0072] refer to Figure 4 , Figure 4 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application, Figure 3 The difference between the methods shown is that Figure 4 In the three-dimensional detector shown, a target doping region 16 is formed between the central electrode 12 and the equipotential electric field plane 15 , and the doping concentration of the target doping region 16 is lower than the doping concentration of the central electrode 12 .

[0073] Since the doping concentration of the target doping region 16 is lower than the doping concentration of the central electrode 12 , the electric field and resistance characteristics at the bottom of the central electrode 12 can be better adjusted and optimized based on the high-low junction formed based on the difference in doping concentration.

[0074] Optionally, the doping type of the target doping region 16 is different from the doping type of the central electrode 12 , so that a PN junction can be formed at the bottom of the central electrode 12 , and the electric field and resistance characteristics at the bottom of the central electrode 12 can be better adjusted and optimized through the PN junction.

[0075] exist Figure 4 In the method shown, a central columnar hole having a depth less than the thickness of the semiconductor device layer 112 can be prepared first, and ion implantation can be performed based on the central columnar hole to form a target doping region 16 in the semiconductor device layer 112 exposed at the bottom of the central columnar hole, and then a semiconductor material can be filled in the central columnar hole to form a central electrode 12 in the central columnar hole.

[0076] exist Figure 4 In the manner shown, a central columnar hole having a depth equal to the thickness of the semiconductor device layer 112 may also be formed, and the desired target doping region 16 may be deposited in the central columnar hole.

[0077] refer to Figure 5 , Figure 5 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application, Figure 4 The difference between the methods shown is that Figure 5 In the three-dimensional detector shown, after the target doping region 16 is formed, the target doping region 16 is annealed so that the target doping region 16 surrounds the bottom side wall of the central electrode 12 to better protect the central electrode 12 .

[0078] exist Figure 2-Figure 5 In the illustrated method, the semiconductor substrate 11 is a silicon-on-insulator (SOI) as an example for illustration. The semiconductor device layer 112 is the top silicon layer of the SOI, the semiconductor base 111 is the bottom silicon layer of the SOI, and there is an insulating buried layer 113 between the top silicon layer and the bottom silicon layer; the equipotential electric field plane 15 is the interface between the top silicon layer and the insulating buried layer.

[0079] If the semiconductor substrate 11 is silicon on insulator, the bottom of the trench electrode 13 and the central electrode 12 can be arranged to extend and stop at the interface between the top silicon layer and the insulating buried layer, that is, stop at the equipotential electric field plane 15; or the trench electrode 13 can be arranged to extend and stop at the interface, and the central electrode 12 stops above the interface.

[0080] refer to Figure 6 , Figure 6A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application, in which the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111; the doping concentration of the semiconductor epitaxial layer is less than the doping concentration of the semiconductor substrate 111; and the equipotential electric field plane 15 is the interface between the semiconductor epitaxial layer and the semiconductor substrate 111. This method can use the top surface of the semiconductor substrate 111 with a relatively high doping concentration as the equipotential electric field plane 15 to form a uniform electric field distribution at the bottom of the trench electrode 13.

[0081] Alternatively, if Figure 6 As shown, if the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111, the bottom of the trench electrode 13 extends to the interface; the bottom of the central electrode 12 stops above the interface and has a preset distance from the interface.

[0082] In other embodiments, the bottom of the groove electrode 13 can also extend below the interface, with any height between the bottom and top surfaces of the semiconductor substrate 111 as the equipotential electric field plane 15; at this time, the bottom of the central electrode 12 stops above the interface and has a preset distance from the interface.

[0083] If the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111 , as described in the above embodiment, a target doping region 16 may also be set between the central electrode 12 and the equipotential electric field plane 15 . The implementation method is different from the above embodiment, and the embodiment of the present application will not be illustrated separately.

[0084] refer to Figure 7 , Figure 7 A cross-sectional view of another three-dimensional detector provided in an embodiment of the present application, based on any of the above implementations, Figure 7 In the illustrated embodiment, it further includes: forming an isolation ring in the surface of the semiconductor device layer 112. The isolation ring includes: at least one first isolation ring 171; and / or, at least one second isolation ring 172. The depth of the first isolation ring 171 and the second isolation ring 172 are both less than the depth of the central electrode 12; the first isolation ring 171 surrounds the trench electrode 13; and the second isolation ring 172 is located between the central electrode 12 and the trench electrode 13.

[0085] exist Figure 7 In the illustrated manner, the three-dimensional detector is described as having both the first isolation ring 171 and the second isolation ring 172. It is obvious that in the embodiment of the present application, the three-dimensional detector may only have the first isolation ring 171, or only have the second isolation ring 172, or both the first isolation ring 171 and the second isolation ring 172 are provided.

[0086] If the three-dimensional detector has a first isolation ring 171, the number of the first isolation ring 171 can be 1 or any plural number greater than 1. If the three-dimensional detector has a second isolation ring 172, the number of the second isolation ring 172 can be 1 or any plural number greater than 1. The embodiment of the present application does not limit the number of the first isolation ring 171 and the second isolation ring 172.

[0087] exist Figure 6 In the method shown, SOI is used as an example to illustrate the implementation method of the isolation ring. If the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111, at least one first isolation ring 171 can also be formed on the surface of the semiconductor device layer 112; and / or, at least one second isolation ring 172. This embodiment of the present application will not be illustrated separately.

[0088] In one implementation of the embodiment of the present application, a method for forming a central electrode 12 and a trench electrode 13 surrounding the central electrode 12 in a semiconductor device layer 112 may include: first, forming a central columnar hole in the semiconductor device layer 112, the depth of the central columnar hole not exceeding the equipotential electric field plane 15; then, filling the central columnar hole with a first semiconductor material to form the central electrode 12; further, forming a trench surrounding the central electrode 12 in the semiconductor device layer 112, the bottom of the trench extending to the equipotential electric field plane 15; finally, filling the trench with a second semiconductor material to form the trench electrode 13. In this method, the central electrode 12 is formed first, and then the trench electrode 13 is formed.

[0089] In another way, the method of forming the central electrode 12 and the trench electrode 13 surrounding the central electrode 12 in the semiconductor device layer 112 may include: first, forming a trench in the semiconductor device layer 112; then, filling the first semiconductor material in the trench to form the trench electrode 13; further, forming a central columnar hole in the semiconductor device layer 112 surrounded by the trench electrode 13, the depth of the central columnar hole not exceeding the equipotential electric field plane 15; finally, filling the second semiconductor material in the central columnar hole to form the central electrode 12. In this way, the trench electrode 13 is formed first, and then the central electrode 12 is formed.

[0090] refer to Figure 8-Figure 29 , Figure 8-Figure 29 A product structure diagram of a three-dimensional detector preparation method at different process stages provided in an embodiment of the present application, wherein the preparation method is illustrated using SOI preparation of a three-dimensional detector as an example.

[0091] like Figure 8-Figure 29 As shown, the preparation method comprises:

[0092] Step S211: Figure 8 As shown, SOI is provided.

[0093] In this step, photolithography may be performed on the top silicon surface of the SOI to form an alignment mark.

[0094] Step S212: Fig. 9 As shown, the SOI is thermally oxidized to form a silicon oxide layer on its upper and lower surfaces respectively. Optionally, the thickness of the silicon oxide layer can be 1 μm or other thickness.

[0095] Step S213: Fig.10 As shown, the top silicon oxide layer 19 is subjected to photolithography and etching to form an opening, and ion lithography is performed based on the opening to form a first isolation ring 171 .

[0096] Step S214: First, Fig.11 As shown, silicon oxide is deposited by PECVD to increase the thickness of the top silicon oxide layer 19. The thickness of the deposited silicon oxide can be 700 nm or other thicknesses. At this time, the thickness of the top silicon oxide layer 19 can be 1.5 μm or other thicknesses. Then, as Fig.12 As shown, the top silicon oxide layer 19 is planarized by using CMP or dry etching process, and 1 μm or other thickness of the top silicon oxide layer 19 can be removed, and 700 nm or other thickness of the top silicon oxide layer 19 can be retained.

[0097] Step S215: First, Fig.13 As shown, a patterned first mask layer 22 is formed on the surface of the top silicon oxide layer 19, and then Fig.14 As shown, the top silicon oxide layer 19 is etched based on the first mask layer 22, and then Fig.15 As shown, based on the etched top silicon oxide layer 19 and the patterned first mask layer 22, the top silicon layer is etched to form a central columnar hole 120. Finally, as shown in FIG. Fig.16 As shown, the first mask layer 22 is removed.

[0098] In this step, the depth of the central columnar hole 120 is the same as the thickness of the top silicon layer. If the thickness of the top silicon layer is 5 μm, the depth of the central columnar hole 120 is 5 μm. If the thickness of the top silicon layer is 30-300 μm, the depth of the central columnar hole 120 is 30-300 μm.

[0099] Step S216: First, Fig.17 As shown, a first doping type polysilicon 121 is deposited in the central columnar hole 120, and then, as shown in FIG. Fig.18 As shown, the first doped type polysilicon 121 on the surface of the top silicon oxide layer 19 is removed by a CMP process, and the first doped type polysilicon 121 in the central columnar hole 120 is retained to form the central electrode 12.

[0100] Step S217: Fig.19 As shown, silicon oxide is deposited to increase the thickness of the top silicon oxide layer 19 and make the top silicon oxide layer 19 cover the top of the central electrode 12. Optionally, the thickness of the silicon oxide deposited in this step can be 2000Å or other thicknesses.

[0101] Step S218: First, Fig. 20 As shown, a second mask layer 21 is formed on the surface of the top silicon oxide layer 19, and then, as shown in FIG. Fig.21 As shown, based on the photolithography patterning of the second mask layer 21, an opening is formed in the region of the second mask layer 21 corresponding to the trench electrode 13, and then as shown in FIG. Fig. 22 As shown, based on the patterned second mask layer 21, the pattern of the second mask layer 21 is transferred to the top silicon oxide layer 19, and finally as shown in FIG. Fig.23 As shown, based on the patterned second mask layer 21 and the top silicon oxide layer 19 , the top silicon layer is etched to form a trench 130 .

[0102] The depth of the groove 130 is the same as the thickness of the top silicon layer. In the embodiment of the present application, the etching depths of the groove 130 and the central columnar hole 120 are set to extend to the top surface of the insulating buried layer 113, and the insulating buried layer 113 is used as an etching stop layer to facilitate the control of the etching depths of the groove 130 and the central columnar hole 120.

[0103] Step S219: First, Fig.24 As shown, the second doping type polysilicon 131 is filled in the trench 130, and then, as shown in FIG. Fig.25 As shown, the second doped type polysilicon 131 on the surface of the top silicon oxide layer 19 is removed by a CMP process, and the second doped type polysilicon 131 in the trench 130 is retained to form a trench electrode 13.

[0104] Step S220: Fig.26 As shown, silicon oxide is deposited to increase the thickness of the top silicon oxide layer 19, and the top silicon oxide layer 19 covers the top of the central electrode 12 and the trench electrode 13. Optionally, the thickness of the silicon oxide deposited in this step can be 3000Å ​​or other thicknesses.

[0105] Step S221: First, Fig. 27 As shown, conductive holes 18 are formed in the top silicon oxide layer 19 above the central electrode 12 and the trench electrode 13, respectively. Fig.28 As shown, a metal interconnection layer 14 is formed on the surface of the top silicon oxide layer 19, and the metal interconnection layer includes a first metal electrode 141 and a second metal electrode 142. The first metal electrode 141 is connected to the central electrode 12, and the second metal electrode 142 is connected to the trench electrode 13. Finally, as shown in FIG. Fig.29As shown, a patterned passivation layer 23 is formed on the surface of the top silicon oxide layer 19 , and the passivation layer has an opening exposing the first metal electrode 141 and the second metal electrode 142 .

[0106] The conductive hole 18 may include metal tungsten filled in the through hole. The conductive hole 18 at least extends downward to the top surface of the corresponding central electrode 12 or the top surface of the corresponding groove electrode 13. In order to achieve better electrical contact, the conductive hole 18 may be arranged to extend downward to the inside of the corresponding central electrode 12 or the inside of the groove electrode 13.

[0107] exist Figure 8-Figure 29 In the illustrated method, SOI is used as an example to illustrate the preparation method provided in the embodiment of the present application. Other process methods for preparing three-dimensional detectors based on SOI can be prepared in the same way, and the embodiment of the present application will not be illustrated separately.

[0108] refer to Figure 30-Figure 44 , Figure 30-Figure 44 A product structure diagram of a three-dimensional detector preparation method at different process stages provided in an embodiment of the present application, wherein the preparation method takes the semiconductor epitaxial layer on the surface of the semiconductor substrate 111 as the semiconductor device layer 112 as an example to illustrate the preparation method of the three-dimensional detector.

[0109] like Figure 30-Figure 44 As shown, the preparation method comprises:

[0110] Step S311: Fig.30 As shown, a semiconductor substrate 11 is provided, in which a semiconductor base 111 is a lightly doped silicon base, and a semiconductor epitaxial layer on the surface of the lightly doped silicon base can be a P-type epitaxial layer with a thickness of 50 μm or other thicknesses.

[0111] Step S312: Fig.31 As shown, a top silicon oxide layer 19 is formed on the surface of the semiconductor device layer 112 by a thermal oxidation process, and a patterned third mask layer 25 is formed on the surface of the top silicon oxide layer 19. The third mask layer 25 may be a photoresist layer.

[0112] Step S313: First, Fig.32 As shown, the top silicon oxide layer 19 is etched based on the third mask layer 25, and the pattern structure of the third mask layer 25 is transferred to the top silicon oxide layer 19. Fig.33 As shown, based on the patterned third mask layer 25 and the top silicon oxide layer 19 , a trench 130 is formed in the semiconductor device layer 112 .

[0113] The trench 130 extends to the interface between the semiconductor substrate 111 and the semiconductor device layer 112 , and the interface is an equipotential electric field plane 15 .

[0114] Step S314: Fig.34 As shown, in-situ doping can be performed based on the trench 130, and the second doping type polysilicon 131 can be filled in the trench 130. Fig.35 As shown, the second doped type polysilicon 131 on the surface of the top silicon oxide layer 19 is removed by etching back or CMP, and the second doped type polysilicon 131 in the trench 130 is retained, thereby forming the trench electrode 13. The second doped type polysilicon 131 can be P++ doped polysilicon.

[0115] Step S315: Fig.36 As shown, silicon oxide is deposited by PECVD to increase the thickness of the top silicon oxide layer 19 so that the top silicon oxide layer 19 covers the top of the trench electrode 13 .

[0116] Step S316: Fig.37 As shown, a patterned fourth mask layer 24 is formed on the surface of the top silicon oxide layer 19, and then Fig.38 As shown, the top silicon oxide layer 19 is etched based on the fourth mask layer 24, and the pattern structure of the fourth mask layer 24 is transferred to the top silicon oxide layer 19. Fig.39 As shown, based on the patterned fourth mask layer 24 and the top silicon oxide layer 19 , the semiconductor device layer 112 is etched to form a central columnar hole 120 . The bottom of the central columnar hole 120 is located above the equipotential electric field plane 15 .

[0117] Step S317: Fig.40 As shown, after the first doping type polysilicon 121 is in-situ doped in the central columnar hole 120, as shown in FIG. Fig.41 As shown, the first doped type polysilicon 121 on the surface of the top silicon oxide layer 19 is removed by etching back or CMP process, and the first doped type polysilicon 121 in the central columnar hole 120 is retained as the central electrode 12. The first doped type polysilicon 121 can be N++ doped polysilicon.

[0118] Step S318: Fig.42 As shown, silicon oxide is deposited to thicken the top silicon oxide layer 19 so that the top silicon oxide layer 19 covers the top of the central electrode 12 and the trench electrode 13, and then a through hole is formed to expose the central electrode 12 and the trench electrode 13. Fig.43 As shown, metal tungsten is deposited in the through hole to form a conductive hole 18.

[0119] Step S319: Fig.44As shown, a metal interconnection layer 14 is formed on the surface of the top silicon oxide layer 19 , and the metal interconnection layer includes a first metal electrode 141 and a second metal electrode 142 . The first metal electrode 141 is connected to the central electrode 12 , and the second metal electrode 142 is connected to the trench electrode 13 .

[0120] The first metal electrode 141 and the second metal electrode 142 can be connected to the corresponding central electrode 12 and the groove electrode 13 through a plurality of conductive holes 18, respectively, to reduce the contact resistance. In other embodiments, the first metal electrode 141 and the second metal electrode 142 can be connected to the corresponding central electrode 12 and the groove electrode 13 through one conductive hole 18, respectively.

[0121] From the above description, it can be seen that the preparation method provided in the embodiment of the present application can prepare a thin three-dimensional detector based on an epitaxial silicon substrate or an SOI substrate. The preparation method includes laser marking, cleaning, gluing, photolithography, etching, dry gluing, oxide layer growth, deep silicon etching, in-situ doping, CMP, annealing, conductive hole etching, metal magnetron sputtering, metal patterning, passivation and other processes.

[0122] The preparation method provided in the embodiment of the present application has a simple process and is convenient for mass production of three-dimensional detectors. The prepared three-dimensional detectors can be used in large scientific devices, proton therapy micro-metrology, X-ray single photon detectors and other fields.

[0123] The etching process required in the corresponding process steps in the preparation method can be any one of the etching processes such as wet etching, dry etching, Bosch process and laser etching, and the corresponding etching process is not limited in the embodiment of the present application.

[0124] If an SOI substrate is used, a SOI substrate with a top silicon layer of ultra-pure high-resistance silicon can be selected according to application requirements. The thickness of the top silicon layer can be customized, ranging from a few microns to hundreds of microns, and can be selected according to different etching processes. The thickness of the top silicon layer in the SOI substrate can be 5 to 20 microns, and the thickness of the insulating buried layer 113 can be 1 to 3 microns. SOI substrates of other sizes are all within the protection scope of the technical solution of the embodiment of this application.

[0125] Based on the preparation method provided in the above embodiment, another embodiment of the present application further provides a three-dimensional detector. As shown in the accompanying drawings provided in the above embodiment, the three-dimensional detector includes:

[0126] A semiconductor substrate 11, wherein the semiconductor substrate 11 includes a semiconductor base 111 and a semiconductor device layer 112 located on a surface of one side of the semiconductor base 111;

[0127] A central electrode 12 and a trench electrode 13 surrounding the central electrode 12 are disposed in the semiconductor device layer 112, and the central electrode 12 and the trench electrode 13 have different doping types;

[0128] A metal interconnection layer 14 is disposed on the surface of the semiconductor device layer 112, wherein the metal interconnection layer 14 includes a first metal electrode 141 and a second metal electrode 142, wherein the first metal electrode 141 is connected to the central electrode 12, and the second metal electrode 142 is connected to the trench electrode 13;

[0129] The trench electrodes 13 are located on the same closed equipotential electric field plane 15 facing the bottom of the semiconductor substrate 111 , and the depth of the central electrode 12 in the semiconductor device layer 112 does not exceed the equipotential electric field plane 15 .

[0130] The first metal electrode 141 and the second metal electrode 142 are connected to the central electrode 12 and the trench electrode 13 respectively through at least one conductive hole 18. Before forming the conductive hole 18, the top silicon oxide layer 19 can be leveled by etching back or CMP process, and then the conductive hole 18 is formed. The metal filled in the conductive hole 18 is not limited to metal tungsten, and can also be other metal materials, such as aluminum or copper.

[0131] Optionally, the semiconductor substrate 11 is silicon on insulator, the semiconductor device layer 112 is the top silicon layer of the silicon on insulator, the semiconductor base 111 is the bottom silicon layer of the silicon on insulator, and there is an insulating buried layer 113 between the top silicon layer and the bottom silicon layer; the equipotential electric field plane 15 is the interface between the top silicon layer and the insulating buried layer 113; the bottom of the trench electrode 13 and the central electrode 12 both extend and stop at the interface; or, the trench electrode 13 extends and stops at the interface, and the central electrode 12 stops above the interface.

[0132] Or, the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111; the doping concentration of the semiconductor epitaxial layer is lower than the doping concentration of the semiconductor substrate 111, so the resistivity of the semiconductor epitaxial layer is greater than the resistivity of the semiconductor substrate 111; the equipotential electric field plane 15 is the interface between the semiconductor epitaxial layer and the semiconductor substrate 111; the bottom of the trench electrode 13 extends to the interface; the bottom of the central electrode 12 stops above the interface and has a preset distance from the interface.

[0133] If the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111, in order to make the bottom of the trench electrode 13 have a more uniform electric field, the trench electrode 13 penetrates the semiconductor epitaxial layer so that the bottom of the trench electrode 13 at least extends to the top surface of the semiconductor substrate 111 with low impedance, or extends to the inside of the semiconductor substrate 111. The bottom of the central electrode 12 is located above the semiconductor substrate 111, and the depth is less than the thickness of the semiconductor epitaxial layer.

[0134] Optionally, an isolation ring is provided inside the semiconductor device layer 112, and the isolation ring includes at least one first isolation ring 171 and / or at least one second isolation ring 172; wherein the depth of the first isolation ring 171 and the second isolation ring 172 are both less than the depth of the central electrode 12; the first isolation ring 171 surrounds the trench electrode 13; and the second isolation ring 172 is located between the central electrode 12 and the trench electrode 13.

[0135] If the semiconductor device layer 112 is a semiconductor epitaxial layer on the surface of the semiconductor substrate 111 , the thickness of the semiconductor epitaxial layer may be 5-500 μm, and the semiconductor epitaxial layer has a higher resistance than the semiconductor substrate 111 .

[0136] If the semiconductor substrate 11 is an SOI substrate, the thickness of the top silicon layer can be 5~20μm, and the thickness of the insulating buried layer 113 can be 1~3μm. SOI substrates of other sizes are also within the protection scope of the technical solution of the embodiment of the application. The thickness of each layer structure in the SOI substrate is not limited to the numerical range provided in the application embodiment.

[0137] In the embodiment of the present application, as described above, the trench electrode 13 and the central electrode 12 can be formed by an etching process (such as a Bosch process) and an in-situ doping process. The width of the trench electrode 13 and the central electrode 12 can be 0.54 to 5 μm. One of the trench electrode 13 and the central electrode 12 is N-type doped (such as phosphorus doped), and the other is P-type doped (such as boron doped), and the doping concentration can be 1×10 19 cm -3 ~3×10 20 cm -3 .

[0138] In the three-dimensional detector, in the semiconductor device layer 112, the depth and width of the electrode are positively correlated. The greater the electrode depth, the greater its width, so as to ensure the reliability and stability of the electrode in the semiconductor device layer 112. For example, when the electrode width is 994nm, the depth can be 35.5μm; when the electrode width is 1.98μm, the electrode depth can be 43.2μm; when the electrode width is 2.84μm, the electrode depth can be 51.9μm.

[0139] refer to Figure 45-Figure 48 , Figure 45-Figure 48 The front electrode layout structures of four different three-dimensional detectors provided in the embodiments of the present application. Figure 45-Figure 48 Both are plan views of the groove electrode 13 and the central electrode 12 on the front side of the three-dimensional detector.

[0140] exist Fig.45In the illustrated embodiment, the central electrode 12 is a square hole electrode connected to the first metal electrode 141 based on a conductive hole 18; the groove electrode 13 is a square frame electrode connected to the second metal electrode 142 based on multiple conductive holes 18 located in the same row.

[0141] exist Fig.46 In the illustrated embodiment, the central electrode 12 is a square hole electrode connected to the first metal electrode 141 based on four conductive holes 18 arranged in a 2×2 pattern; the groove electrode 13 is a square frame electrode connected to the second metal electrode 142 based on multiple conductive holes 18 arranged in two rows.

[0142] exist Fig.47 In the illustrated embodiment, the central electrode 12 is a circular hole electrode, connected to the first metal electrode 141 based on two conductive holes 18; the groove electrode 13 is a circular ring electrode, connected to the second metal electrode 142 based on multiple conductive holes 18 on half of the circular ring electrode.

[0143] exist Fig.48 In the illustrated embodiment, the central electrode 12 is a circular hole electrode, connected to the first metal electrode 141 based on a conductive hole 18; the groove electrode 13 is a circular ring electrode, connected to the second metal electrode 142 based on multiple conductive holes 18 on half of the circular ring electrode.

[0144] In the embodiment of the present application, the pattern structure of the central electrode 12 and the groove electrode 13 and the number and arrangement of the connected conductive holes 18 can be set according to the needs, and are not limited to Figure 45-Figure 48 The method shown.

[0145] refer to Fig.49 , Fig.49 A three-dimensional schematic diagram of a groove electrode and a central electrode in a three-dimensional detector provided in an embodiment of the present application. In this embodiment, the central electrode 12 is a cylindrical electrode, and the groove electrode 13 is a cylindrical electrode surrounding the circumferential electrode.

[0146] refer to Fig.50 , Fig.50 This is a three-dimensional schematic diagram of a groove electrode and a central electrode in another three-dimensional detector provided in an embodiment of the present application. In this embodiment, the central electrode 12 is a cylindrical electrode, and the groove electrode 13 is a square tube electrode surrounding the circumferential electrode.

[0147] In the embodiment of the present application, in the three-dimensional view, the central electrode 12 can be a cylindrical electrode, a prismatic electrode, etc.; the groove electrode 13 can be a cylindrical electrode, a square cylindrical electrode or other polygonal cylindrical electrodes. In the two-dimensional top view of the front side, the groove electrode 13 can be a closed graphic structure or a non-closed graphic structure, not limited to Fig.49 and Fig.50 The method shown.

[0148] In the three-dimensional detector, one of the central electrode 12 and the groove electrode 13 is P-type doped, and the other is N-type doped. If the central electrode 12 is used as a readout electrode, it can be P-type doped, and the groove electrode 13 can be N-type doped. In this case, the three-dimensional detector is a hole collection detector. If the central electrode is N-type doped and the groove electrode 13 is P-type doped, the three-dimensional detector can be used as an electron collection detector.

[0149] In the embodiment of the present application, the semiconductor substrate 111 includes Si, Ge, GaN, SiC, HgI 2 , GaAs, TiBr, CdTe, CdZnTe, CdSe, GaP, HgS, PbI 2 And one or more combinations of materials such as AlSb, etc. The embodiment of the present application does not limit the material of the semiconductor substrate 111.

[0150] The size of the three-dimensional detector can be set according to the application field. For example, the device size may be different in applications in strong radiation environments such as lidar detection, medical diagnosis, large scientific equipment, aerospace, etc., and the embodiments of the present application do not limit this.

[0151] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. The implementation methods provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0152] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0153] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0154] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0155] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a three-dimensional detector, characterized in that: The preparation method comprises: Providing a semiconductor substrate, the semiconductor substrate comprising a semiconductor base and a semiconductor device layer located on a surface of one side of the semiconductor base; forming a central electrode and a trench electrode surrounding the central electrode in the semiconductor device layer, wherein the central electrode and the trench electrode have different doping types; forming a metal interconnection layer on the surface of the semiconductor device layer, the metal interconnection layer comprising a first metal electrode and a second metal electrode, the first metal electrode being connected to the central electrode, and the second metal electrode being connected to the trench electrode; Wherein, the trench electrodes are located on the same closed equipotential electric field plane toward the bottom of the semiconductor substrate, and the depth of the central electrode in the semiconductor device layer does not exceed the equipotential electric field plane; the equipotential electric field plane is the bottom surface of the semiconductor device layer toward the semiconductor substrate.

2. The preparation method according to claim 1, characterized in that: The semiconductor substrate is a silicon-on-insulator, the semiconductor device layer is a top silicon layer of the silicon-on-insulator, the semiconductor base is a bottom silicon layer of the silicon-on-insulator, and an insulating buried layer is provided between the top silicon layer and the bottom silicon layer; The equipotential electric field plane is the interface between the top silicon layer and the insulating buried layer.

3. The preparation method according to claim 2, characterized in that: The bottoms of the groove electrode and the central electrode both extend and stop at the interface; Alternatively, the trench electrode extends and stops at the interface, and the central electrode stops above the interface.

4. The preparation method according to claim 1, characterized in that: The semiconductor device layer is a semiconductor epitaxial layer on the surface of the semiconductor substrate; the doping concentration of the semiconductor epitaxial layer is less than the doping concentration of the semiconductor substrate; The equipotential electric field plane is the interface between the semiconductor epitaxial layer and the semiconductor substrate.

5. The preparation method according to claim 4, characterized in that: The bottom of the trench electrode extends to the interface; The bottom of the central electrode stops above the interface and has a preset distance from the interface.

6. The preparation method according to claim 1, characterized in that: Forming a central electrode and a trench electrode surrounding the central electrode in the semiconductor device layer, comprising: forming a central columnar hole in the semiconductor device layer, wherein the depth of the central columnar hole does not exceed the equipotential electric field plane; Filling the central columnar hole with a first semiconductor material to form the central electrode; forming a trench surrounding the central electrode in the semiconductor device layer, wherein the bottom of the trench extends to the equipotential electric field plane; Filling a second semiconductor material in the trench to form the trench electrode; or, forming a trench in the semiconductor device layer; Filling the first semiconductor material in the trench to form the trench electrode; forming a central columnar hole in the semiconductor device layer surrounded by the trench electrode, wherein the depth of the central columnar hole does not exceed the equipotential electric field plane; The central columnar hole is filled with a second semiconductor material to form the central electrode.

7. The preparation method according to claim 1, characterized in that: Also includes: forming an isolation ring in the semiconductor device layer, the isolation ring comprising at least one first isolation ring and at least one second isolation ring; Wherein, the depths of the first isolation ring and the second isolation ring are both less than the depth of the central electrode; the first isolation ring surrounds the groove electrode; The second isolation ring is located between the central electrode and the trench electrode.

8. A three-dimensional detector formed by the preparation method according to any one of claims 1 to 7, characterized in that: The three-dimensional detector comprises: A semiconductor substrate, comprising a semiconductor base and a semiconductor device layer located on a surface of one side of the semiconductor base; A central electrode disposed in the semiconductor device layer and a trench electrode surrounding the central electrode, wherein the central electrode and the trench electrode have different doping types; A metal interconnection layer disposed on the surface of the semiconductor device layer, the metal interconnection layer comprising a first metal electrode and a second metal electrode, the first metal electrode being connected to the central electrode, and the second metal electrode being connected to the trench electrode; Wherein, the trench electrodes are located on the same closed equipotential electric field plane toward the bottom of the semiconductor substrate, and the depth of the central electrode in the semiconductor device layer does not exceed the equipotential electric field plane; the equipotential electric field plane is the bottom surface of the semiconductor device layer toward the semiconductor substrate.

9. The three-dimensional detector according to claim 8, characterized in that: The semiconductor substrate is a silicon-on-insulator, the semiconductor device layer is a top silicon layer of the silicon-on-insulator, the semiconductor base is a bottom silicon layer of the silicon-on-insulator, and an insulating buried layer is provided between the top silicon layer and the bottom silicon layer; The equipotential electric field plane is the interface between the top silicon layer and the insulating buried layer; the bottoms of the trench electrode and the central electrode both extend and stop at the interface; or, the trench electrode extends and stops at the interface, and the central electrode stops above the interface; Or, the semiconductor device layer is a semiconductor epitaxial layer on the surface of the semiconductor substrate; The equipotential electric field plane is the interface between the semiconductor epitaxial layer and the semiconductor substrate; The doping concentration of the semiconductor epitaxial layer is less than the doping concentration of the semiconductor substrate; the bottom of the trench electrode extends to the interface; the bottom of the central electrode stops above the interface and has a preset distance from the interface.

10. The three-dimensional detector according to claim 8, characterized in that: An isolation ring is arranged in the semiconductor device layer, wherein the isolation ring includes at least one first isolation ring and / or at least one second isolation ring; The depths of the first isolation ring and the second isolation ring are both smaller than the depth of the central electrode; the first isolation ring surrounds the groove electrode; and the second isolation ring is located between the central electrode and the groove electrode.

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