Rapid discharging circuit suitable for high-voltage LDO and discharging method thereof

Abstract

The invention discloses a rapid discharge circuit suitable for a high-voltage LDO and a discharge method thereof, the rapid discharge circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a current source I0 and a Zener diode Z2, the source electrodes of the PMOS tubes M1, M2 and M3 are connected with an input power supply Vin, the PMOS tubes M1, M2 and M3 form a current mirror, the drain electrode of the NMOS tube M4 and the NMOS tube M6 form a current mirror, an input signal EN controls the NMOS tube M7, and the Zener diode Z2 limits the grid voltage of the NMOS tube M5. According to the high-voltage LDO, the function of rapidly discharging the output signal Vout in the turn-off state of the high-voltage LDO can be achieved through a small turn-off current and a simple circuit structure.

Description

Technical Field

[0001] The present invention relates to a discharge circuit and a discharge method thereof, in particular to a fast discharge circuit and a discharge method thereof suitable for a high-voltage LDO, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] In order to meet the needs of high-voltage application scenarios, it is usually necessary to use a high-voltage LDO to provide a stable power supply voltage for various electronic devices. Generally, a large capacitor of uF level is connected at the output stage. This causes the output to discharge slowly when the high-voltage LDO is powered off, but it can continue to provide power to subsequent devices for a period of time, resulting in disordered power-on and power-off timing of subsequent devices, causing functional abnormalities. To solve this problem, the conventional approach is to connect a fast discharge branch at the output stage of the high-voltage LDO to ensure that the power output can be quickly pulled down when the power is off.

[0003] like Figure 2 As shown, in the traditional high-voltage LDO structure, the pre-voltage divider circuit converts the power supply Vin into the internal power supply voltage VDD, providing a suitable power supply voltage for the low-voltage part of the high-voltage LDO, wherein the input signal EN controls the working state of the pull-down MOS tube M5 of the output Vout through an inverter. When the input signal EN is low, that is, the circuit is in the off state, the input signal EN outputs a high level through the inverter to turn on the MOS tube M5, and the output Vout is quickly discharged. However, this requires that the internal power supply voltage VDD is still at a high level when the LDO is turned off, which increases the leakage path of the power supply to the ground of the high-voltage LDO in the off state, which will greatly increase the off current of the entire high-voltage LDO. Therefore, the traditional high-voltage LDO cannot simultaneously take into account the low off current and the fast discharge of the output Vout in the off state. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a fast discharge circuit and a discharge method suitable for a high-voltage LDO, so as to realize a fast discharge function of an output signal Vout in a shutdown state of the high-voltage LDO with a relatively small shutdown current.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A fast discharge circuit suitable for high-voltage LDO, comprising a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a current source I0 and a Zener diode Z2, wherein the source of the PMOS tube M1, the source of the PMOS tube M2 and the source of the PMOS tube M3 are connected to an input power supply Vin, the gate of the PMOS tube M1 is connected to the drain of the PMOS tube M1, one end of the current source I0, the gate of the PMOS tube M2 and the gate of the PMOS tube M3, the drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the NMOS tube M5 and the gate of the PMOS tube M6. The gate of M4 is connected to the gate of NMOS tube M6, the drain of PMOS tube M3 is connected to the drain of NMOS tube M6, the cathode of Zener diode Z2 and the gate of NMOS tube M5 are connected, the source of NMOS tube M6 is connected to the drain of NMOS tube M7, the gate of NMOS tube M7 is connected to the input signal EN, the drain of NMOS tube M5 is connected to the output signal Vout, the other end of current source I0, the source of NMOS tube M4, the source of NMOS tube M7, the anode of Zener diode Z2 and the source of NMOS tube M5 are grounded, wherein the pull-down capability of NMOS tube M6 is stronger than the pull-up capability of PMOS tube M3.

[0006] Furthermore, a gate protection circuit is provided at the gate of the NMOS transistor M7.

[0007] Furthermore, the gate protection circuit includes a resistor R1 and a Zener diode Z1, one end of the resistor R1 is connected to the input signal EN, the other end of the resistor R1 is connected to the cathode of the Zener diode Z1 and the gate of the NMOS tube M7, and the anode of the Zener diode Z1 is grounded.

[0008] Furthermore, the gate voltage of the NMOS tube M7 does not exceed the voltage V Z1 , voltage V Z1 Equal to the reverse breakdown voltage of Zener diode Z1.

[0009] Furthermore, the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 have the same width-to-length ratio, the number ratio of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 is 1:1:m, and the currents flowing through the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 are I1, I2 and I3 respectively, and the current of the current source I0 is I0, then I3=m*I2=m*I1=m*I0.

[0010] Furthermore, the width-to-length ratios of the NMOS tubes M4 and M6 are the same, the number ratio of the NMOS tubes M4 and M6 is 1:n, and the currents flowing through the NMOS tubes M4 and M6 are I4 and I6 respectively, then I6=n*I4=n*I0, and n>m.

[0011] A discharge method based on a fast discharge circuit suitable for a high-voltage LDO comprises the following steps: When the input signal EN is at a high level, the high-voltage LDO is in a normal working state, and the NMOS tube M7 works in the linear region, that is, the NMOS tube M7 is turned on, and at this time, the branch where the PMOS tube M3 is located and the branch where the NMOS tube M6 is located are turned on at the same time. Since the pull-down ability of the NMOS tube M6 is stronger than the pull-up ability of the PMOS tube M3, at this time, the gate voltage of the NMOS tube M5 is pulled down to the ground by the NMOS tube M6, and the NMOS tube M5 is in a turned-off state, which has no effect on the output signal Vout, and the output signal Vout is output normally; When the input signal EN is at a low level, the high-voltage LDO is in the off state, and the NMOS tube M7 works in the cut-off region, that is, the NMOS tube M7 is turned off. At this time, the branch where the PMOS tube M3 is located is turned on and the branch where the NMOS tube M6 is located is turned off. The gate of the NMOS tube M5 is pulled up to the voltage V through the PMOS tube M3. Z2 , voltage V Z2 It is equal to the reverse breakdown voltage of the Zener diode Z2, and the NMOS tube M5 is in the on state, providing a fast discharge path for the output signal Vout of the high-voltage LDO when the circuit is turned off.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a fast discharge circuit and a discharge method suitable for a high-voltage LDO, the control signal for pulling down the NMOS tube M5 is generated in the voltage domain of the input signal Vin, and when the circuit is turned off, even if the internal power supply voltage VDD after pre-division is at a low level, the NMOS tube M5 can still be turned on normally to quickly discharge the output signal Vout, and the present invention can realize the fast discharge function of the output signal Vout when the high-voltage LDO is turned off with a small turn-off current and a simple circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a fast discharge circuit suitable for high-voltage LDO of the present invention.

[0014] Figure 2 is a schematic diagram of a high voltage LDO with a fast discharge path in the prior art. DETAILED DESCRIPTION

[0015] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0016] like Figure 1 As shown, a fast discharge circuit suitable for a high-voltage LDO of the present invention comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a current source I0 and a Zener diode Z2, the source of the PMOS tube M1, the source of the PMOS tube M2 and the source of the PMOS tube M3 are connected to an input power supply Vin, the gate of the PMOS tube M1 is connected to the drain of the PMOS tube M1, one end of the current source I0, the gate of the PMOS tube M2 and the gate of the PMOS tube M3, the drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the NMOS tube M5 and the NMOS tube M6, and the gate of the PMOS tube M7. The gate of the MOS tube M4 is connected to the gate of the NMOS tube M6, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M6, the cathode of the Zener diode Z2 and the gate of the NMOS tube M5, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M7, the gate of the NMOS tube M7 is connected to the input signal EN, the drain of the NMOS tube M5 is connected to the output signal Vout, the other end of the current source I0, the source of the NMOS tube M4, the source of the NMOS tube M7, the anode of the Zener diode Z2 and the source of the NMOS tube M5 are grounded, wherein the pull-down capability of the NMOS tube M6 is stronger than the pull-up capability of the PMOS tube M3.

[0017] Zener diode Z2 makes the gate voltage of NMOS tube M5 not higher than voltage V Z2 , voltage V Z2 It is equal to the reverse breakdown voltage of the Zener diode Z2. Therefore, in actual operation, since the input signal Vin is larger than that, when the gate of the NMOS tube M5 is at a high level, it is equal to the voltage V Z2 In this way, even if the input signal Vin is larger than the internal voltage VDD, the circuit can still operate stably and safely.

[0018] The gate of the NMOS tube M7 is provided with a gate protection circuit, which includes a resistor R1 and a Zener diode Z1, one end of the resistor R1 is connected to the input signal EN, the other end of the resistor R1 is connected to the cathode of the Zener diode Z1 and the gate of the NMOS tube M7, and the anode of the Zener diode Z1 is grounded.

[0019] The gate voltage of NMOS tube M7 does not exceed the voltage V Z1 , voltage V Z1 It is equal to the reverse breakdown voltage of the Zener diode Z1, thereby protecting the NMOS tube M7.

[0020] The width-to-length ratios of the PMOS tubes M1, M2 and M3 are the same, the number ratio of the PMOS tubes M1, M2 and M3 is 1:1:m, assuming that the currents flowing through the PMOS tubes M1, M2 and M3 are I1, I2 and I3 respectively, and the current of the current source I0 is I0, then I3=m*I2=m*I1=m*I0.

[0021] The width-to-length ratio of the NMOS tube M4 and the NMOS tube M6 is the same, and the number ratio of the NMOS tube M4 to the NMOS tube M6 is 1:n. Assuming that the currents flowing through the NMOS tube M4 and the NMOS tube M6 are I4 and I6 respectively, then I6=n*I4=n*I0, and n>m, that is, the pull-down capability of the NMOS tube M6 is stronger than the pull-up capability of the PMOS tube M3.

[0022] A discharge method based on a fast discharge circuit suitable for a high-voltage LDO comprises the following steps: When the input signal EN is at a high level, the high-voltage LDO is in a normal working state, and the NMOS tube M7 works in a linear region, which can be regarded as a switch tube in a conducting state, that is, the NMOS tube M7 is turned on, and at this time, the branch where the PMOS tube M3 and the branch where the NMOS tube M6 are located are turned on at the same time. Since the pull-down ability of the NMOS tube M6 is stronger than the pull-up ability of the PMOS tube M3, at this time, the gate voltage of the NMOS tube M5 is pulled down to the ground by the NMOS tube M6, and the NMOS tube M5 is in a turned-off state, which has no effect on the output signal Vout, and the output signal Vout is output normally.

[0023] When the input signal EN is at a low level, the high-voltage LDO is in the off state, and the NMOS tube M7 works in the cut-off region, which can be regarded as a switch tube in the off state, that is, the NMOS tube M7 is turned off, at this time, the branch where the PMOS tube M3 is located is turned on and the branch where the NMOS tube M6 is located is turned off, and the gate of the NMOS tube M5 is pulled up to the voltage V through the PMOS tube M3. Z2 , voltage V Z2 It is equal to the reverse breakdown voltage of the Zener diode Z2, and the NMOS tube M5 is in the on state, providing a fast discharge path for the output signal Vout of the high-voltage LDO when the circuit is turned off.

[0024] A fast discharge circuit suitable for a high-voltage LDO of the present invention adopts an input signal Vin as an input voltage instead of VDD generated inside the high-voltage LDO. Thus, even if the high-voltage LDO is turned off and VDD is at a low level, the operation of the fast discharge circuit suitable for the high-voltage LDO of the present invention is not affected.

[0025] The present invention provides a fast discharge circuit and a discharge method suitable for a high-voltage LDO. The control signal of a pull-down NMOS tube M5 is generated in the voltage domain of an input signal Vin. When the circuit is turned off, even if the internal power supply voltage VDD after pre-division is at a low level, the NMOS tube M5 can still be turned on normally to quickly discharge the output signal Vout. The present invention can realize the fast discharge function of the output signal Vout when the high-voltage LDO is turned off with a small turn-off current and a simple circuit structure.

[0026] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A fast discharge circuit suitable for high voltage LDO, characterized in that: The invention comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a current source I0 and a Zener diode Z2, wherein the source of the PMOS tube M1, the source of the PMOS tube M2 and the source of the PMOS tube M3 are connected to the input power supply Vin, the gate of the PMOS tube M1 is connected to the drain of the PMOS tube M1, one end of the current source I0, the gate of the PMOS tube M2 and the gate of the PMOS tube M3, the drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the gate of the NMOS tube M4 and the NMOS The gate of the S transistor M6 is connected, the drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M6, the cathode of the Zener diode Z2 and the gate of the NMOS transistor M5, the source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M7, the gate of the NMOS transistor M7 is connected to the input signal EN, the drain of the NMOS transistor M5 is connected to the output signal Vout, the other end of the current source I0, the source of the NMOS transistor M4, the source of the NMOS transistor M7, the anode of the Zener diode Z2 and the source of the NMOS transistor M5 are grounded, wherein the pull-down capability of the NMOS transistor M6 is stronger than the pull-up capability of the PMOS transistor M3.

2. A fast discharge circuit suitable for high voltage LDO according to claim 1, characterized in that: The gate of the NMOS tube M7 is provided with a gate protection circuit.

3. A fast discharge circuit suitable for high voltage LDO according to claim 2, characterized in that: The gate protection circuit includes a resistor R1 and a Zener diode Z1. One end of the resistor R1 is connected to the input signal EN, the other end of the resistor R1 is connected to the cathode of the Zener diode Z1 and the gate of the NMOS tube M7, and the anode of the Zener diode Z1 is grounded.

4. The fast discharge circuit suitable for high voltage LDO according to claim 3, characterized in that: The gate voltage of the NMOS tube M7 does not exceed the voltage V Z1 , voltage V Z1 Equal to the reverse breakdown voltage of Zener diode Z1.

5. The fast discharge circuit suitable for high voltage LDO according to claim 1, characterized in that: The PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 have the same width-to-length ratio, the number ratio of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 is 1:1:m, assuming that the currents flowing through the PMOS tube M1, the PMOS tube M2 and the PMOS tube M3 are I1, I2 and I3 respectively, and the current of the current source I0 is I0, then I3=m*I2=m*I1=m*I0.

6. A fast discharge circuit suitable for high voltage LDO according to claim 5, characterized in that: The width-to-length ratio of the NMOS tube M4 and the NMOS tube M6 is the same, the number ratio of the NMOS tube M4 and the NMOS tube M6 is 1:n, and the currents flowing through the NMOS tube M4 and the NMOS tube M6 are I4 and I6 respectively, then I6=n*I4=n*I0, and n>m.

7. A discharge method based on the fast discharge circuit suitable for high-voltage LDO according to any one of claims 1 to 6, characterized in that The following steps are involved: When the input signal EN is at a high level, the high-voltage LDO is in a normal working state, and the NMOS tube M7 works in the linear region, that is, the NMOS tube M7 is turned on, and at this time, the branch where the PMOS tube M3 is located and the branch where the NMOS tube M6 is located are turned on at the same time. Since the pull-down ability of the NMOS tube M6 is stronger than the pull-up ability of the PMOS tube M3, at this time, the gate voltage of the NMOS tube M5 is pulled down to the ground by the NMOS tube M6, and the NMOS tube M5 is in a turned-off state, which has no effect on the output signal Vout, and the output signal Vout is output normally; When the input signal EN is at a low level, the high-voltage LDO is in the off state, and the NMOS tube M7 works in the cut-off region, that is, the NMOS tube M7 is turned off. At this time, the branch where the PMOS tube M3 is located is turned on and the branch where the NMOS tube M6 is located is turned off. The gate of the NMOS tube M5 is pulled up to the voltage V through the PMOS tube M3. Z2 , voltage V Z2 It is equal to the reverse breakdown voltage of the Zener diode Z2, and the NMOS tube M5 is in the on state, providing a fast discharge path for the output signal Vout of the high-voltage LDO when the circuit is turned off.

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