An EMI low-pass filter with integrated electrostatic and surge protection functions

Abstract

The present invention provides an EMI low-pass filter with integrated electrostatic and surge protection functions, including a first TVS structure provided with a first P-type well region and a grounded P+ heavily doped active region, a second TVS structure provided with a floating second P-type well region and a grounded P+ heavily doped active region, an N+ heavily doped active region provided in the first P-type well region and the second P-type well region, the bottom of the N-type semiconductor substrate is grounded, a vertical forward ESD path is formed between the N+ heavily doped active region in the first P-type well region and the bottom of the N-type semiconductor substrate, a horizontal reverse ESD path is formed between the P+ heavily doped active region of the first TVS structure and the N+ heavily doped active region in the first P-type well region, and the second TVS structure also forms a forward ESD path and a reverse ESD path. The beneficial effects of the present invention are: it can realize high-frequency signal suppression function, electrostatic and surge protection capabilities.

Description

Technical Field

[0001] The invention relates to the technical field of filters, and in particular to an EMI low-pass filter with integrated electrostatic and surge protection functions. Background Art

[0002] Electromagnetic Interference (EMI) refers to the interference source (usually electronic equipment) coupling the signal on its own electrical network to another electrical network through conductive media (such as cables) or space radiation. Filters are a good EMI solution that can allow specific frequency components in the signal to pass through while greatly attenuating or suppressing other frequency components. For some applications, filters can remove noise or harmonics that interfere with normal signals within the system. For example, signal processing circuits such as digital signals, communications, audio, images, video compression, and sensor outputs can use low-pass filters to effectively filter out high-frequency noise and retain low-frequency signal components, thereby improving signal quality.

[0003] Electrostatic discharge (ESD) refers to a phenomenon in which the charge accumulated by the human body or material is discharged to the surrounding objects through a conductive channel. The use of transient voltage suppressors (TVS) can provide efficient electrostatic protection for electronic circuits.

[0004] At present, the design and application environment of electronic products are complex. Electromagnetic interference and electrostatic discharge are the two most common phenomena in the application environment of electronic equipment. They can cause electronic products to fail and reduce the reliability of electronic products. In recent years, as electronic products tend to be miniaturized, the system complexity is higher, and the signal transmission frequency and speed inside the electronic system are getting faster and faster, EMI and ESD problems have become increasingly serious. The independent or joint occurrence of EMI and ESD events will interfere with and reduce the signal integrity of electronic products, and in severe cases, even damage the internal circuits of electronic products.

[0005] Figure 1 (a) is a schematic diagram of the circuit structure of an existing typical p-type CRC low-pass filter. The low-pass filter circuit is composed of 1 resistor and 2 capacitors in series and parallel. Figure 1 (b) is a schematic diagram of the S21 curve of a typical p-type CRC low-pass filter. S21 is the insertion loss, which reflects the amplitude and phase changes of the signal when it passes through the device under test. The cut-off frequency refers to the frequency at which the filter begins to attenuate signals of a specific frequency. At this time, the low-pass filter cannot normally transmit signals higher than this frequency. The cut-off frequency is usually specified at the -3 dB point, indicating that f -3dBThe corresponding output signal has dropped to 0.707 times of the maximum value. However, this circuit can only achieve filtering function.

[0006] Figure 2 (a) is a schematic diagram of the circuit structure of an existing EMI low-pass filter with integrated electrostatic and surge protection functions. This design scheme uses the parasitic capacitance of the TVS to the ground as the capacitor in the CRC low-pass filter circuit, which can simultaneously play the role of electrostatic protection, surge protection and low-pass filtering. Figure 2 (b) is a schematic diagram of the structure using a PNP type TVS as a filter capacitor, but this design has the following problems: (1) Usually the capacitor in the CRC low-pass filter circuit determines the -3 dB cutoff bandwidth. After the cutoff bandwidth is determined, the parasitic capacitance of the TVS tube to the ground is also determined; (2) If the surge protection capability of the filter is to be enhanced, the TVS tube must be designed to be large. Therefore, in order to take into account the requirements of parasitic capacitance, it is usually inclined to reduce the parasitic capacitance per unit area of ​​the TVS tube. Therefore, a floating PNP tube is usually used as the TVS tube; (3) However, due to its small current gain, the surge protection capability of the PNP type TVS tube is still not ideal under the same parasitic capacitance and layout area. If NPN TVS tubes are used, under the same parasitic capacitance and layout area, the product's surge protection level and clamping voltage can be further significantly improved due to its higher current gain and stronger electrostatic discharge capability. However, in actual design, due to the common ground requirements of p-type CRC low-pass filters and the need for floating base regions, unidirectional NPN TVS tubes are usually difficult to use in the design of p-type CRC low-pass filters. Summary of the invention

[0007] In order to solve the problems in the prior art, the present invention provides an EMI low-pass filter with integrated electrostatic and surge protection functions. By arranging a first TVS structure, a second TVS structure and a resistor R that cooperate with each other in the EMI low-pass filter with integrated electrostatic and surge protection functions, the first TVS structure, the second TVS structure and the resistor R can form a filtering circuit. The first TVS structure includes an NPN transistor Q1 and a PNP transistor Q3, and the second TVS structure includes an NPN transistor Q2 and a PNP transistor Q4. The first TVS structure and the second TVS structure are used as capacitors in the low-pass filtering circuit, which can achieve attenuation and suppression of high-frequency signals while providing excellent electrostatic and surge protection capabilities, and the layout area is small, which solves the problem that the typical p-type CRC low-pass filter in the prior art can only achieve the filtering function, and the TVS tube of the EMI low-pass filter with integrated electrostatic and surge protection functions will occupy a huge layout area.

[0008] The present invention provides an EMI low-pass filter with integrated electrostatic and surge protection functions, comprising an N-type semiconductor substrate and a first TVS structure, a second TVS structure and a resistor R arranged on the N-type semiconductor substrate, wherein the first TVS structure, the second TVS structure and the resistor R can form a filter circuit, wherein the first TVS structure is provided with a floating first P-type well region and a grounded P+ heavily doped active region, the second TVS structure is provided with a floating second P-type well region and a grounded P+ heavily doped active region, the first P-type well region is provided with an N+ heavily doped active region connected to an I / O port 1, the bottom of the N-type semiconductor substrate is grounded, and the first P-type well region is provided with an N+ heavily doped active region connected to an I / O port 1. A vertical forward ESD path is formed between the N+ heavily doped active area and the bottom of the N-type semiconductor substrate, a horizontal reverse ESD path is formed between the P+ heavily doped active area of ​​the first TVS structure and the N+ heavily doped active area in the first P-type well area, an N+ heavily doped active area connected to I / O port 2 is provided in the second P-type well area, a vertical forward ESD path is formed between the N+ heavily doped active area in the second P-type well area and the bottom of the N-type semiconductor substrate, and a horizontal reverse ESD path is formed between the P+ heavily doped active area of ​​the second TVS structure and the N+ heavily doped active area in the second P-type well area.

[0009] The present invention is further improved, wherein the first TVS structure includes an NPN transistor Q1 and a PNP transistor Q3, and the second TVS structure includes an NPN transistor Q2 and a PNP transistor Q4, the collector of the NPN transistor Q1 is connected to the I / O port one and one end of the resistor R, the base of the NPN transistor Q1 is floating and connected to the collector of the PNP transistor Q3, the collector of the NPN transistor Q2 is connected to the I / O port two and the other end of the resistor R, the base of the NPN transistor Q2 is floating and connected to the collector of the PNP transistor Q4, and the emitter of the NPN transistor Q1, the base of the PNP transistor Q3, the emitter of the PNP transistor Q3, the emitter of the NPN transistor Q2, the base of the PNP transistor Q4, and the emitter of the PNP transistor Q4 are grounded.

[0010] The present invention is further improved in that the resistor R is a P-type active region resistor.

[0011] The present invention is further improved in that the resistor R is an N-type active region resistor.

[0012] The present invention is further improved, wherein the resistor R is an N-well resistor or a P-well resistor or a polysilicon resistor.

[0013] The present invention is further improved, the P+ heavily doped active area in the first TVS structure and the P+ heavily doped active area in the second TVS structure are connected to the bottom of the N-type semiconductor substrate, and the connection method is to connect through wiring or a redistribution layer during packaging, or to connect through metal interconnects during PCB board integration.

[0014] The present invention is further improved, that is, a metal conductive layer is provided on the top of the N-type semiconductor substrate, the P+ heavily doped active area in the first TVS structure is grounded through the metal conductive layer, the N+ heavily doped active area in the first P-type well area is connected to I / O port one through the metal conductive layer, the P+ heavily doped active area in the second TVS structure is grounded through the metal conductive layer, and the N+ heavily doped active area in the second P-type well area is connected to I / O port two through the metal conductive layer.

[0015] The present invention is further improved, and a contact hole is also provided on the top of the N-type semiconductor substrate, the P+ heavily doped active area in the first TVS structure is connected to the metal conductive layer through the contact hole, the N+ heavily doped active area in the first P-type well area is connected to the metal conductive layer through the contact hole, the P+ heavily doped active area in the second TVS structure is connected to the metal conductive layer through the contact hole, and the N+ heavily doped active area in the second P-type well area is connected to the metal conductive layer through the contact hole.

[0016] The present invention is further improved, the first P-type well region and the second P-type well region are merged into a large P-type well region, the resistor R is an N-type active area resistor and is arranged in the large P-type well region, two vertical forward ESD paths are formed between the N+ heavily doped active area in the large P-type well region and the bottom of the N-type semiconductor substrate, two horizontal reverse ESD paths are formed between the P+ heavily doped active area in the first TVS structure, the P+ heavily doped active area in the second TVS structure and the N+ heavily doped active area in the large P-type well region, and the two forward ESD paths of the large P-type well region and the two reverse ESD paths form a pair of bidirectional ESD channels.

[0017] The present invention is further improved in that three large P-type well regions are provided on the N-type semiconductor substrate, and each of the large P-type well regions has a pair of bidirectional ESD channels.

[0018] Compared with the prior art, the present invention has the following beneficial effects: providing an EMI low-pass filter with integrated electrostatic and surge protection functions, by arranging a first TVS structure, a second TVS structure and a resistor R that cooperate with each other in the EMI low-pass filter with integrated electrostatic and surge protection functions, the first TVS structure, the second TVS structure and the resistor R can form a filter circuit, the first TVS structure includes an NPN transistor Q1 and a PNP transistor Q3, the second TVS structure includes an NPN transistor Q2 and a PNP transistor Q4, and the first TVS structure and the second TVS structure are used as capacitors in the low-pass filter circuit, so that the filter It can not only suppress high-frequency signals, but also provide excellent electrostatic protection and surge protection capabilities. It can achieve attenuation suppression of high-frequency signals while providing excellent electrostatic and surge protection capabilities. It has a small layout area, which can save manufacturing costs and packaging costs. It has a wide range of applications and can meet the requirements of various applications. It provides a good integrated solution for electrostatic protection and electromagnetic interference filtering of electronic circuits, and solves the problem that the typical p-type CRC low-pass filter in the prior art can only achieve filtering functions, and the TVS tube of the EMI low-pass filter with integrated electrostatic and surge protection functions occupies a huge layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] FIG. 1 (a) is a schematic diagram of a circuit structure of a typical existing p-type CRC low-pass filter;

[0021] FIG1( b ) is a schematic diagram of an insertion loss curve of a typical existing p-type CRC low-pass filter;

[0022] FIG. 2 (a) is a schematic diagram of the circuit structure of an existing EMI low-pass filter integrating electrostatic and surge protection functions;

[0023] FIG2 (b) is a schematic diagram of the structure of an existing voltage regulator tube used as a filter capacitor;

[0024] FIG3 (a) is a schematic structural diagram of a first embodiment of an EMI low-pass filter with integrated electrostatic and surge protection functions according to the present invention;

[0025] FIG3( b ) is a circuit diagram of a first embodiment of an EMI low-pass filter with integrated electrostatic and surge protection functions according to the present invention;

[0026] FIG3( c ) is an IV characteristic curve of the first embodiment of the EMI low-pass filter with integrated electrostatic and surge protection functions of the present invention;

[0027] FIG4 (a) is a schematic structural diagram of a second embodiment of an EMI low-pass filter with integrated electrostatic and surge protection functions according to the present invention;

[0028] FIG4( b ) is a circuit diagram of a second embodiment of an EMI low-pass filter with integrated electrostatic and surge protection functions according to the present invention;

[0029] Figure 5 It is a schematic structural diagram of a third embodiment of the EMI low-pass filter with integrated electrostatic and surge protection functions of the present invention. DETAILED DESCRIPTION

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0031] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0033] As shown in Figure 3 (a) - Figure 5As shown, the present invention provides an EMI low-pass filter with integrated electrostatic and surge protection functions, including an N-type semiconductor substrate and a first TVS structure, a second TVS structure and a resistor R arranged on the N-type semiconductor substrate, the resistor R being a P-type active area resistor, the first TVS structure, the second TVS structure and the resistor R being able to form a filter circuit, the first TVS structure being provided with a floating first P-type well area and a grounded P+ heavily doped active area, the second TVS structure being provided with a floating second P-type well area and a grounded P+ heavily doped active area, the first P-type well area being provided with an N+ heavily doped active area connected to an I / O port 1, the bottom of the N-type semiconductor substrate being grounded, the second TVS structure being provided with a floating second P-type well area and a grounded P+ heavily doped active area, the first P-type well area being provided with an N+ heavily doped active area connected to an I / O port 1, the bottom of the N-type semiconductor substrate being grounded, and the second TVS structure being provided with a floating second P-type well area and a grounded P+ heavily doped active area. A vertical forward ESD path is formed between an N+ heavily doped active region in a P-type well region and the bottom of an N-type semiconductor substrate, a horizontal reverse ESD path is formed between the P+ heavily doped active region of the first TVS structure and the N+ heavily doped active region in the first P-type well region, an N+ heavily doped active region connected to an I / O port 2 is provided in the second P-type well region, a vertical forward ESD path is formed between the N+ heavily doped active region in the second P-type well region and the bottom of the N-type semiconductor substrate, and a horizontal reverse ESD path is formed between the P+ heavily doped active region of the second TVS structure and the N+ heavily doped active region in the second P-type well region.

[0034] As shown in Figure 3 (a) - Figure 5 As shown, 100 represents a P-type semiconductor substrate, 200, 300, 400 represent an N-type semiconductor substrate, 110, 113 represent an N-type well region, 210 represents a first P-type well region, 212 represents a second P-type well region, 310, 410, 420, 430 represent a large P-type well region, 112, 115, 201, 301, 401 represent a P+ heavily doped active region, 202, 101, 312, 412, 422, 432 represent resistors R, 111, 114, 211, 213, 31 1, 313, 411, 413, 421, 423, 431, 433 represent N+ heavily doped active areas, 130 represents a metal conductive layer, 140 represents a contact hole, 120, 170, 190 represent metal interconnects connecting I / O port 1 and I / O port 1, 150, 180, 191 represent metal interconnects connecting I / O port 2 and I / O port 2, and 160 represents a metal interconnect that shorts the top GND and the bottom GND of an N-type semiconductor substrate off-chip (at the packaging level or board-level integration).

[0035] As shown in FIG. 3( a ) and FIG. 3( b ), as a first embodiment of the present invention, the first TVS structure of this embodiment includes an NPN transistor Q1 and a PNP transistor Q3, and the second TVS structure includes an NPN transistor Q2 and a PNP transistor Q4. The collector of the NPN transistor Q1 is connected to the I / O port 1 and one end of the resistor R, the base of the NPN transistor Q1 is floating and connected to the collector of the PNP transistor Q3, the collector of the NPN transistor Q2 is connected to the I / O port 2 and the other end of the resistor R, the base of the NPN transistor Q2 is floating and connected to the collector of the PNP transistor Q4, and the emitter of the NPN transistor Q1, the base of the PNP transistor Q3, the emitter of the PNP transistor Q3, the emitter of the NPN transistor Q2, the base of the PNP transistor Q4, and the emitter of the PNP transistor Q4 are grounded.

[0036] The resistor R can be an N-type active area resistor, an N-well resistor, a P-well resistor, or a polysilicon resistor; the P+ heavily doped active area in the first TVS structure and the P+ heavily doped active area in the second TVS structure are connected to the bottom of the N-type semiconductor substrate, and the connection method is to connect through a wire bonding or a redistribution layer during packaging, or to connect through a metal interconnection line during PCB board integration; a metal conductive layer is provided on the top of the N-type semiconductor substrate, the P+ heavily doped active area in the first TVS structure is grounded through the metal conductive layer, the N+ heavily doped active area in the first P-type well region is connected to the I / O port one through the metal conductive layer, and the second TVS structure is connected to the I / O port one through the metal conductive layer. The P+ heavily doped active area in the second TVS structure is grounded through the metal conductive layer, and the N+ heavily doped active area in the second P-type well area is connected to the I / O port 2 through the metal conductive layer; a contact hole is also provided on the top of the N-type semiconductor substrate, the P+ heavily doped active area in the first TVS structure is connected to the metal conductive layer through the contact hole, the N+ heavily doped active area in the first P-type well area is connected to the metal conductive layer through the contact hole, the P+ heavily doped active area in the second TVS structure is connected to the metal conductive layer through the contact hole, and the N+ heavily doped active area in the second P-type well area is connected to the metal conductive layer through the contact hole.

[0037] In this embodiment, firstly, a p-type CRC low-pass filter is constructed by using a first TVS structure composed of an NPN transistor Q1 and a PNP transistor Q3, a second TVS structure composed of an NPN transistor Q2 and a PNP transistor Q4, and a resistor R. Under the premise of meeting the filtering index, the surge and electrostatic protection capabilities can be significantly improved, and the clamping voltage can be optimized. The IV characteristic curve thereof is shown in FIG3 (c). Secondly, the first TVS structure composed of an NPN transistor Q1 and a PNP transistor Q3, and the second TVS structure composed of an NPN transistor Q2 and a PNP transistor Q4 both adopt a planar / vertical hybrid TVS architecture. In the structure, a forward ESD path, i.e., a forward NPN electrostatic discharge path, is realized, and in the planar structure, a reverse ESD path, i.e., a reverse PNPN electrostatic discharge path, is realized; in addition, the reverse PNPN electrostatic discharge path is composed of a P+ heavily doped active region, an N-type semiconductor substrate, a floating first P-type well region or a second P-type well region, and an N+ heavily doped active region. The conduction characteristics of the PNPN four-layer path are similar to those of a diode, and it is composed of a PNP and an NPN forming a positive feedback loop; moreover, the top GND and the bottom GND of the N-type semiconductor substrate can be connected by wire bonding or RDL (Re-distributed layer) during packaging, or can be connected by metal interconnection lines during PCB (Printed circuit board) board-level integration, or the upper and lower GNDs can be not short-circuited during application. At this time, the top GND is floating, and the first TVS structure composed of the NPN transistor Q1 and the PNP transistor Q3 and the second TVS structure composed of the NPN transistor Q2 and the PNP transistor Q4 become bidirectional.

[0038] As shown in FIG. 4 (a) to FIG. 4 (b), as the second embodiment of the present invention, the difference between this embodiment and the first embodiment is that the first P-type well region and the second P-type well region are merged into a large P-type well region, the resistor R is an N-type active region resistor and is arranged in the large P-type well region, and two vertical forward ESD paths are formed between the N+ heavily doped active region in the large P-type well region and the bottom of the N-type semiconductor substrate, and two horizontal reverse ESD paths are formed between the P+ heavily doped active region in the first TVS structure, the P+ heavily doped active region in the second TVS structure, and the N+ heavily doped active region in the large P-type well region. The two forward ESD paths in the large P-type well region and the two reverse ESD paths form a pair of bidirectional ESD channels. In this embodiment, the first TVS structure composed of the NPN transistor Q1 and the PNP transistor Q3, the second TVS structure composed of the NPN transistor Q2 and the PNP transistor Q4, and the resistor R can further share the same P-well, that is, a large P-type well area, which can reduce the overall size and enhance the isolation between the resistor R and the N-type semiconductor substrate.

[0039] like Figure 5 As shown, as the third embodiment of the present invention, the difference between this embodiment and the second embodiment is that three large P-type well regions are provided on the N-type semiconductor substrate, and each large P-type well region has a pair of bidirectional ESD channels. In this embodiment, the structure includes a total of three pairs of bidirectional ESD channels, namely three input ports and three output ports, and each pair of bidirectional ESD channels can be electrically isolated. Of course, the number of the large P-type well regions can also be adjusted according to specific circuit requirements.

[0040] The manufacturing process of an EMI low-pass filter with integrated electrostatic and surge protection functions of the present invention is applicable to various common integrated circuit manufacturing processes, such as nano-scale complementary metal oxide semiconductor (CMOS) process, three-dimensional fin field effect transistor (FinField-EffectTransistor, FinFET) or gate-all-around FET (GAA) process, or silicon-on-insulator (SOI) process, etc.

[0041] As can be seen from the above, the present invention provides an EMI low-pass filter with integrated electrostatic and surge protection functions. By arranging a first TVS structure, a second TVS structure and a resistor R that cooperate with each other in the EMI low-pass filter with integrated electrostatic and surge protection functions, the first TVS structure, the second TVS structure and the resistor R can form a filter circuit. The first TVS structure includes an NPN transistor Q1 and a PNP transistor Q3, and the second TVS structure includes an NPN transistor Q2 and a PNP transistor Q4. The first TVS structure and the second TVS structure are used as capacitors in the low-pass filter circuit, so that the filter can not only It can suppress high-frequency signals and provide excellent electrostatic protection and surge protection. It can achieve attenuation suppression of high-frequency signals while providing excellent electrostatic and surge protection. It has a small layout area, which can save manufacturing cost and packaging cost. It has a wide range of applications and can meet the requirements of various applications. It provides a good integrated solution for electrostatic protection and electromagnetic interference filtering of electronic circuits, and solves the problem that the typical p-type CRC low-pass filter in the prior art can only realize the filtering function, and the TVS tube of the EMI low-pass filter with integrated electrostatic and surge protection functions occupies a huge layout area.

[0042] The specific implementation modes described above are preferred implementation modes of the present invention, and are not intended to limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to the specific implementation modes, and all equivalent changes made according to the present invention are within the protection scope of the present invention.

Claims

1. An EMI low-pass filter with integrated electrostatic and surge protection functions, characterized in that: The invention comprises an N-type semiconductor substrate and a first TVS structure, a second TVS structure and a resistor R arranged on the N-type semiconductor substrate, wherein the first TVS structure, the second TVS structure and the resistor R can form a filter circuit, the first TVS structure is provided with a floating first P-type well region and a grounded P+ heavily doped active region, the second TVS structure is provided with a floating second P-type well region and a grounded P+ heavily doped active region, the first P-type well region is provided with an N+ heavily doped active region connected to an I / O port 1, the bottom of the N-type semiconductor substrate is grounded, the N+ heavily doped active region in the first P-type well region is connected to the N-type semiconductor substrate, and the N+ heavily doped active region in the first P-type well region is connected to the N-type semiconductor substrate. A vertical forward ESD path is formed between the bottom of the conductor substrate, a horizontal reverse ESD path is formed between the P+ heavily doped active area of ​​the first TVS structure and the N+ heavily doped active area in the first P-type well area, an N+ heavily doped active area connected to I / O port 2 is provided in the second P-type well area, a vertical forward ESD path is formed between the N+ heavily doped active area in the second P-type well area and the bottom of the N-type semiconductor substrate, and a horizontal reverse ESD path is formed between the P+ heavily doped active area of ​​the second TVS structure and the N+ heavily doped active area in the second P-type well area.

2. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 1, characterized in that: The first TVS structure includes an NPN transistor Q1 and a PNP transistor Q3, and the second TVS structure includes an NPN transistor Q2 and a PNP transistor Q4. The collector of the NPN transistor Q1 is connected to the I / O port one and one end of the resistor R, the base of the NPN transistor Q1 is floating and connected to the collector of the PNP transistor Q3, the collector of the NPN transistor Q2 is connected to the I / O port two and the other end of the resistor R, the base of the NPN transistor Q2 is floating and connected to the collector of the PNP transistor Q4, and the emitter of the NPN transistor Q1, the base of the PNP transistor Q3, the emitter of the PNP transistor Q3, the emitter of the NPN transistor Q2, the base of the PNP transistor Q4, and the emitter of the PNP transistor Q4 are grounded.

3. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 2, characterized in that: The resistor R is a P-type active region resistor.

4. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 2, characterized in that: The resistor R is an N-type active region resistor.

5. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 2, characterized in that: The resistor R is an N-well resistor, a P-well resistor, or a polysilicon resistor.

6. The EMI low-pass filter with integrated electrostatic and surge protection functions according to any one of claims 3 to 5, characterized in that: The P+ heavily doped active area in the first TVS structure and the P+ heavily doped active area in the second TVS structure are connected to the bottom of the N-type semiconductor substrate, and the connection method is to connect through wiring or a redistribution layer during packaging, or to connect through metal interconnects during PCB board integration.

7. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 6, characterized in that: A metal conductive layer is provided on the top of the N-type semiconductor substrate, the P+ heavily doped active area in the first TVS structure is grounded through the metal conductive layer, the N+ heavily doped active area in the first P-type well area is connected to I / O port one through the metal conductive layer, the P+ heavily doped active area in the second TVS structure is grounded through the metal conductive layer, and the N+ heavily doped active area in the second P-type well area is connected to I / O port two through the metal conductive layer.

8. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 7, characterized in that: A contact hole is also provided on the top of the N-type semiconductor substrate, and the P+ heavily doped active area in the first TVS structure is connected to the metal conductive layer through the contact hole, the N+ heavily doped active area in the first P-type well area is connected to the metal conductive layer through the contact hole, the P+ heavily doped active area in the second TVS structure is connected to the metal conductive layer through the contact hole, and the N+ heavily doped active area in the second P-type well area is connected to the metal conductive layer through the contact hole.

9. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 2 or 8, characterized in that: The first P-type well region and the second P-type well region are merged into a large P-type well region, the resistor R is an N-type active area resistor and is arranged in the large P-type well region, two vertical forward ESD paths are formed between the N+ heavily doped active area in the large P-type well region and the bottom of the N-type semiconductor substrate, two horizontal reverse ESD paths are formed between the P+ heavily doped active area in the first TVS structure, the P+ heavily doped active area in the second TVS structure and the N+ heavily doped active area in the large P-type well region, and the two forward ESD paths and the two reverse ESD paths of the large P-type well region form a pair of bidirectional ESD channels.

10. The EMI low-pass filter with integrated electrostatic and surge protection functions according to claim 9, characterized in that: Three large P-type well regions are arranged on the N-type semiconductor substrate, and each of the large P-type well regions has a pair of bidirectional ESD channels.

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