Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and is applied to the technical field of semiconductors. According to the semiconductor device, the dielectric layer is arranged on the embedded word line structure to isolate the embedded word line structure from the corresponding bit line structure, so that the problems of short circuit, electric leakage and the like between the second part of the first work function material layer in the embedded word line structure and the corresponding bit line structure, which are derived along with the miniaturization of the size of the semiconductor device, are solved; therefore, the reliability and the performance of the semiconductor device are improved. Moreover, the newly added first dielectric layer can also be used as an internal component film layer of the bit line structure, such as a gate dielectric layer, so that no extra processing technology needs to be added, and the purposes of simplifying the processing flow and reducing the manufacturing cost are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in an increasing risk of short circuits between some bit line structures and buried word line structures. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to avoid the problems of short circuit, leakage and the like in the bit line structure and the buried word line structure derived from the miniaturization of the semiconductor device size, thereby improving the reliability and performance of the semiconductor device.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a semiconductor device, comprising:

[0005] a substrate comprising a first region and a second region;

[0006] a plurality of active structures defined by an insulating structure;

[0007] A buried word line structure is arranged in the substrate, spanning the plurality of active structures and the insulating structure and extending in a horizontal direction, and the buried word line structure comprises:

[0008] The first work function material layer comprises:

[0009] A first portion, located on the first region;

[0010] a second portion located on the second region, wherein in a vertical direction, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than an upper surface of the active structure; and

[0011] A plurality of word line conductive plugs are in direct contact with the second portion of the first work function material layer.

[0012] In some optional examples, the insulating structure may include:

[0013] A first insulating structure, located on the first region of the substrate;

[0014] The second insulating structure is located on the second region of the substrate, and the width of the second insulating structure in the horizontal direction is greater than the width of the first insulating structure in the horizontal direction.

[0015] In some optional examples, the active structure may include:

[0016] A first active structure, disposed between adjacent first insulating structures;

[0017] The second active structure is disposed between the adjacent first insulating structure and the second insulating structure, and the width of the second active structure in the horizontal direction is greater than the width of the first active structure in the horizontal direction.

[0018] In some optional examples, the junction between the first portion and the second portion of the first work function material layer may be located on the second active structure, and the upper surface of the first work function material layer at the junction may be in a gradually descending step shape in the horizontal direction from the second active structure to the first insulating structure.

[0019] In some optional examples, the buried word line structure may further include: a second work function material layer located above the first portion of the first work function material layer.

[0020] In some optional examples, the sidewall of the second work function material layer may be located above the junction of the first portion and the second portion of the first work function material layer, and the upper surface profile of the second work function material layer may be an arc shape that is concave toward the bottom surface of the first insulating structure.

[0021] In some optional examples, an upper surface of the second work function material layer located above the junction of the first portion and the second portion of the first work function material layer may be in a gradually decreasing slope in the horizontal direction from the second active structure to the first insulating structure.

[0022] In some optional examples, an upper surface of the second work function material layer located at the junction of the first portion and the second portion of the first work function material layer may be in a gradually descending step shape in the horizontal direction from the second active structure to the first insulating structure.

[0023] In some optional examples, the semiconductor device may further include:

[0024] a covering layer, located above the second work function material layer;

[0025] The dielectric layer spans across the plurality of active structures and the plurality of insulating structures and is disposed above the cover layer and the second portion of the first work function material layer in a horizontal direction.

[0026] In a second aspect, based on the same inventive concept, the present invention further provides a semiconductor device, comprising:

[0027] a substrate including a plurality of active structures defined by a plurality of insulating structures;

[0028] A word line trench is located in the substrate;

[0029] A buried word line structure, comprising:

[0030] The buried portion is located in the word line trench and has an upper surface not higher than an upper surface of the active structure;

[0031] a protruding portion, located above the buried portion, wherein in a vertical direction, an upper surface of the protruding portion is higher than upper surfaces of all the active structures;

[0032] A plurality of word line conductive plugs are in direct contact with the upper surface of the protruding portion.

[0033] In a second aspect, based on the same inventive concept, a method for preparing a semiconductor device comprises:

[0034] a substrate comprising a first region and a second region;

[0035] a plurality of active structures defined by an insulating structure;

[0036] A buried word line structure is arranged in the substrate, spanning the plurality of active structures and the insulating structure and extending in a horizontal direction, and the buried word line structure comprises:

[0037] The first work function material layer comprises:

[0038] A first portion, located on the first region;

[0039] a second portion located on the second region, wherein in a vertical direction, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than an upper surface of the active structure; and

[0040] A plurality of word line conductive plugs are in direct contact with the second portion of the first work function material layer.

[0041] In some optional examples, the buried word line structure may further include:

[0042] The second work function material layer is located above the first portion of the first work function material layer.

[0043] In some optional examples, the step of forming the buried word line structure may include:

[0044] Forming a plurality of word line grooves extending in a horizontal direction in the first area and the second area of ​​the substrate respectively;

[0045] forming a first work function material layer in the word line trench;

[0046] removing a portion of the height of the first work function material layer located in the first region of the substrate;

[0047] A second work function material layer is formed on the first portion of the first work function material layer remaining in the first region of the substrate.

[0048] In some optional examples, the insulating structure may include:

[0049] A first insulating structure, located on the first region of the substrate;

[0050] The second insulating structure is located on the second region of the substrate, and the width of the second insulating structure in the horizontal direction is greater than the width of the first insulating structure in the horizontal direction.

[0051] In some optional examples, the sidewall of the second work function material layer may be located above the junction of the first portion and the second portion of the first work function material layer, and the upper surface profile of the second work function material layer may be an arc shape that is concave toward the bottom surface of the first insulating structure.

[0052] In some optional examples, the upper surface of the second work function material layer located at the junction of the first part and the second part of the first work function material layer may be in a gradually descending step shape in the horizontal direction from the second insulating structure to the first insulating structure.

[0053] In some optional examples, the method for preparing the semiconductor device may further include:

[0054] forming a capping layer on the second work function material layer;

[0055] A dielectric layer is formed on the cover layer, and the dielectric layer also crosses the multiple active structures and the multiple insulating structures and is arranged above the second portion of the first work function material layer in a horizontal direction.

[0056] In the present invention, a dielectric layer is provided on the buried word line structure to isolate the buried word line structure from the corresponding bit line structure, thereby avoiding the problems of short circuit and leakage between the second part of the first work function material layer in the buried word line structure and the corresponding bit line structure derived from the miniaturization of the semiconductor device size, thereby achieving the purpose of improving the reliability and performance of the semiconductor device. In addition, the newly added dielectric layer can also be used as an internal component film layer of the bit line structure, such as a gate dielectric layer, so there is no need to add additional process technology, thereby achieving the purpose of simplifying the process flow and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0058] Figure 1 FIG. 4 is a top view of a semiconductor device provided in one embodiment of the present invention.

[0059] Figure 2 to Figure 23 It is a structural schematic diagram of the preparation method provided in one embodiment of the present invention during the preparation process.

[0060] Wherein, the accompanying drawings are marked as follows:

[0061] 100-substrate, 1-first region, 2-second region, AA / BB / CC-tangent direction, STI1-first insulation structure, STI2-second insulation structure, ACT1-first active structure, ACT2-second active structure, R-word line trench, WL-buried word line structure, 110-insulating layer, 111-mask layer, 120 / 120' / 120"-first work function material layer, 120".1-first part of the first work function material layer, 120".2- The second part of the first work function material layer, INT1-the junction between the first part 120".1 of the first work function material layer and the second part 120".1 thereof, 130-photoresist layer, 140 / 140'-second work function material layer, 150 / 150'-covering layer, 160 / 160'-dielectric layer, 170-gate layer, BL-bit line structure, 180-first isolation layer, 190-second isolation layer, WCT-word line conductive plug, BCT-bit line conductive plug.

[0062] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0063] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.

[0064] Please refer to Figure 1 and Fig. 22 , Figure 1 is a schematic top view of a semiconductor device in some embodiments, Fig. 22 The semiconductor device in the first embodiment of the present invention is Figure 1 The local cross-sectional diagram in the AA, BB and CC directions is shown in FIG. Figure 1 and Fig. 22 As shown, the semiconductor device may include a substrate 100 , a plurality of insulating structures, a plurality of active structures, a plurality of buried word line structures WL, and a plurality of word line conductive plugs WCT.

[0065] In one embodiment, a first region 1 and a second region 2 are defined on the substrate 100. The first region 1 may also be referred to as an array region, where a memory cell is disposed, wherein the memory cell is, for example, a dynamic random access memory cell; the second region 2 may also be referred to as a peripheral region, where a buried word line structure WL and a bit line structure for controlling the operation of the memory cell are electrically connected to a peripheral circuit, and the second region 2 is, for example, disposed adjacent to the first region 1, but is not limited thereto. A plurality of insulating structures may be provided on the substrate 100, and the insulating structures define a plurality of active structures on the first region 1 of the substrate 100 and isolate adjacent active structures, that is, the plurality of insulating structures and the plurality of active structures are arranged on the substrate 100 in an adjacent arrangement; and the plurality of insulating structures may be specifically divided into a first insulating structure STI1 located on the first region 1 and a second insulating structure STI2 located on the second region 2 according to their width differences in a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction), and the width of the second insulating structure STI2 in the horizontal direction is greater than the width of the first insulating structure STI1 in the horizontal direction, and the widths of different first insulating structures STI1 or different second insulating structures STI2 in the horizontal direction may also be different, but are not limited thereto. Similarly, the plurality of active structures may also be specifically divided into a first active structure ACT1 located on the first region 1 and a second active structure ACT2 located approximately at the boundary region between the first region 1 and the second region 2 according to their width differences in the horizontal direction, and the width of the second active structure ACT2 in the horizontal direction is greater than the width of the first active structure ACT1 in the horizontal direction, but not limited thereto. Specifically, the first active structure ACT1 may be disposed between adjacent first insulating structures STI1, and the second active structure ACT2 may be disposed between adjacent first insulating structures STI1 and second insulating structures STI2, but not limited thereto.

[0066] In one embodiment, the semiconductor device may further include an insulating layer 110, and the insulating layer 110 is located on the surface of the insulating structure and the active structure; the buried word line structure WL may span across the multiple first active structures ACT1, the multiple second active structures ACT2, the multiple first insulating structures STI1 and the multiple second insulating structures STI2 in a horizontal direction and be arranged in a word line groove in the substrate 100 to bury the multiple active structures and the multiple insulating structures. In detail, the buried word line structure WL is located on the insulating layer 110 in the word line groove, and may include a first work function material layer 120", a second work function material layer 140' and a covering layer 150' which are sequentially stacked in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction).

[0067] Specifically, the first work function material layer 120" can be specifically divided into a first portion 120".1 and a second portion 120".2 along the horizontal direction, the first portion 120".1 of the first work function material layer 120" is located on at least a portion of the surface of the second active structure ACT2 and on the first insulating structure STI1 and the first active structure ACT1, the second portion 120".2 of the first work function material layer 120" is located on the remaining portion of the surface of the second active structure ACT2 and on a portion of the surface of the second insulating structure STI2, And in the vertical direction, the upper surface of the second part 120".2 of the first work function material layer 120" may be higher than the upper surfaces of all the first active structures ACT1 and the second active structures ACT2, and the upper surface of the first part 120".1 of the first work function material layer 120" may be lower than the upper surface of the first active structure ACT1. The second work function material layer 140' is located above the first part 120".1 of the first work function material layer 120", and the covering layer 150' is located above the second work function material layer 140'.

[0068] In the present embodiment, the junction INT1 between the first part 120".1 and the second part 120".2 of the first work function material layer 120" may be located on the second active structure ACT2, and the upper surface of the first work function material layer 120" located at the junction INT1 is in the shape of a gradually descending step in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, and the side wall of the second work function material layer 140' is located above the junction INT1 between the first part 120".1 and the second part 120".2 of the first work function material layer 120", and the upper surface profile of the second work function material layer 140' may be an irregular shape that is recessed toward the bottom surface of the first insulating structure STI1, for example, in the shape of a gradually descending step in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, such as Fig. 22The L-shaped profile shown, but not limited to this. Under this arrangement, the highest end of the upper surface of the second work function material layer 140' is at the same horizontal height as the upper surface of the second part 120".2 of the first work function material layer 120", and there is a height difference between the highest end of its upper surface and the lowest end of the upper surface, which is the side wall height of the second work function material layer 140', and the top surface of the covering layer 150' is lower than the highest end of the upper surface of the second work function material layer 140', that is, the covering layer 150' only covers part of the side wall of the second work function material layer 140'. Under this arrangement, the buried word line structure WL as a whole may include a buried portion arranged in upper and lower parts, which is located in the word line groove and whose upper surface is not higher than the upper surface of the first active structure ACT1, and a protruding portion located above the buried portion and whose upper surface is higher than the upper surfaces of the first active structure ACT1 and the second active structure ACT2, such as Fig. 22 In the area framed by the black dotted line, the buried word line structure WL of the present application has a protruding portion, which is higher than the upper surface of the active structure. Compared with the buried portion, the surface of the protruding portion is closer to the top of the bit line structure BL in the vertical direction, that is, the difference between the protruding portion and the top of the bit line structure in the vertical direction is reduced, which is beneficial to the subsequent formation of the word line conductive plug WCT / bit line conductive plug BCT.

[0069] In one embodiment, the semiconductor device further comprises a plurality of bit line structures BL, a first isolation layer 180, a second isolation layer 190 and a bit line conductive plug BCT arranged on the substrate 100, wherein the bit line structures BL extend in a direction perpendicular to the extending direction of the buried word line structures WL and are arranged in a spaced relationship in the middle region of the first active structure ACT1 or the second active structure ACT2 to control the source of the transistor of the memory cell. The first isolation layer 180 is wrapped around the outer surface of the bit line structure BL and extends to cover the exposed cover layer 150', the second work function material layer 140', the second portion 120'.2 of the first work function material layer 120'' and the second isolation structure STI2. The second isolation layer 190 is fully covered on the substrate 100. The word line conductive plug WCT is located on the buried word line structure WL and directly contacts the second portion 120 ″.2 (i.e., the protruding portion) of the first work function material layer 120 ″ thereunder through the second isolation layer 190 and the first isolation layer 180. The bit line conductive plug BCT is located on the bit line structure BL. Specifically, the bit line structure BL may include a dielectric layer 160 ′ and a gate layer 170 stacked in sequence along a vertical direction. The material of the dielectric layer 160 ′ may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. The material of the gate layer 170 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and / or composite layer of the above metal materials, but not limited thereto. Furthermore, the dielectric layer 160 ′ may be a single layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but is not limited thereto.

[0070] Since in the embodiment of the present invention, after forming the cover layer 150' of the buried word line structure WL, a dielectric material, such as silicon dioxide or silicon nitride, and a gate material, such as tungsten (W) are formed on the substrate 100 to fully cover the active structure and the isolation structure, and then a portion of the dielectric material and the gate material are etched away in the vertical direction to form a plurality of bit line structures BL spaced apart from each other, wherein the added dielectric material serves as both the gate dielectric layer of the bit line structure BL and the isolation layer between the bit line structure BL and the second portion 120".2 of the first work function material layer 120" in the buried word line structure WL, the preparation method provided in the embodiment of the present invention can achieve the purpose of isolating the buried word line structure and the corresponding bit line structure without adding any additional process technology, while achieving the purpose of simplifying the process flow and reducing the manufacturing cost.

[0071] In some embodiments, the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto; the materials of the first insulating structure STI1 and the second insulating structure STI2 may include a single layer or multiple layers of insulating materials such as oxide insulating materials, nitride insulating materials or other suitable insulating materials, but not limited thereto; the material of the first work function material layer 120" in the buried word line structure WL may include a single layer or multiple layers of conductive materials, such as titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten nitride, tungsten carbide, titanium aluminide, aluminum nitride, titanium, tungsten, aluminum, copper, titanium, tantalum or other suitable metal conductive materials or non-metal conductive materials, but not limited thereto; the material of the second work function material layer 140' The material may include doped polysilicon, undoped polysilicon or other materials different from the conductive layer, but not limited thereto; the materials of the cover layer 150', the first isolation layer 180 and the second isolation layer 190 may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), or a combination of the above materials, but not limited thereto; the materials of the word line conductive plug WCT and the bit line conductive plug BCT may be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but not limited thereto.

[0072] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present invention may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present invention will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0073] Please refer to Fig.23 As shown, combined with Figure 1 ,in Fig.23: is a cross-sectional schematic diagram of a semiconductor device in a second embodiment of the present invention. The structure of the semiconductor device in this embodiment is substantially the same as that of the semiconductor device in the aforementioned first embodiment, such as the semiconductor device also includes a plurality of first active structures ACT1, a plurality of second active structures ACT2, a plurality of first isolation structures STI1, a plurality of second isolation structures STI2, a plurality of buried word line structures WL, and a plurality of word line conductive plugs WCT, and the same parts are not repeated here. The main difference between the semiconductor device in this embodiment and the aforementioned first embodiment is that the upper surface profile of the second work function material layer 140' in the buried word line structure WL is an arc shape that is concave toward the bottom surface of the first insulating structure STI1, for example, it is a slope shape that gradually decreases in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, but it is not limited to this. Under this setting, it is also possible to avoid the second part 120'.2 of the first work function material layer 120' in the buried word line structure WL and the corresponding bit line structure BL from short circuit and leakage caused by the miniaturization of the size of the semiconductor device.

[0074] It should be noted that, in order to simplify the drawing, the upper surface profile of the second portion 120 ″.2 of the first work function material layer 120 ″ in the above-mentioned embodiment 1 and embodiment 2 may be as follows: Fig. 22 or Fig.23 In order to meet the actual semiconductor process results, the upper surface profile of the second portion 120 ″.2 of the first work function material layer 120 ″ may also be as follows: Figure 6 The uneven curved arc surface structure shown is not limited thereto.

[0075] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for manufacturing a semiconductor device in an embodiment of the present invention, the method for manufacturing a semiconductor device proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the manufacturing method during the preparation process.

[0076] Please refer to Figure 2 to Figure 23 , which is a structural schematic diagram of a semiconductor device manufacturing method provided in an embodiment of the present invention during the preparation process.

[0077] like Figure 2 and Figure 3As shown, a substrate 100 is first provided, and a plurality of grooves are formed in the substrate 100 by an etching process, and an insulating material (such as silicon oxide, silicon nitride, etc.) is filled in the plurality of grooves by a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, so as to form a plurality of first isolation structures STI1 on the first region 1 of the substrate 100, and a plurality of second isolation structures STI2 are formed on the second region 2 of the substrate 100, and a first active structure ACT1 is defined on the substrate 100 between adjacent first insulation structures STI1, and a second active structure ACT2 is defined on the substrate 100 between adjacent first insulation structures STI1 and second insulation structures STI2. In one embodiment, the width of the second insulation structure STI2 in the horizontal direction is greater than the width of the first insulation structure STI1 in the horizontal direction, and the width of the second active structure ACT2 in the horizontal direction is greater than the width of the first active structure ACT1 in the horizontal direction, but the present invention is not limited thereto.

[0078] Then, an etching process, such as at least one of a dry etching process and a wet etching process, is used to form a plurality of word line trenches R extending in the horizontal direction in the substrate 100 corresponding to the first area 1 and the second area 2, respectively. Then, a mask layer 111 (such as silicon nitride) is formed on the active structure and the isolation structure by using at least one of the deposition processes, and an insulating layer 110 (such as oxide), a first work function material layer 120 (such as metal tungsten) and a patterned photoresist layer 130 are sequentially formed in the word line trenches R. In one embodiment, the insulating layer 110 and the first work function material layer 120 also extend on the top surface of the second insulating structure STI2 and the substrate 100 outside the word line trenches R, and the patterned photoresist layer 130 exposes the top surface of the first work function material layer 120 on the first active structure ACT1, the first insulating structure STI1 and part of the second active structure ACT2, so as to prepare for the subsequent etching process.

[0079] like Figure 4 and Figure 5 As shown, two etching processes are then continuously performed to remove part of the first work function material layer 120 along the vertical direction, and the top surface of the first work function material layer 120 remaining in the word line trench R in the first area 1 is lower than the top surface of the active structure, while the top surface of the first work function material layer 120 remaining in the word line trench R in the second area 2 is higher than the top surface of the active structure. Specifically, the first work function material layer 120 can be etched and removed for the first time using the patterned photoresist layer 130 as a mask to form Figure 4In the structure shown in FIG. 1 , at this time, since the top surface of the first work function material layer 120 located in the second area 2 is covered with a patterned photoresist layer 130, its height remains unchanged after this etching, and the first work function material layer 120 located in the first area 1 removes part of its height in the vertical direction, that is, after the first etching, the top surface of the remaining first work function material layer on the first area 1 can be at the same horizontal height as the top surface of the mask layer 111, while the top surface of the remaining first work function material layer on the second area 2 is higher than the top surface of the insulating layer 110 (that is, higher than the first work function material layer remaining on the first area 2). The top surface of the material layer); illustratively, in the embodiment of the present invention, the first work function material layer remaining after the first etching is marked with the reference numeral 120', wherein the portion of the first work function material layer 120' located on the first area 1 is marked with the reference numeral 120'.1, and the portion on the second area 2 is marked with the reference numeral 120'.2, and the junction between the two is marked with the reference numeral INT1; then the patterned photoresist layer 130 is removed, and the first work function material layer 120' is further etched and removed for the second time along the vertical direction by an etching process, so as to form a Figure 5 The structure shown, that is, after the second etching, the top surface of the remaining first work function material layer on the first area 1 is lower than the top surface of the substrate 100 (i.e., the active structure), and the top surface of the remaining first work function material layer on the second area 2 is at the same horizontal height as the top surface of the mask layer 111; obviously, the second etching deepens the height difference between the remaining first work function material layer on the first area 1 and the second area 2 in the vertical direction; illustratively, in the embodiment of the present invention, the first work function material layer remaining after the second etching is marked with the figure mark 120", wherein the part of the first work function material layer 120" located on the first area 1 is marked with the figure mark 120".1 (hereinafter referred to as the first part 120".1), and the part on the second area 2 is marked with the figure mark 120".2 (hereinafter referred to as the second part 120".2), and the junction between the two is also marked with the figure mark INT1.

[0080] It should be noted that, in order to simplify the drawing, the upper surface profile of the second portion 120 ″.2 of the first work function material layer 120 ″ may be as follows: Figure 5 In order to meet the actual semiconductor process results, the upper surface profile of the second portion 120 ″.2 of the first work function material layer 120 ″ may also be as follows: Figure 6 The uneven curved arc surface structure shown in Figure 6 In addition, in order to further simplify the drawing, the black dotted line in the embodiment of the present invention is used as the frame area. Figure 7 to Figure 23 All in Figure 5The upper surface profile of the second portion 120 ″.2 of the first work function material layer 120 ″ is shown as a planar structure as a basis for subsequent related process technologies.

[0081] like Figure 7 to Figure 9 As shown, a deposition process may then be used to form a second work function material layer 140 (e.g., polysilicon) on the substrate 100 that fully covers the first portion 120 ″.1 and the second portion 120 ″.2 of the first work function material layer 120 ″. Subsequently, an etching process is further used to remove a portion of the height of the second work function material layer 140 in the vertical direction to form a second work function material layer 140 as shown in FIG. Figure 8 The structure shown in FIG. 1 is shown in FIG. 1 , and the second work function material layer 140 remaining after etching is exemplarily identified by reference numeral 140 ′. Figure 8 As shown, the sidewall and bottom of the second work function material layer 140' may have an L-shaped profile, that is, the upper surface profile of the second work function material layer 140' may be a step-shaped profile that gradually decreases in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, and the sidewall of the second work function material layer 140' is located above the junction INT1 of the first part 120".1 and the second part 120".2 of the first work function material layer 120", but not limited to this. In another embodiment, as Fig. 9 As shown, the sidewalls and bottom of the second work function material layer 140' have an arc-shaped profile, that is, the upper surface profile of the second work function material layer 140' can be a gradually decreasing slope in the horizontal direction from the second active structure ACT2 to the first insulating structure STI1, and the sidewalls of the second work function material layer 140' can also be located above the junction INT1 of the first part 120".1 and the second part 120".2 of the first work function material layer 120", but not limited to this.

[0082] It should be understood that Figures 10 to 23 Based on Figure 8 or Fig. 9 The structure shown is a corresponding structure obtained by performing the same subsequent process technology. Therefore, in order to simplify the description, the following embodiments of the present invention are introduced in a manner of unified description of two drawings corresponding to the same process technology.

[0083] like Fig.10 or Fig.11 As shown, a deposition process is then used to form a covering layer 150 (e.g., silicon oxynitride) on the substrate 100 to fully cover the first work function material layer 120" on the active structure and the insulating structure. The covering layer 150 fills the first insulating structure STI1 in the vertical direction at a portion located on the first region 1 and is in direct contact with the second work function material layer 140' located therein.

[0084] like Fig.12 or Fig.13 As shown, an etching process is then used to remove part of the height of the cover layer 150 in the vertical direction, so that the remaining cover layer 150' is only located on the first region 1, and its top surface is flush with the surface of the substrate 100 (ie, the top surface of the first active structure ACT1).

[0085] like Fig.14 or Fig.15 As shown, the insulating layer 110 and the mask layer 111 on the substrate 100 are then removed by an etching process to expose the surface of the substrate 100 on both sides of the adjacent word line trenches R in the first region 1, and the surface of the second insulating structure STI2 on both sides of the adjacent word line trenches R in the second region 2. At this time, the top surface of the second portion 120".2 of the first work function material layer of the word line trench R in the second region 2 is higher than the surface of the substrate 100.

[0086] like Fig.16 or Fig.17 As shown, a deposition process is then used to form a dielectric layer 160 on the substrate 100 to fully cover the second part 120".2 of the first work function material layer 120" and the covering layer 150' on the active structure and the insulating structure, wherein the dielectric layer 160 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but not limited thereto; at this time, the portion of the dielectric layer 160 located on the second area 1 wraps the top surface and side walls of the second part 120".2 of the first work function material layer 120" exposed on the second area 2. Obviously, in the embodiment of the present invention, after forming the covering layer 150' of the buried word line structure WL and before forming the bit line structure BL, the dielectric layer 160 is first formed, so as to isolate the second part 120".2 of the first work function material layer 120" in the buried word line structure WL from the corresponding bit line structure BL through the added dielectric layer 160, thereby avoiding the problems of short circuit, leakage, etc. between the second part 120".2 of the first work function material layer 120" in the buried word line structure and the corresponding bit line structure BL derived from the miniaturization of the size of the semiconductor device.

[0087] like Fig.18 or Fig.19As shown, a gate material layer (not shown) may be further formed on the dielectric layer 160, and a portion of the gate material layer and the dielectric layer 160 may be further removed by an etching process to form a plurality of bit line structures BL consisting of the gate layer 170 formed after etching and the remaining dielectric layer 160', and the bit line structures BL extend in a direction perpendicular to the extending direction of the buried word line structure WL, and are arranged in a spaced relationship in the middle region of the first active structure ACT1 or the second active structure ACT2; in other embodiments, the dielectric layer 160 on the top and side of the second portion 120".2 may be retained. In one embodiment, the gate material layer The material may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. Obviously, in the embodiment of the present invention, the dielectric layer 160' not only serves as an isolation layer between the bit line structure BL and the second portion 120".2 of the first work function material layer 120" in the buried word line structure WL, but also serves as a gate dielectric layer of the bit line structure BL. Therefore, the preparation method provided in the embodiment of the present invention can achieve the purpose of isolating the buried word line structure and the corresponding bit line structure without adding additional process technology, while achieving the purpose of simplifying the process flow and reducing the manufacturing cost.

[0088] like Fig. 20 or Fig.21 As shown, a first isolation layer 180 (for example, silicon nitride) is then formed on the substrate 100, and the first isolation layer 180 covers the outer surface of the bit line structure BL, and extends to cover the top surface of the cover layer 150' and the second part 120".2 of the first work function material layer 120" in the buried word line structure WL; at this time, the first isolation layer 180 wraps the top surface and side wall of the second part 120".2 of the first work function material layer 120" exposed on the second region 2. In other embodiments, the first isolation layer 180 may cover the surface of the dielectric layer 160, and the dielectric layer 160 covers the top and side surfaces of the second part 120".2.

[0089] like Fig. 22 or Fig.23As shown, a second isolation layer 190 (e.g., silicon oxide or silicon nitride) is then formed on the substrate 100 to bury the corresponding semiconductor components (e.g., the bit line structure BL) on the first region 1 and the second region 2, and a plurality of word line conductive plugs WCT are formed through the second isolation layer 190 and the first isolation layer 180 to directly contact the second portion 120".2 of the first work function material layer 120" thereunder, and a plurality of bit line conductive plugs BCT are formed through the second isolation layer 190 and the first isolation layer 180 to directly contact the gate layer 170 in the bit line structure. In one embodiment, the materials of the word line conductive plugs WCT and the bit line conductive plugs BCT can be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but are not limited thereto.

[0090] In summary, in the present invention, a dielectric layer is provided on the buried word line structure to isolate the buried word line structure from the corresponding bit line structure, thereby avoiding the problems of short circuit and leakage between the second part of the first work function material layer in the buried word line structure and the corresponding bit line structure derived from the miniaturization of the semiconductor device size, thereby achieving the purpose of improving the reliability and performance of the semiconductor device. In addition, the newly added dielectric layer can also be used as an internal component film layer of the bit line structure, such as a gate dielectric layer, so there is no need to add additional process technology, thereby achieving the purpose of simplifying the process flow and reducing manufacturing costs.

[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0092] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a first region and a second region; a plurality of active structures defined by an insulating structure; A buried word line structure is arranged in the substrate, spanning the plurality of active structures and the insulating structure and extending in a horizontal direction, and the buried word line structure comprises: The first work function material layer comprises: A first portion, located on the first region; a second portion located on the second region, wherein in a vertical direction, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than an upper surface of the active structure; and A plurality of word line conductive plugs are in direct contact with the second portion of the first work function material layer.

2. The semiconductor device according to claim 1, wherein The insulating structure comprises: A first insulating structure, located on the first region of the substrate; The second insulating structure is located on the second region of the substrate, and the width of the second insulating structure in the horizontal direction is greater than the width of the first insulating structure in the horizontal direction.

3. The semiconductor device according to claim 2, wherein: The active structure comprises: A first active structure, disposed between adjacent first insulating structures; The second active structure is disposed between the adjacent first insulating structure and the second insulating structure, and the width of the second active structure in the horizontal direction is greater than the width of the first active structure in the horizontal direction.

4. The semiconductor device according to claim 3, characterized in that The junction between the first part and the second part of the first work function material layer is located on the second active structure, and the upper surface of the first work function material layer at the junction is in a gradually descending step shape in the horizontal direction from the second active structure to the first insulating structure.

5. The semiconductor device according to claim 3, wherein: The buried word line structure further includes: a second work function material layer located above the first portion of the first work function material layer.

6. The semiconductor device according to claim 5, characterized in that The sidewall of the second work function material layer is located above the junction of the first part and the second part of the first work function material layer, and the upper surface profile of the second work function material layer is an arc shape that is concave toward the bottom surface of the first insulation structure.

7. The semiconductor device according to claim 6, wherein: An upper surface of the second work function material layer located above the junction between the first portion and the second portion of the first work function material layer is in a gradually decreasing slope in a horizontal direction from the second active structure to the first insulating structure.

8. The semiconductor device according to claim 5, wherein: An upper surface of the second work function material layer located at the junction of the first portion and the second portion of the first work function material layer is in a step-like shape that gradually descends in a horizontal direction from the second active structure to the first insulating structure.

9. The semiconductor device according to claim 5, characterized in that Also includes: a covering layer, located above the second work function material layer; The dielectric layer spans across the plurality of active structures and the plurality of insulating structures and is disposed above the cover layer and the second portion of the first work function material layer in a horizontal direction.

10. A semiconductor device, characterized in that: include: a substrate including a plurality of active structures defined by a plurality of insulating structures; A word line trench is located in the substrate; A buried word line structure, comprising: The buried portion is located in the word line trench and has an upper surface not higher than an upper surface of the active structure; a protruding portion, located above the buried portion, wherein in a vertical direction, an upper surface of the protruding portion is higher than upper surfaces of all the active structures; A plurality of word line conductive plugs are in direct contact with the upper surface of the protruding portion.

11. A method for preparing a semiconductor device, characterized in that: include: a substrate comprising a first region and a second region; a plurality of active structures defined by an insulating structure; A buried word line structure is arranged in the substrate, spanning the plurality of active structures and the insulating structure and extending in a horizontal direction, and the buried word line structure comprises: The first work function material layer comprises: A first portion, located on the first region; a second portion located on the second region, wherein in a vertical direction, an upper surface of the second portion is higher than an upper surface of the active structure, and an upper surface of the first portion is lower than an upper surface of the active structure; and A plurality of word line conductive plugs are in direct contact with the second portion of the first work function material layer.

12. The method for preparing a semiconductor device according to claim 11, wherein: The buried word line structure further comprises: The second work function material layer is located above the first portion of the first work function material layer.

13. The method for preparing a semiconductor device according to claim 12, wherein: The steps of forming the buried word line structure include: Forming a plurality of word line grooves extending in a horizontal direction in the first area and the second area of ​​the substrate respectively; forming a first work function material layer in the word line trench; removing a portion of the height of the first work function material layer located in the first region of the substrate; A second work function material layer is formed on the first portion of the first work function material layer remaining in the first region of the substrate.

14. The method for preparing a semiconductor device according to claim 13, wherein: The insulating structure comprises: A first insulating structure, located on the first region of the substrate; The second insulating structure is located on the second region of the substrate, and the width of the second insulating structure in the horizontal direction is greater than the width of the first insulating structure in the horizontal direction.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The sidewall of the second work function material layer is located above the junction of the first part and the second part of the first work function material layer, and the upper surface profile of the second work function material layer is an arc shape that is concave toward the bottom surface of the first insulation structure.

16. The method for preparing a semiconductor device according to claim 14, wherein: An upper surface of the second work function material layer located at the junction of the first portion and the second portion of the first work function material layer is in a step shape that gradually decreases in a horizontal direction from the second insulating structure to the first insulating structure.

17. The method for preparing a semiconductor device according to claim 13, wherein: Also includes: forming a capping layer on the second work function material layer; A dielectric layer is formed on the cover layer, and the dielectric layer also crosses the multiple active structures and the multiple insulating structures and is arranged above the second portion of the first work function material layer in a horizontal direction.

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