GPGPU and host data transmission method and device, and medium

Abstract

The invention discloses a data transmission method and device for a GPGPU and a host and a medium, and the method comprises the steps: obtaining a first transmission attribute corresponding to DMA transmission at this time through a running program at a host side; if the number of channels is a specified number representing automatic setting, determining the number of actual channels used at this time according to the data length of the first transmission attribute and the task emergency degree of DMA transmission at this time; through a DMA-CTRL controller, corresponding channels are selected based on the actual channel number, and second transmission attributes corresponding to the channels are obtained; and controlling the DMA controller through the DMA-CTRL controller, executing the DMA transmission based on the second transmission attribute, and feeding back a transmission result to the DMA-CTRL controller through the DMA controller. The DMA-CTRL controller is added in the GPGPU, and the DMA controllers and the PCIe-D controllers are controlled to perform data transmission at the same time, so that the data transmission speed between the GPGPU and the host can be effectively increased, the overall task execution time is shortened, and the influence of the PCIe interface on the overall calculation performance is improved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a method, device and medium for data transmission between a GPGPU and a host. Background Art

[0002] With the development of high-performance computing, the performance of general-purpose graphics processing units (GPGPUs) has been continuously improved. At present, mainstream GPGPUs have reached a relatively high level in terms of hardware parameters such as the number of cores and clock speed, memory capacity and bandwidth. For example, the memory bandwidth of some GPGPU models has reached 4.8TB per second.

[0003] Due to the advantages of PCIe (Peripheral Component Interface Express) interface in compatibility, size, cost, etc., PCIe interface is still the most widely used GPGPU interface. However, the transmission bandwidth of PCIe is much lower than the internal bandwidth of GPGPU. Taking PCIe5.0 interface as an example, its transmission bandwidth is only 128GB per second, and the transmission bandwidth of PCIe4.0 interface is only 64GB per second, which limits the computing power of high-performance GPGPU. Summary of the invention

[0004] In order to solve the above problems, the present application proposes a data transmission method between a GPGPU and a host, which is applied in a data transmission system, wherein the data transmission system includes a host side and a device side, wherein the host side includes a CPU module and multiple PCIe-H controllers, and the device side includes a GPGPU module, wherein the GPGPU module includes a DMA-CTRL controller, multiple DMA controllers, and multiple PCIe-D controllers; wherein the PCIe-H controller, the DMA controller, and the PCIe-D controller correspond to each other, and the DMA-CTRL controller is used to control the DMA controller and the PCIe-D controller;

[0005] The method comprises:

[0006] Obtaining, by running a program on the host side, a first transmission attribute corresponding to the current DMA transmission, wherein the first transmission attribute includes the number of channels, a source address, a destination address, and a data length of the DMA transmission;

[0007] If the number of channels is a designated number indicating automatic setting, then determining the actual number of channels used this time according to the data length of the first transfer attribute and the urgency of the task of this DMA transfer;

[0008] By means of the DMA-CTRL controller, a corresponding channel is selected based on the actual number of channels, and a second transmission attribute corresponding to each channel is obtained according to the first transmission attribute, wherein the second transmission attribute includes a source address, a destination address, and a data length;

[0009] The DMA controller is controlled by the DMA-CTRL controller to perform the current DMA transfer based on the second transfer attribute, and the transfer result is fed back to the DMA-CTRL controller by the DMA controller.

[0010] In one example, a memory module is further provided on the host side, and a video memory module is further provided on the device side;

[0011] Obtaining the first transmission attribute corresponding to the current DMA transmission through the running program on the host side, specifically including:

[0012] Determine the data sender and the data receiver in this DMA transmission by running the program on the host side;

[0013] If the data sender is the host side and the data receiver is the device side, the source address and the destination address in the first transmission attribute are obtained based on the memory module and the video memory module respectively;

[0014] If the data sender is the device side and the data receiver is the host side, the source address and the destination address in the first transmission attribute are obtained based on the video memory module and the memory module respectively.

[0015] In one example, each of the PCIe-D controllers and each of the DMA controllers are multi-channel; each channel of the DMA controller corresponds to each channel of the PCIe-D controller; each channel of the DMA controller and each channel of the PCIe-D controller can be controlled individually.

[0016] In one example, according to the data length of the first transmission attribute and the urgency of the task of this DMA transmission, determining the actual number of channels used this time specifically includes:

[0017] Obtain the maximum data length of a single transfer of each channel of the DMA controller;

[0018] Determine the actual number of channels used this time based on the maximum data length and the data length of the first transmission attribute;

[0019] According to the urgency of the task of this DMA transfer, the actual number of channels is corrected.

[0020] In one example, based on the maximum data length and the data length of the first transmission attribute, determining the actual number of channels used this time specifically includes:

[0021] The data length of the first transmission attribute is divided by the maximum data length, and 1 is added according to the result of the division to obtain the actual number of channels used this time.

[0022] In one example, after obtaining the first transmission attribute corresponding to the current DMA transmission, the method further includes:

[0023] If the number of channels is a set number indicating manual setting, determining whether the set number exceeds an upper limit of the number of channels corresponding to the PCIe-D controller and the DMA controller;

[0024] If it does not exceed, the set number will be used as the actual number of channels used this time.

[0025] In one example, feeding back the transmission result to the DMA-CTRL controller through the DMA controller specifically includes:

[0026] Through the DMA controller, whenever the corresponding channel completes the DMA transmission, the corresponding transmission result is fed back to the DMA-CTRL controller;

[0027] When all channels corresponding to the DMA controller complete DMA transmission, the DMA controller sends a transmission completion interrupt request to the PCIe-H controller corresponding to the host side through the PCIe-D controller corresponding to the DMA controller, so that the PCIe-H controller passes the transmission completion interrupt request to the running program through the device driver.

[0028] In an example, the number of the PCIe-H controller, the number of the DMA controller, and the number of the PCIe-D controller are all three; the number of channels of each of the PCIe-D controller and each of the DMA controller are all sixteen.

[0029] On the other hand, the present application also proposes a data transmission device between a GPGPU and a host, comprising:

[0030] at least one processor; and,

[0031] a memory communicatively connected to the at least one processor; wherein,

[0032] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the data transmission method between the GPGPU and the host as described in any of the above examples.

[0033] On the other hand, the present application also proposes a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to be: the data transmission method between the GPGPU and the host described in any of the above examples.

[0034] The data transmission method between GPGPU and host proposed in this application can bring the following beneficial effects:

[0035] By adding a DMA-CTRL controller to the GPGPU and controlling multiple DMA controllers and multiple PCIe-D controllers to transmit data simultaneously, the data transmission speed between the GPGPU and the host can be effectively improved, the overall task execution time can be reduced, and the impact of the PCIe interface on the overall computing performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0037] Figure 1 Schematic diagram of the flow of the data transmission method between GPGPU and host in the embodiment of the present application;

[0038] Figure 2 This is a structural diagram of a data transmission system in one scenario in an embodiment of the present application;

[0039] Figure 3 This is a schematic diagram of the channel correspondence relationship between the PCIe-D controller and the DMA controller in one scenario in an embodiment of the present application;

[0040] Figure 4 Schematic diagram of data transmission equipment between GPGPU and host in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0042] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0043] like Figure 1As shown, the embodiment of the present application provides a data transmission method between a GPGPU and a host, which is applied in a data transmission system, such as Figure 2 As shown, the data transmission system includes a host side and a device side.

[0044] Specifically, the host side includes a CPU module and multiple PCIe-H controllers, and the device side includes a GPGPU module. The CPU module is a central processing unit (CPU) module, and the PCIe-H controller refers to a controller that implements corresponding control of the PCIe interface (referred to as PCIe-H interface) on the host side.

[0045] The GPGPU module includes a DMA-CTRL controller, multiple DMA controllers, and multiple PCIe-D controllers, which can effectively improve the data transmission speed between the GPGPU and the host, reduce the overall task execution time, and improve the impact of the PCIe interface on the overall computing performance. The PCIe-D controller refers to a controller that implements corresponding control of the PCIe interface on the device side (referred to as the PCIe-D interface). Direct Memory Access (DMA) refers to a data transmission method that allows data transmission between the GPU and the host memory. The DMA controller is a controller used to control DMA implementation. The DMA-CTRL controller refers to the master controller set on the device side, which is used to control the DMA controller and the PCIe-D controller. The DMA-CTRL controller can assign DMA transmission tasks to the corresponding DMA controller channel and PCIe-D channel according to the number of channels set by the running program.

[0046] Furthermore, the PCIe-H controller, the DMA controller, and the PCIe-D controller correspond to each other, including correspondence in quantity and correspondence during data transmission.

[0047] like Figure 1 As shown, the method includes:

[0048] S101: obtaining, through the running program on the host side, a first transmission attribute corresponding to the current DMA transmission, wherein the first transmission attribute includes the number of channels, source address, destination address, and data length of the DMA transmission.

[0049] The running program refers to a program that is currently running on the host side and has a data transmission (ie, DMA transmission) requirement. By initiating the requirement, the DMA transmission is started and the corresponding first transmission attribute is obtained.

[0050] In the first transfer attribute, the number of channels refers to the channels required for this DMA transfer, including the channels of the DMA and PCIe-D interfaces, which are controlled by the DMA controller and PCIe-D controller respectively. The source address and destination address refer to the source address and destination address of this DMA transfer respectively. The data length refers to the total data length of this DMA transfer.

[0051] like Figure 2 As shown, a memory module (e.g., Figure 2 ), and a video memory module is also provided on the device side (for example, Figure 2 The GDDR module shown in the figure). Double Data Rate SDRAM (DDR) is a form of memory, referred to as DDR module. Graphics Double Data Rate SDRAM (GDDR for short) is a form of video memory.

[0052] At this time, when determining the first transmission attribute corresponding to this DMA transmission, the data sender and the data receiver in this DMA transmission can be determined by running a program on the host side.

[0053] When data is sent from the host side to the device side, the data sender is the host side and the data receiver is the device side. The source address and destination address in the first transmission attribute are obtained based on the memory module and the video memory module respectively, that is, the source address is stored in the DDR module and the destination address is stored in the GDDR module.

[0054] When the host side reads data from the device side, the data sender is the device side and the data receiver is the host side. The source address and destination address in the first transmission attribute are obtained based on the video memory module and the memory module respectively, that is, the source address is stored in the GDDR module and the destination address is stored in the DDR module.

[0055] In addition, if Figure 2 As shown in the figure, in a common case, the number of PCIe-H controllers, DMA controllers, and PCIe-D controllers are all three, namely PCIe-H1, PCIe-H2, PCIe-H3, DMA1, DMA2, DMA3, PCIe-D1, PCIe-D2, PCIe-D3. Of course, in actual work, the number can be set based on demand. The DMA controller and PCIe-D controller are connected through the GPGPU internal bus.

[0056] Each PCIe-D controller and each DMA controller are multi-channel, and each channel of the DMA controller corresponds to each channel of the PCIe-D controller; each channel of the DMA controller and each channel of the PCIe-D controller can be controlled individually.

[0057] like Figure 3 As shown, in a common case, the number of channels of each PCIe-D controller and each DMA controller is 16. Taking PCIe-D1 and DMA1 as examples, they include PCIe-D1-CH1 to PCIe-D1-CH16, DMA1-CH1 to DMA1-CH16, and each channel corresponds to each other. Of course, the number of channels of each PCIe-H controller can also be the same as and correspond to the number of channels of the PCIe-D controller and the DMA controller.

[0058] S102: If the number of channels is a designated number that indicates automatic setting, the actual number of channels used this time is determined according to the data length of the first transfer attribute and the urgency of the task of this DMA transfer.

[0059] Before initiating data transmission of the DMA transmission task, the running program sets the DMA-CTRL controller through the driver, including the number of channels, source address, destination address, data length, etc. of the DMA transmission in the first transmission attribute.

[0060] There are two ways to set the number of channels. The first way is to set the number of channels to a specified number that indicates automatic setting, and the other way is to set the number of channels to a set number that indicates manual setting. For example, if the number of channels is set to "0", it is a specified number, indicating that the number of channels this time is automatically determined by the DMA-CTRL controller. If the number of channels is set to a number other than "0", it means that the number of channels this time is specified manually or by running the program.

[0061] Specifically, if the number of channels is a specified number (for example, if it is 0), the number of channels is automatically determined by the DMA-CTRL controller, and the DMA-CTRL controller obtains the maximum data length of a single transfer of each channel of the DMA controller. The maximum data length SIZE-MAX is usually preset or default.

[0062] At this time, based on the maximum data length and the data length of the first transmission attribute, the actual number of channels used this time is determined. For example, the data length of the first transmission attribute is divided by the maximum data length, and 1 is added according to the result of the division to obtain the actual number of channels used this time. In other words, if the data length of this DMA transfer does not exceed SIZE-MAX, 1 idle DMA controller channel and PCIe-D channel are automatically allocated. If the data length of this DMA transfer exceeds SIZE-MAX, but does not exceed 2 times SIZE-MAX, 2 idle DMA controller channels and PCIe-D channels are automatically allocated, and so on.

[0063] Of course, the actual number of channels can also be modified according to the urgency of the task of this DMA transfer. For example, if the urgency of the task is the preset "urgent", then the number of channels corresponding to the urgency of the task will be added to the actual number of channels calculated. Usually, the more urgent the task is, the more channels will be added to ensure that the task is executed quickly and with priority.

[0064] If the number of channels is not a specified number, but a set number (for example, if it is greater than 0), the set number of channels is used as the basis to determine whether the set number exceeds the upper limit of the number of channels corresponding to the PCIe-D controller and the DMA controller.

[0065] If it does not exceed the limit, the set number will be used as the actual number of channels used this time.

[0066] Of course, if it exceeds, the actual number of channels can be calculated automatically.

[0067] S103: Selecting corresponding channels based on the actual number of channels through the DMA-CTRL controller, and obtaining second transmission attributes corresponding to each channel according to the first transmission attributes, wherein the second transmission attributes include a source address, a destination address, and a data length.

[0068] After determining the actual number of channels, the DMA-CTRL controller can evenly distribute the current transfer task to the corresponding number of idle DMA controller channels and PCIe-D channels. The DMA-CTRL controller will calculate the data length, source address, and destination address corresponding to each channel based on the number of channels actually used for this DMA transfer and the data length, source address, and destination address set by the running program, and set the corresponding DMA controller and PCIe-D controller based on the calculation results.

[0069] Among them, the source address and destination address in the second transmission attribute are the same as the source address and destination address in the first transmission attribute, and the data length of the second transmission attribute of each channel is obtained by the DMA-CTRL controller by averaging and splitting the data length in the first transmission attribute.

[0070] S104: controlling the DMA controller through the DMA-CTRL controller to perform this DMA transfer based on the second transfer attribute, and feeding back the transfer result to the DMA-CTRL controller through the DMA controller.

[0071] The running program sets the DMA-CTRL controller through the driver, and the DMA-CTRL controller starts DMA transmission by controlling the corresponding DMA controller channel. When the transmission is completed, the DMA controller promptly feeds back the event to the DMA-CTRL controller.

[0072] Specifically, through the DMA controller, whenever the corresponding channel completes the DMA transmission, the corresponding transmission result is fed back to the DMA-CTRL controller.

[0073] When all the channels corresponding to it have completed the DMA transmission, a report is initiated to the DMA-CTRL controller. At this time, the DMA-CTRL controller controls the DMA controller to send a message to the corresponding PCIe-D controller through instructions, and sends a transmission completion interrupt request to the PCIe-H controller corresponding to the host side through the PCIe-D controller, so that the PCIe-H controller passes the transmission completion interrupt request to the running program through the device driver, thereby completing this data transmission task.

[0074] like Figure 4 As shown, the embodiment of the present application also provides a data transmission device between a GPGPU and a host, including:

[0075] at least one processor; and,

[0076] a memory communicatively connected to the at least one processor; wherein,

[0077] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the data transmission method between the GPGPU and the host as described in any of the above embodiments.

[0078] The embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to be: the data transmission method between the GPGPU and the host as described in any of the above embodiments.

[0079] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0080] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0081] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0082] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0083] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0084] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0085] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0086] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0087] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0089] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A data transmission method between a GPGPU and a host, characterized in that: The invention is applied in a data transmission system, wherein the data transmission system includes a host side and a device side, wherein the host side includes a CPU module and multiple PCIe-H controllers, and the device side includes a GPGPU module, wherein the GPGPU module includes a DMA-CTRL controller, multiple DMA controllers, and multiple PCIe-D controllers; wherein the PCIe-H controller, the DMA controller, and the PCIe-D controller correspond to each other, and the DMA-CTRL controller is used to control the DMA controller and the PCIe-D controller; The method comprises: Obtaining, by running a program on the host side, a first transmission attribute corresponding to the current DMA transmission, wherein the first transmission attribute includes the number of channels, a source address, a destination address, and a data length of the DMA transmission; If the number of channels is a designated number indicating automatic setting, then determining the actual number of channels used this time according to the data length of the first transfer attribute and the urgency of the task of this DMA transfer; By means of the DMA-CTRL controller, a corresponding channel is selected based on the actual number of channels, and a second transmission attribute corresponding to each channel is obtained according to the first transmission attribute, wherein the second transmission attribute includes a source address, a destination address, and a data length; The DMA controller is controlled by the DMA-CTRL controller to perform the current DMA transfer based on the second transfer attribute, and the transfer result is fed back to the DMA-CTRL controller by the DMA controller.

2. The method according to claim 1, characterized in that The host side is also provided with a memory module, and the device side is also provided with a video memory module; Obtaining the first transmission attribute corresponding to the current DMA transmission through the running program on the host side, specifically including: Determine the data sender and the data receiver in this DMA transmission by running the program on the host side; If the data sender is the host side and the data receiver is the device side, the source address and the destination address in the first transmission attribute are obtained based on the memory module and the video memory module respectively; If the data sender is the device side and the data receiver is the host side, the source address and the destination address in the first transmission attribute are obtained based on the video memory module and the memory module respectively.

3. The method according to claim 1, characterized in that Each of the PCIe-D controllers and each of the DMA controllers are multi-channel; each channel of the DMA controller corresponds to each channel of the PCIe-D controller; each channel of the DMA controller and each channel of the PCIe-D controller can be controlled individually.

4. The method according to claim 3, characterized in that According to the data length of the first transmission attribute and the urgency of the task of this DMA transmission, the actual number of channels used this time is determined, specifically including: Obtain the maximum data length of a single transfer of each channel of the DMA controller; Determine the actual number of channels used this time based on the maximum data length and the data length of the first transmission attribute; According to the urgency of the task of this DMA transfer, the actual number of channels is corrected.

5. The method according to claim 4, characterized in that Based on the maximum data length and the data length of the first transmission attribute, determining the actual number of channels used this time specifically includes: The data length of the first transmission attribute is divided by the maximum data length, and 1 is added according to the result of the division to obtain the actual number of channels used this time.

6. The method according to claim 3, characterized in that: After obtaining the first transmission attribute corresponding to the current DMA transmission, the method further includes: If the number of channels is a set number indicating manual setting, determining whether the set number exceeds an upper limit of the number of channels corresponding to the PCIe-D controller and the DMA controller; If it does not exceed, the set number will be used as the actual number of channels used this time.

7. The method according to claim 3, characterized in that Feedback of the transmission result to the DMA-CTRL controller through the DMA controller specifically includes: Through the DMA controller, whenever the corresponding channel completes the DMA transmission, the corresponding transmission result is fed back to the DMA-CTRL controller; Through the DMA controller, when all channels corresponding to itself complete DMA transmission, a transmission completion interrupt request is sent to the PCIe-H controller corresponding to the host side through its corresponding PCIe-D controller, so that the PCIe-H controller passes the transmission completion interrupt request to the running program through the device driver.

8. The method according to claim 3, characterized in that The number of the PCIe-H controller, the number of the DMA controller, and the number of the PCIe-D controller are all three; the number of channels of each of the PCIe-D controller and each of the DMA controller are all sixteen.

9. A data transmission device between a GPGPU and a host, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the data transmission method between the GPGPU and the host as described in any one of claims 1 to 8.

10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured as: the data transmission method between a GPGPU and a host as described in any one of claims 1 to 8.

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