Metal-oxide field effect transistor with fin-shaped structure and manufacturing method of metal-oxide field effect transistor

Abstract

The invention relates to a fin-structured metal-oxide field effect transistor and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the fin-structured metal-oxide field effect transistor comprises an n-type first semiconductor layer, an n-type second semiconductor layer, an n-type third semiconductor layer, a p-type fourth semiconductor region, an n-type fifth semiconductor region and a p-type sixth semiconductor region; a gate trench is etched on the n-type third semiconductor layer, a gate oxide layer is arranged in the gate trench and on the upper surface of the n-type third semiconductor layer, and a polycrystalline silicon gate is formed on the upper part of the gate oxide layer; oxide is deposited on the upper surface of the n-type third semiconductor layer to form a metal layer medium, Schottky contact and ohmic contact are formed on the metal layer medium, and the Schottky contact and the ohmic contact are not communicated with each other; the invention also comprises a first metallization layer and a second metallization layer. According to the invention, the on resistance of the device can be greatly reduced, the Schottky diode is embedded on the basis of not increasing the size of the device, and the bipolar degradation effect is avoided.

Description

Technical Field

[0001] The invention relates to a fin-shaped metal-oxide field effect transistor (MOSFET) and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Silicon carbide (SiC) is known for its excellent physical and chemical stability, showing performance beyond conventional materials. The band gap of SiC is about three times that of silicon, and its breakdown electric field strength is one order of magnitude higher than that of silicon, which means that it can provide higher reliability and efficiency in high-voltage applications. In addition, SiC can still maintain good conductivity at high temperatures of 2000°C, making it an ideal semiconductor material for high-temperature environments.

[0003] Among the many SiC crystal forms, the most common ones include 3C-SiC, 4H-SiC, 6H-SiC and 15R-SiC. 4H-SiC is an ideal choice for power electronic devices due to its high electron mobility, low on-resistance and high current density. In fact, 4H-SiC is not only the third-generation semiconductor material with the best performance, the highest degree of commercialization and the most mature technology, but also the preferred material for the manufacture of power semiconductor devices under high voltage, high temperature and radiation resistance.

[0004] Silicon carbide (SiC) MOSFETs are currently at the heart of electric vehicles (EVs) as switching devices, located inside inverters and converters, making important contributions to the performance and long-term reliability of EVs and driving the development of EVs. SiC MOSFETs have received special attention due to their potential to replace existing silicon superjunction transistors and integrated gate bipolar transistor technologies. The silicon carbide power MOSFET market has expanded significantly since 2010 and now exceeds $200 million per year. In particular, as SiC replaces silicon technology in multiple markets such as automotive, photovoltaics, and railways, many new players have entered the market and are expected to achieve double-digit compound annual growth rates. The main high-power silicon carbide MOSFETs currently on the market are mainly vertical lateral diffusion MOSFETs, and major device manufacturers have relatively mature planar MOSFET technology.

[0005] Fig.15The conventional planar MOSFET structure is shown, including a semiconductor substrate 116, an n-type semiconductor epitaxial layer 117, a p-type semiconductor region 118, a high-doping concentration p-type semiconductor region 119, a high-doping concentration n-type semiconductor region 120, a gate oxide layer 108, a polysilicon gate electrode 121, an oxide dielectric layer 122, a second metallization layer 112, and a first metallization layer 111. The gate oxide layer 108 is formed by an oxidation process, and an inversion layer conductive channel is formed near the gate oxide layer 108 in the p-type semiconductor region 118 by controlling the polysilicon gate electrode 121, and the channel connects the high-doping concentration n-type semiconductor region 120 and the n-type semiconductor epitaxial layer 117. Silicon carbide material can grow an oxide layer on the surface by a thermal oxidation process, so SiC MOSFET can basically use the preparation process of silicon-based power MOSFET. However, due to the presence of a large amount of trapped charges and interface charges at the interface of the p-type semiconductor region 118 / gate oxide layer 108 (ie, at the SiC / SiO2 interface), the channel mobility of the SiC MOSFET is low, thereby increasing the on-resistance of the device.

[0006] In addition, SiC MOSFET also has a bipolar degradation effect of the body diode in the application. When the body diode is forward-conducted, the microscopic defect basal plane dislocation (BPD) that existed earlier on the SiC crystal is triggered, and the energy released by the recombination of electrons and holes causes the stacking fault to spread at the BPD. The stacking fault will spread to the surface of the chip and then stop spreading. The area with the enlarged stacking defect inside shows a greater resistance, so the current flowing through it is reduced. This bipolar degradation effect causes the performance of the transistor to degrade. To avoid this situation, the method of embedding Schottky diodes is usually adopted. However, the existing methods of embedding Schottky diodes will inevitably increase the size of the device, thereby leading to an increase in the cost of the device. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present invention provides a fin-shaped metal-oxide field effect transistor and a method for manufacturing the same, which can significantly reduce the on-resistance of the device and achieve embedded Schottky diodes without increasing the size of the device, thereby avoiding the bipolar degradation effect.

[0008] The present invention adopts the following technical solution: A fin-shaped metal-oxide field effect transistor, comprising, from bottom to top, an n-type first semiconductor layer, an n-type second semiconductor layer and an n-type third semiconductor layer, wherein a p-type fourth semiconductor region is formed on the upper surface of the n-type third semiconductor layer by ion implantation, an n-type fifth semiconductor region is implanted on the upper surface of the p-type fourth semiconductor region by ion implantation, and a p-type sixth semiconductor region is formed on the upper surface of the n-type third semiconductor layer, wherein the depth of the p-type sixth semiconductor region is greater than that of the n-type fifth semiconductor region, the p-type sixth semiconductor region is connected to the p-type fourth semiconductor region and does not exceed the p-type fourth semiconductor region; A gate trench is etched on the n-type third semiconductor layer, the gate trench penetrates the p-type fourth semiconductor region to reach the n-type third semiconductor layer, a gate oxide layer is arranged inside the gate trench and on the upper surface of the n-type third semiconductor layer, a polysilicon gate is formed on the upper part of the gate oxide layer, and the polysilicon gate is isolated from the p-type fourth semiconductor region, the n-type fifth semiconductor region, and the n-type third semiconductor layer by the gate oxide layer; the polysilicon gate is removed to the upper surface of the n-type third semiconductor layer, oxide is deposited on the upper surface of the n-type third semiconductor layer to form a metal layer medium, an opening one is formed in the center of the metal layer medium, and openings two are formed at both ends, the opening one is a Schottky contact, the opening two is an ohmic contact, and the opening one and the opening two are not connected to each other; A first metallization layer is disposed at the bottom of the n-type first semiconductor layer, a second metallization layer is disposed at the opposite side of the first metallization layer, and the first metallization layer is in contact with the n-type first semiconductor layer.

[0009] As an anisotropic crystal, silicon carbide has different properties on different crystal planes. Planar MOSFET forms a conductive channel on the (0001) crystal plane. According to the unique properties of silicon carbide crystals, compared with the (0001) crystal plane, the conductive channel formed on the (11-20) crystal plane has a lower interface defect density, resulting in lower channel resistance, higher channel mobility, faster switching speed and less loss.

[0010] In the production of silicon carbide power devices, usually along the <0001> The epitaxial layer grows in the direction of Fig.15 In the conventional planar MOSFET structure shown in FIG. 1 , the channel is formed at the interface between the p-type semiconductor region and the gate oxide layer, that is, Fig.16 In the present invention, since the direction of the gate oxide layer is perpendicular to the direction in the conventional planar MOSFET structure, the channel is formed at the interface between the p-type fourth semiconductor region 104 and the gate oxide layer 108. Fig.16 The middle is the (11-20) crystal plane.

[0011] A Schottky diode is embedded in a traditional MOSFET device. When it is forward-conducting, the Schottky diode does not work. In the present invention, a Schottky contact is arranged on the n-type third semiconductor layer. When the body diode is reversed, the embedded Schottky contact has a lower turn-on voltage, so the Schottky diode is turned on before the pn junction of the body diode, thereby avoiding the turn-on of the body diode and also avoiding the occurrence of the bipolar degeneration effect.

[0012] The present invention adds an n-type third semiconductor layer as a current spreading layer. The n-type third semiconductor layer has a higher doping concentration than the n-type second semiconductor layer, and can allow a higher current to pass through during forward conduction while reducing the width of the JFET region to maintain the breakdown voltage.

[0013] Preferably, the n-type first semiconductor layer is an N-type semiconductor substrate made of silicon carbide with high concentration of impurities added; The thickness of the N-type semiconductor substrate is in the range of 300 μm to 350 μm, and the impurity concentration in the n-type first semiconductor layer is 1×10 19 cm -3 .

[0014] Preferably, the n-type second semiconductor layer is formed on the n-type first semiconductor layer and is made of silicon carbide with impurities added at a lower concentration. The thickness and impurity concentration of the n-type second semiconductor layer depend on the operating voltage design of the semiconductor device. Generally, for an operating voltage of 1200V, the n-type second semiconductor layer is 10 μm and the impurity concentration is 1×10 16 cm -3 .

[0015] Preferably, the n-type third semiconductor layer is on the n-type second semiconductor layer as a current spreading layer and is made of silicon carbide with a lower concentration of impurities added. The impurity concentration of the n-type third semiconductor layer is slightly higher than that of the n-type second semiconductor layer. The thickness of the n-type third semiconductor layer is 1-3 μm, and the impurity concentration is 1×10 16 cm -3 Up to 1×10 17 cm -3 .

[0016] Preferably, the p-type fourth semiconductor region is located within the n-type third semiconductor layer and is formed by ion implantation on the basis of the n-type third semiconductor layer. A JFET region is formed between the two p-type fourth semiconductor regions. The spacing between the JFET regions cannot be too small to prevent the device from being turned on normally. The width of the JFET region is greater than 1.5 μm. The thickness of the p-type fourth semiconductor region defines the vertical channel length. The thickness of the p-type fourth semiconductor region is 0.1-2 μm, and the doping concentration is usually 5×10 17 cm -3 .

[0017] Preferably, the n-type fifth semiconductor region is also formed by ion implantation, with a depth of 0.3-0.5 μm; the impurity concentration of the n-type fifth semiconductor region is 1×10 20 cm -3 And not less than 1×10 18 cm -3 .

[0018] Preferably, the depth of the p-type sixth semiconductor region is greater than that of the n-type fifth semiconductor region and the p-type sixth semiconductor region, and the impurity concentration of the p-type sixth semiconductor region is 1×10 20 cm -3 And not less than 1×1018 cm -3 .

[0019] Preferably, the gate trench penetrates the p-type fourth semiconductor region to reach the n-type third semiconductor layer, and a Schottky contact is formed on the n-type third semiconductor layer and a portion of the p-type fourth semiconductor region; an ohmic contact is formed on the n-type fifth semiconductor region and the p-type sixth semiconductor region.

[0020] A method for manufacturing a metal-oxide field effect transistor based on the above-mentioned fin-shaped structure comprises the following steps: (1) preparing an n-type first semiconductor layer from silicon carbide to form an N-type semiconductor substrate; (2) forming an n-type second semiconductor layer on the surface of the n-type first semiconductor layer by epitaxial growth, and further forming an n-type third semiconductor layer on the surface of the n-type second semiconductor layer by epitaxial growth; (3) Implanting aluminum or boron ion impurity ions into the surface of the n-type third semiconductor layer to form a p-type fourth semiconductor region; (4) implanting impurity ions of high concentration of nitrogen or phosphorus ions into the upper surface of the p-type fourth semiconductor region to form an n-type fifth semiconductor region, wherein the implantation depth of the n-type fifth semiconductor region is shallower than that of the p-type fourth semiconductor region; then implanting impurity ions of high concentration of aluminum or boron ions into the upper surface of the n-type third semiconductor layer to form a p-type sixth semiconductor region, wherein the implantation depth of the p-type sixth semiconductor region is greater than that of the n-type fifth semiconductor region; (5) forming a gate trench on the n-type third semiconductor layer by dry plasma etching, then forming a gate oxide layer by thermal oxidation process, and depositing polysilicon on the gate oxide layer to form a polysilicon gate; (6) removing excess polysilicon to the upper surface of the n-type third semiconductor layer by plasma etching, and depositing oxide to form a metal layer dielectric; (7) On the metal layer dielectric, an ohmic contact region is formed by dry etching, a layer of metal is deposited to form an ohmic contact, and then a Schottky contact is formed by dry etching; (8) Finally, deposit the first metallization layer and the second metallization layer.

[0021] Preferably, in step (5), the thickness of the gate oxide layer is 40 nm to 100 nm.

[0022] For any details not provided in the present invention, please refer to the prior art.

[0023] The beneficial effects of the present invention are: 1. The present invention improves on the traditional planar MOSFET device structure by etching a gate trench, which penetrates the n-type first semiconductor layer, the n-type second semiconductor layer to the n-type third semiconductor layer to form a fin-shaped gate oxide layer; by applying voltage to the gate electrode formed by the polysilicon gate, a conductive channel is formed on the (11-20) crystal plane in the vertical direction. The present invention can achieve a higher channel mobility and significantly reduce the on-resistance by selecting a suitable channel crystal plane and optimizing the design structure. It has a higher channel density, and at the same time, the SiC crystal plane interface defects where the channel is located are less, and has a higher channel mobility, so it can achieve a lower specific on-resistance.

[0024] 2. The present invention adds an additional opening 2 to realize the function of the Schottky diode and forms a Schottky contact on the JFET region, which can effectively reduce the bipolar degradation effect and reasonably utilize the space without increasing the device size, thereby greatly reducing the device cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings in the specification, which constitute a part of the present application, are used to provide further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0026] Figure 1 This is a schematic diagram of the structure of the n-type first semiconductor layer in an embodiment of the present invention; Figure 2 A semiconductor cross-sectional view showing the formation of an n-type second semiconductor layer in an embodiment of the present invention; Figure 3 A semiconductor cross-sectional view showing the formation of an n-type third semiconductor layer in an embodiment of the present invention; Figure 4 A cross-sectional view of a semiconductor formed by ion implantation into a p-type fourth semiconductor region in an embodiment of the present invention; Figure 5 A cross-sectional view of a semiconductor implanted with an n-type fifth semiconductor region and a p-type sixth semiconductor region in an embodiment of the present invention; Figure 6 A cross-sectional view of a semiconductor device in which a gate trench is formed in an embodiment of the present invention; Figure 7 A cross-sectional view of a semiconductor device in which a gate oxide layer is formed in an embodiment of the present invention; Figure 8 A cross-sectional view of a semiconductor device for forming a polysilicon gate in an embodiment of the present invention; Fig. 9 A cross-sectional view of a semiconductor device with excess polysilicon removed according to an embodiment of the present invention; Fig.10 A cross-sectional view of a semiconductor in which a metal layer medium is formed in an embodiment of the present invention; Fig.11A cross-sectional view of a semiconductor device for forming an ohmic contact in an embodiment of the present invention; Fig.12 A cross-sectional view of a semiconductor in which a Schottky contact is formed in an embodiment of the present invention; Fig.13 A cross-sectional view of a semiconductor in which a first metallization layer is formed in an embodiment of the present invention; Fig.14 A cross-sectional view of a semiconductor in which a second metallization layer is formed in an embodiment of the present invention; Fig.15 Shown is a cross-sectional view of a conventional planar MOSFET structure; Fig.16 Schematic diagram of the main crystal planes of 4H-SiC crystal; Fig.17 The output characteristics of the structure of the present invention and the traditional planar MOSFET are compared; Fig.18 is the characteristic curve of the structure of the present invention under reverse voltage; Fig.19 A schematic cross-sectional view of a metal-oxide field effect transistor with a fin structure according to Example 1 of the present invention; Fig. 20 A schematic cross-sectional view of a metal-oxide field effect transistor with a fin structure according to Example 2 of the present invention; In the figure, 101-n-type first semiconductor layer, 102-n-type second semiconductor layer, 103-n-type third semiconductor layer, 104-p-type fourth semiconductor region, 105-n-type fifth semiconductor region, 106-p-type sixth semiconductor region, 107-gate trench, 108-gate oxide layer, 109-polysilicon gate, 110-Schottky contact, 111-first metallization layer, 112-second metallization layer, 113-ohmic contact, 114-metal layer dielectric, 115-polysilicon; 116-semiconductor substrate, 117-n-type semiconductor epitaxial layer, 118-p-type semiconductor region, 119-high doping concentration p-type semiconductor region, 120-high doping concentration n-type semiconductor region, 121-polysilicon gate electrode, 122-oxide dielectric layer. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the drawings in the implementation of this specification, but are not limited to this. Anything not fully described in the present invention shall be based on the conventional technology in the art.

[0028] Example 1 A fin-shaped metal-oxide field effect transistor, such as Figure 1As shown, it includes, from bottom to top, an n-type first semiconductor layer 101, an n-type second semiconductor layer 102, and an n-type third semiconductor layer 103. A p-type fourth semiconductor region 104 is formed on the upper surface of the n-type third semiconductor layer 103 by ion implantation. An n-type fifth semiconductor region 105 is implanted on the upper surface of the p-type fourth semiconductor region 104 by ion implantation. A p-type sixth semiconductor region 106 is formed on the upper surface of the n-type third semiconductor layer 103. The depth of the p-type sixth semiconductor region 106 is greater than that of the n-type fifth semiconductor region 105, and the p-type sixth semiconductor region 106 is connected to the p-type fourth semiconductor region 104 and does not exceed the p-type fourth semiconductor region 104. A gate trench 107 is etched on the n-type third semiconductor layer 103, the gate trench 107 penetrates the p-type fourth semiconductor region to reach the n-type third semiconductor layer, a gate oxide layer 108 is arranged inside the gate trench 107 and on the upper surface of the n-type third semiconductor layer 103, a polysilicon gate 109 is formed on the upper part of the gate oxide layer 108, and the polysilicon gate 109 is isolated from the p-type fourth semiconductor region 104, the n-type fifth semiconductor region 105, and the n-type third semiconductor layer 103 by the gate oxide layer 108; the polysilicon gate 109 is removed to the upper surface of the n-type third semiconductor layer 103, and oxide is deposited on the upper surface of the n-type third semiconductor layer 103 to form a metal layer dielectric 114, an opening 1 is formed in the center of the metal layer dielectric 114, and openings 2 are formed at both ends, the opening 1 is a Schottky contact 110, the opening 2 is an ohmic contact 113, and the opening 1 and the opening 2 are not connected to each other; A first metallization layer 111 is disposed at the bottom of the n-type first semiconductor layer 101 , and a second metallization layer 112 is disposed on the opposite side of the first metallization layer 111 . The first metallization layer 111 is in contact with the n-type first semiconductor layer 101 .

[0029] As an anisotropic crystal, silicon carbide has different properties on different crystal planes. Fig.16 As shown, the planar MOSFET forms a conductive channel on the (0001) crystal plane. According to the unique properties of silicon carbide crystals, compared with the (0001) crystal plane, the conductive channel formed on the (11-20) crystal plane has a lower interface defect density, resulting in lower channel resistance, higher channel mobility, faster switching speed and less loss.

[0030] In the production of silicon carbide power devices, usually along the <0001> The epitaxial layer grows in the direction of Fig.15 In the conventional planar MOSFET structure shown in FIG. 1 , a channel is formed at the interface between the p-type semiconductor region 118 and the gate oxide layer 108, that is, Fig.16 On the (0001) crystal plane shown, Fig.16In the embodiment, a1, a2, a3, and c are hexagonal coordinate axes. In the present invention, since the direction in which the gate oxide layer is formed is perpendicular to the direction in the conventional planar MOSFET structure, the channel is formed at the interface between the p-type fourth semiconductor region 104 and the gate oxide layer 108. Fig.16 The middle is the (11-20) crystal plane.

[0031] A Schottky diode is embedded in a traditional MOSFET device. When it is forward-conducting, the Schottky diode does not work. In the present invention, a Schottky contact is arranged on the n-type third semiconductor layer. When the body diode is reversed, the embedded Schottky contact has a lower turn-on voltage, so the Schottky diode is turned on before the pn junction of the body diode, thereby avoiding the turn-on of the body diode and also avoiding the occurrence of the bipolar degeneration effect.

[0032] The present invention adds an n-type third semiconductor layer 103 as a current spreading layer. The n-type third semiconductor layer 103 has a higher doping concentration than the n-type second semiconductor layer 102, and can allow a higher current to pass through during forward conduction while reducing the width of the JFET region to maintain the breakdown voltage.

[0033] The n-type first semiconductor layer 101 is an N-type semiconductor substrate made of silicon carbide with high concentration impurities added; The thickness of the N-type semiconductor substrate is in the range of 300 μm to 350 μm, and the impurity concentration in the n-type first semiconductor layer is 1×10 19 cm -3 .

[0034] The n-type second semiconductor layer 102 is formed on the n-type first semiconductor layer and is made of silicon carbide with low concentration impurities added. The thickness and impurity concentration of the n-type second semiconductor layer 102 depend on the operating voltage design of the semiconductor device. Generally, for a 1200V operating voltage, the n-type second semiconductor layer is 10 μm and the impurity concentration is 1×10 16 cm -3 .

[0035] The n-type third semiconductor layer 103 is on the n-type second semiconductor layer and is made of silicon carbide with low-concentration impurities added as a current spreading layer. The impurity concentration of the n-type third semiconductor layer is slightly higher than that of the n-type second semiconductor layer. The thickness of the n-type third semiconductor layer 103 is 1-3 μm, and the impurity concentration is 1×10 16 cm -3 Up to 1×10 17 cm -3 .

[0036] The p-type fourth semiconductor region 104 is located within the n-type third semiconductor layer and is formed by ion implantation on the basis of the n-type third semiconductor layer. A JFET region is formed between the two p-type fourth semiconductor regions. The spacing between the JFET regions cannot be too small to prevent the device from being turned on normally. The width of the JFET region is greater than 1.5 μm; The thickness of the p-type fourth semiconductor region 104 defines the vertical channel length. The thickness of the p-type fourth semiconductor region is 0.1-2 μm, and the doping concentration is usually 5×10 17 cm -3 .

[0037] The n-type fifth semiconductor region 105 is also formed by ion implantation, with a depth of 0.3-0.5 μm; the impurity concentration of the n-type fifth semiconductor region 105 is 1×10 20 cm -3 And not less than 1×10 18 cm -3 .

[0038] The depth of the p-type sixth semiconductor region 106 is greater than that of the n-type fifth semiconductor region. The impurity concentration of the p-type sixth semiconductor region 106 is 1×10 20 cm -3 And not less than 1×10 18 cm -3 .

[0039] The gate trench 107 penetrates the p-type fourth semiconductor region 104 to reach the n-type third semiconductor layer 103 . The Schottky contact 110 is formed on the n-type third semiconductor layer and part of the p-type fourth semiconductor region. The ohmic contact 113 is formed on the n-type fifth semiconductor region and the p-type sixth semiconductor region.

[0040] A method for manufacturing a metal-oxide field effect transistor based on the above-mentioned fin-shaped structure comprises the following steps: (1) Prepare an n-type first semiconductor layer 101 from silicon carbide to form an N-type semiconductor substrate, such as Figure 1 As shown; (2) forming an n-type second semiconductor layer 102 on the surface of the n-type first semiconductor layer by epitaxial growth, such as Figure 2 , and then form an n-type third semiconductor on the surface of the n-type second semiconductor layer by epitaxial growth, such as Figure 3 As shown; (3) Injecting impurity ions of boron ions into the surface of the n-type third semiconductor layer to form a p-type fourth semiconductor region 104, such as Figure 4 As shown; (4) Implanting impurity ions of high concentration nitrogen ions into the upper surface of the p-type fourth semiconductor region to form an n-type fifth semiconductor region 105, wherein the implantation depth of the n-type fifth semiconductor region 105 is shallower than that of the p-type fourth semiconductor region; then implanting impurity ions of high concentration boron ions into the upper surface of the n-type third semiconductor layer to form a p-type sixth semiconductor region 106, wherein the implantation depth of the p-type sixth semiconductor region 106 is greater than that of the n-type fifth semiconductor region 105, as shown in FIG. Figure 5 As shown; (5) Forming a gate trench 107 on the n-type third semiconductor layer 103 by dry plasma etching, such as Figure 6 As shown, a gate oxide layer 108 is then formed by a thermal oxidation process. Figure 7 As shown, polysilicon is deposited on the gate oxide layer 108 to form a polysilicon gate 109. Figure 8 As shown; the thickness of the gate oxide layer 108 is 40nm to 100nm.

[0041] (6) Removing excess polysilicon to the upper surface of the n-type third semiconductor layer by plasma etching, such as Fig. 9 As shown; depositing oxide to form a metal layer dielectric 114, such as Fig.10 As shown; (7) On the metal layer dielectric 114, an ohmic contact region is formed by dry etching, a layer of metal is deposited to form an ohmic contact 113, and then a Schottky contact 110 is formed by dry etching, as shown in FIG. Fig.11 , Fig.12 As shown; (8) Finally, the first metallization layer 111 and the second metallization layer 112 are deposited, as shown in FIG. Fig.13 and Fig.14 shown.

[0042] The overall structure is as follows Fig.19 shown.

[0043] The semiconductor device of the present invention is not limited to the above-mentioned embodiment 1. The specific structure of the components of the semiconductor device according to the present invention can be changed in design in various ways. For example, the groove profile of the sidewall is drawn in the vertical direction, or it can be drawn at an angle of 0 to 30 degrees with the vertical equation, which should be regarded as the protection scope of the present invention.

[0044] In the prior art, the design of devices with embedded Schottky contacts will inevitably increase the size of the device, thereby leading to an increase in the cost of the device. In the preparation process of power devices, the link with the highest cost share is the preparation of silicon carbide substrates. The restrictive factors affecting the cost of silicon carbide substrates are slow production rate, low product yield, and high energy consumption in the preparation process, mainly due to: the current mainstream commercial PVT method has slow crystal growth rate and difficulty in defect control. Since large-size substrates are difficult to produce and have more defects, the size of a single device directly affects the number of devices produced on the same substrate, thereby affecting the overall manufacturing cost. The embodiment of the present invention creatively designs opening two to realize the function of a Schottky diode, and forms a Schottky contact above the JFET area, which can effectively reduce the bipolar degradation effect, and reasonably utilize space without increasing the size of the device, greatly reducing the cost of the device.

[0045] Example 2 A fin-shaped metal-oxide field effect transistor, as described in Example 1, except that polysilicon 115 is deposited at the Schottky contact 110 to replace the Schottky contact to form a heterojunction diode (i.e., polysilicon 115 is deposited at the Schottky contact of Example 1 to replace the Schottky contact of Example 1), which also plays the same freewheeling role as the Schottky contact, reducing the bipolar degradation effect of the body diode, such as Fig. 20 The polysilicon 115 may be a second conductivity type heavily doped with aluminum and boron, or a first conductivity type heavily doped with nitrogen and phosphorus, the first conductivity type being n-type, and the second conductivity type being p-type.

[0046] right Fig.15 A TCAD 2D simulation is performed to compare the conventional planar MOSFET structure with the structure of Example 1 of the present invention.

[0047] Fig.17 The output characteristics of the structure of Example 1 of the present invention and the traditional planar MOSFET are compared, wherein the horizontal axis is the drain voltage (Vd), in V; the vertical axis is the drain current (Id), in A; Vg represents the gate voltage, Figure 4The output characteristics in the figure show the relationship between the drain voltage (Vd) and the drain current (Id) at a specific gate voltage (Vg), and the on-resistance is the ratio of the drain voltage to the drain current when the drain voltage is 1V. It can be seen from the figure that the on-resistance of the structure of the present invention is much lower than that of the traditional planar MOSFET. The low on-resistance of the structure of the present invention is mainly due to two reasons. First, the channel width of the structure of the present invention is larger than that of the traditional planar MOSFET, and the channel resistance is an important part of the on-resistance of the MOSFET. The channel resistance is inversely proportional to the channel width. When the channel length is the same, the wider channel width effectively reduces the channel resistance, thereby reducing the overall on-resistance. Second, due to the anisotropy of 4H-SiC, the on-channel of the traditional planar MOSFET is built on the (0001) crystal plane, and the channel of the structure of the present invention is located on the (11-20) crystal plane perpendicular to the (0001) crystal plane. For MOSFET devices, the existence of gate oxide defects is inevitable and will greatly affect the performance and reliability of the device. Current research shows that the SiC / SiO2 interface on the (11-20) crystal plane has fewer defects than the interface on the (0001) crystal plane, resulting in a significant advantage in mobility. Therefore, choosing to form a channel on the (11-20) crystal plane can improve the gate oxide reliability of the device and reduce the on-resistance.

[0048] Fig.18 : The characteristic of the device of the present invention under reverse voltage, wherein the horizontal axis is the drain voltage (Vd), the unit is V; the vertical axis is the drain current (Id), the unit is A; when the gate is turned off, the body diode of the MOSFET of the traditional structure is turned on at Vd of about -2.1V, and the present invention is turned on at point A (Vd is about -0.7V) because the SBD structure formed by the second metallization layer 112 and the third semiconductor layer 103 at the Schottky contact 110 is embedded, which can avoid the conduction of the body diode to a greater extent and reduce the bipolar degradation effect.

[0049] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A fin-shaped metal-oxide field effect transistor, characterized in that: The device comprises, from bottom to top, an n-type first semiconductor layer, an n-type second semiconductor layer and an n-type third semiconductor layer, wherein a p-type fourth semiconductor region is formed on the upper surface of the n-type third semiconductor layer by ion implantation, an n-type fifth semiconductor region is implanted on the upper surface of the p-type fourth semiconductor region by ion implantation, and a p-type sixth semiconductor region is formed on the upper surface of the n-type third semiconductor layer, wherein the depth of the p-type sixth semiconductor region is greater than that of the n-type fifth semiconductor region, the p-type sixth semiconductor region is connected to the p-type fourth semiconductor region and does not exceed the p-type fourth semiconductor region; A gate trench is etched on the n-type third semiconductor layer, a gate oxide layer is arranged inside the gate trench and on the upper surface of the n-type third semiconductor layer, and a polysilicon gate is formed on the upper part of the gate oxide layer; Removing the polysilicon gate to the upper surface of the n-type third semiconductor layer, depositing oxide on the upper surface of the n-type third semiconductor layer to form a metal layer dielectric, forming an opening 1 in the center of the metal layer dielectric, and forming opening 2 at both ends, the opening 1 is a Schottky contact, the opening 2 is an ohmic contact, and the opening 1 and the opening 2 are not connected to each other; A first metallization layer is disposed at the bottom of the n-type first semiconductor layer, a second metallization layer is disposed at the opposite side of the first metallization layer, and the first metallization layer is in contact with the n-type first semiconductor layer.

2. The metal-oxide field effect transistor with a fin structure according to claim 1, characterized in that: The n-type first semiconductor layer is an N-type semiconductor substrate made of silicon carbide; The thickness of the N-type semiconductor substrate is in the range of 300 μm to 350 μm, and the impurity concentration in the n-type first semiconductor layer is 1×10 19 cm -3 .

3. The metal-oxide field effect transistor with a fin structure according to claim 2, characterized in that: The n-type second semiconductor layer is made of silicon carbide. For a working voltage of 1200 V, the n-type second semiconductor layer is 10 μm and the impurity concentration is 1×10 16 cm -3 .

4. The metal-oxide field effect transistor with a fin structure according to claim 3, characterized in that: The n-type third semiconductor layer is a current spreading layer made of silicon carbide. The thickness of the n-type third semiconductor layer is 1-3 μm, and the impurity concentration is 1×10 16 cm -3 Up to 1×10 17 cm -3 .

5. The metal-oxide field effect transistor with a fin structure according to claim 4, characterized in that: A JFET region is formed between the two p-type fourth semiconductor regions, and a width of the JFET region is greater than 1.5 μm; The thickness of the p-type fourth semiconductor region is 0.1-2 μm, and the doping concentration is usually 5×10 17 cm -3 .

6. The metal-oxide field effect transistor with a fin structure according to claim 5, characterized in that: The depth of the n-type fifth semiconductor region is 0.3-0.5 μm; the impurity concentration of the n-type fifth semiconductor region is 1×10 20 cm -3 And not less than 1×10 18 cm -3 .

7. The metal-oxide field effect transistor with a fin structure according to claim 6, characterized in that: The depth of the p-type sixth semiconductor region is greater than that of the n-type fifth semiconductor region and the p-type sixth semiconductor region. The impurity concentration of the p-type sixth semiconductor region is 1×10 20 cm -3 And not less than 1×10 18 cm -3 .

8. The metal-oxide field effect transistor with a fin structure according to claim 7, characterized in that: The gate trench penetrates the p-type fourth semiconductor region to reach the n-type third semiconductor layer, and Schottky contact is formed on the n-type third semiconductor layer and part of the p-type fourth semiconductor region; ohmic contact is formed on the n-type fifth semiconductor region and the p-type sixth semiconductor region.

9. A method for manufacturing a metal-oxide field effect transistor having a fin structure according to claim 8, characterized in that: The steps include: (1) preparing an n-type first semiconductor layer from silicon carbide to form an N-type semiconductor substrate; (2) forming an n-type second semiconductor layer on the surface of the n-type first semiconductor layer by epitaxial growth, and further forming an n-type third semiconductor layer on the surface of the n-type second semiconductor layer by epitaxial growth; (3) Implanting aluminum or boron ion impurity ions into the surface of the n-type third semiconductor layer to form a p-type fourth semiconductor region; (4) implanting impurity ions of nitrogen or phosphorus into the upper surface of the p-type fourth semiconductor region to form an n-type fifth semiconductor region, wherein the implantation depth of the n-type fifth semiconductor region is shallower than that of the p-type fourth semiconductor region; then implanting impurity ions of aluminum or boron ions into the upper surface of the n-type third semiconductor layer to form a p-type sixth semiconductor region, wherein the implantation depth of the p-type sixth semiconductor region is greater than that of the n-type fifth semiconductor region; (5) forming a gate trench on the n-type third semiconductor layer by dry plasma etching, then forming a gate oxide layer by thermal oxidation process, and depositing polysilicon on the gate oxide layer to form a polysilicon gate; (6) removing excess polysilicon to the upper surface of the n-type third semiconductor layer by plasma etching, and depositing oxide to form a metal layer dielectric; (7) On the metal layer dielectric, an ohmic contact region is formed by dry etching, a layer of metal is deposited to form an ohmic contact, and then a Schottky contact is formed by dry etching; (8) Finally, deposit the first metallization layer and the second metallization layer.

10. The method for manufacturing a fin-shaped metal-oxide field effect transistor according to claim 9, characterized in that: In step (5), the thickness of the gate oxide layer is 40 nm to 100 nm.

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