Successive approximation analog-to-digital converter with mismatch calibration

Abstract

The invention provides a successive approximation analog-to-digital converter with mismatch calibration, and relates to the field of semiconductor integrated circuits. The successive approximation analog-to-digital converter comprises a sampling hold circuit, a differential capacitor array, a comparator module, a successive approximation logic circuit and a calibration logic circuit. The differential capacitor array comprises a successive approximation bit capacitor array, an automatic balance capacitor array and a calibration capacitor array. The successive approximation bit capacitor array is used for quantizing the analog input voltage to generate an analog output voltage. The successive approximation bit capacitor array comprises a redundant bit capacitor, and the redundant bit capacitor is used for calibrating digital deviation in the quantization process. The automatic balancing capacitor array and the calibration capacitor array are respectively connected with a P end and an N end of the successive approximation bit capacitor array, the automatic balancing capacitor array is used for balancing common-mode voltages of the P end and the N end, and the calibration capacitor array is used for calibrating the digital weight of the successive approximation bit capacitor array. According to the invention, the influence of noise and common-mode voltage offset on the analog-to-digital conversion precision can be reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a successive approximation analog-to-digital converter with mismatch calibration. Background Art

[0002] Successive approximation ADC is the abbreviation of successive-approximation register ADC (SAR ADC). It is an analog-to-digital converter that converts continuous analog signals into discrete digital representations. It uses a binary search algorithm to search and compare the quantized values ​​of various possible input voltages, and ultimately obtains the digital signal output of the analog-to-digital conversion.

[0003] Successive approximation analog-to-digital converters are usually manufactured on chips. During the manufacturing process of the chip, the uncertainty of each processing step will make the nominal design value of each device different from the final physical implementation value. The absolute deviation value caused by this production uncertainty may be as high as 20%, and the specific deviation degree of each device is unpredictable. Mismatch usually refers to the relative deviation of parameters between two devices of the same type on the same chip, rather than the absolute deviation of the parameter value of a single device. The binary weighted capacitor array inside the successive approximation analog-to-digital converter is prone to mismatch during manufacturing, which will cause the nonlinearity of the successive approximation analog-to-digital converter. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a successive approximation analog-to-digital converter with mismatch calibration, which can reduce the influence of noise such as clock jitter and common-mode voltage offset on the successive approximation analog-to-digital converter.

[0005] The successive approximation analog-to-digital converter with mismatch calibration provided by an embodiment of the present invention comprises: a sampling and holding circuit, which is used to sample an analog signal to obtain an analog input voltage; a differential capacitor array, which comprises a successive approximation capacitor array, an automatic balancing capacitor array and a calibration capacitor array, wherein the successive approximation capacitor array is used to quantize the analog input voltage to generate an analog output voltage, the successive approximation capacitor array comprises redundant capacitors, and the redundant capacitors are used to calibrate the digital deviation in the quantization process, the automatic balancing capacitor array and the calibration capacitor array are respectively connected to the P terminal and the N terminal of the successive approximation capacitor array, the automatic balancing capacitor array is used to balance the common mode voltage of the P terminal and the N terminal, and the calibration capacitor array is used to calibrate the digital deviation in the quantization process. The capacitor array is used to calibrate the digital weight of the successive approximation capacitor array; the comparator module, the input end of the comparator module is respectively connected to the sampling and holding circuit and the differential capacitor array, the comparator module is used to compare the analog output signal with the analog input signal and output the comparison result; the successive approximation logic circuit is connected to the output end of the comparator and the differential capacitor array, the successive approximation logic circuit is used to control and manage the state of the capacitor in the successive approximation capacitor array according to the comparison result, so that the analog output voltage successively approaches the analog input voltage; the calibration logic circuit is connected to the output end of the comparator and the differential capacitor array, the calibration logic circuit is used to control and manage the automatic balancing capacitor array and the calibration capacitor array.

[0006] According to an embodiment of the present invention, a successive approximation capacitor array includes a low-segment capacitor array, a middle-segment capacitor array and a high-segment capacitor array, wherein the low-segment capacitor array, the middle-segment capacitor array and the high-segment capacitor array are composed of capacitor arrays with non-binary encoded integer weights; and the sampling and holding circuit performs sampling through the lower plate of the high-segment capacitor array.

[0007] According to an embodiment of the present invention, the calibration logic circuit includes a self-measurement calibration circuit for controlling and managing a calibration capacitor array; the self-measurement calibration circuit takes a specific bit of the differential capacitor array as a base point, measures and calculates the weights of the P terminal and the N terminal respectively through the calibration capacitor array, and uses half of the difference between the weights of the P terminal and the N terminal as the calibrated weight.

[0008] According to an embodiment of the present invention, an automatic balancing capacitor array is connected to the P-end and the N-end of the mid-segment capacitor array; the calibration logic circuit includes an automatic balancing circuit for controlling and managing the automatic balancing capacitor array, wherein the automatic balancing circuit makes the automatic balancing capacitor array equivalent to adding a capacitance of at most 6 capacitance units in the mid-segment capacitor array.

[0009] According to an embodiment of the present invention, an automatic balancing capacitor array includes a low-segment balancing capacitor array and a middle-segment balancing capacitor array, the low-segment balancing capacitor array has the same weight configuration as the low-segment capacitor array, and the weight configuration of the middle-segment balancing capacitor array is 2:1:1; the automatic balancing circuit controls the weight of the capacitor of the automatic balancing capacitor array connected to the P terminal or the N terminal so that the deviation value of the common mode voltage between the P terminal and the N terminal is within a preset difference.

[0010] According to an embodiment of the present invention, the low-segment capacitor array, the middle-segment capacitor array, and the high-segment capacitor array all include redundant bit capacitors.

[0011] According to an embodiment of the present invention, the successive approximation analog-to-digital converter also includes a disturbance signal injection module, and the calibration logic circuit also includes a pure analog dithering circuit implemented based on a residual voltage control strategy, wherein the disturbance signal injection module is used to inject a pseudo-random disturbance signal into the redundant bit capacitor through the pure analog dithering circuit.

[0012] According to an embodiment of the present invention, the operation mode of the successive approximation analog-to-digital converter includes a calibration mode and a normal operating mode, wherein the calibration mode is completed before the start of the normal operating mode, wherein the calibration mode includes a common-mode voltage automatic balancing stage, a self-measurement calibration stage and a jitter injection stage, and the normal operating mode includes a sampling stage, a holding stage and a quantization stage.

[0013] According to an embodiment of the present invention, the weight of any non-lowest-order weighted capacitor in the high-segment capacitor array is less than the sum of the weights of all weighted capacitors at lower orders than any non-lowest-order weighted capacitor.

[0014] According to an embodiment of the present invention, the lower portion of the low-segment capacitor array includes a sub-minimum unit capacitor array for improving the accuracy of calibrating digital bit weights.

[0015] According to the successive approximation analog-to-digital converter with mismatch calibration of the embodiment of the present invention, a successive approximation position capacitor array, an automatic balancing capacitor array and a calibration capacitor array are integrated in a differential capacitor array, and the digital deviation in the quantization process is calibrated by adding redundant position capacitors in the successive approximation position capacitor array, thereby suppressing the influence of non-ideal factors such as noise offset on the analog-to-digital conversion result; the automatic balancing capacitor array is connected to the P terminal and the N terminal of the successive approximation position capacitor array, and the size of the automatic balancing capacitor connected to the P terminal and the N terminal is changed by comparing and detecting the common mode voltage at the P and N terminals, so that the common mode voltage at the P terminal and the N terminal can be balanced, and the calibration capacitor array is connected to the P terminal and the N terminal of the successive approximation position capacitor array, and the calibration capacitor array can calibrate the digital weight of the successive approximation position capacitor array. Compared with the existing scheme, the mismatch calibration of the successive approximation analog-to-digital converter of the embodiment of the present invention is more effective and sufficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 It is a schematic diagram of the overall structure of an existing successive approximation analog-to-digital converter.

[0018] Figure 2 It is a schematic diagram of the principle circuit of a 5-bit successive approximation analog-to-digital converter using a binary weighted capacitor array.

[0019] Figure 3 It is a schematic diagram of the residual voltage curve of the final re-averaging technology.

[0020] Figure 4 4 is a schematic diagram of a principle circuit of a successive approximation analog-to-digital converter with mismatch calibration according to an embodiment of the present invention.

[0021] Figure 5 4 is a schematic diagram of a differential capacitor array of a successive approximation analog-to-digital converter with mismatch calibration according to an embodiment of the present invention.

[0022] Figure 6 It is a schematic diagram of the startup items and redundant bits of the residual voltage control strategy.

[0023] Figure 7 This is a schematic diagram comparing the simulation results of the background noise level with and without the redundant bit-based dithering technology.

[0024] Figure 8 Schematic diagram of residual voltage curve using residual voltage control strategy.

[0025] Fig. 9 Schematic diagram of an automatic balancing capacitor array and a successive approximation capacitor array of a successive approximation analog-to-digital converter with mismatch calibration according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0027] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0028] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0029] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0030] In order to better understand the successive approximation analog-to-digital converter with mismatch calibration provided by the present invention, firstly, Figures 1 to 3 The existing successive approximation analog-to-digital converter is introduced. Figure 1 It is a schematic diagram of the overall structure of the existing successive approximation analog-to-digital converter. Figure 2 This is a schematic diagram of the principle circuit of a 5-bit successive approximation analog-to-digital converter using a binary weighted capacitor array. Figure 3 It is a schematic diagram of the residual voltage curve of the final re-averaging technology.

[0031] See also Figure 1 A typical successive approximation analog-to-digital converter usually consists of four parts: a sample-and-hold circuit, which is used to sample the analog signal and obtain the sampled signal; a comparator module, which is used to compare the signal input by the differential capacitor array and output the comparison result; an internal reference digital-to-analog converter DAC, which is used to provide an analog voltage corresponding to the output digital code according to the comparison result of the analog voltage comparator; and a successive approximation register logic circuit, which is used to provide an input voltage V according to the comparison result. in The digital code of .

[0032] The internal reference DAC in a successive approximation DAC is usually implemented using a binary weighted capacitor array. Figure 2 , taking a 5-bit successive approximation analog-to-digital converter as an example. The distribution of the 5-bit binary weighted capacitor array is 16C in parallel u ,8C u、4C u 、2C u , C u , C u , where C u is the size of the unit capacitance, the total capacitance C total 32C u In a binary capacitor array, the size of the least significant bit (LSB) capacitor is recorded as the unit capacitance C. u , then the size of the second least significant bit capacitor is 2C u For an N-bit capacitor array, the size of the most significant bit (MSB) capacitor is 2 N-1 ×C u Specific to Figure 2 The 5-bit binary weighted capacitor array shown in the figure has the highest capacitor, the second highest capacitor, the third highest capacitor, the fourth highest capacitor, and the lowest capacitor. The last capacitor is a dummy capacitor, also known as an adjustment capacitor, which only participates in the sampling process. The binary weighted capacitor array has an upper and a lower plate, where the plate connected to the comparator is the upper plate and the other end is the lower plate.

[0033] Figure 2 The working process of the 5-bit successive approximation analog-to-digital converter shown in the figure is described in chronological order as follows, which is divided into two time sequences: (1) In the sampling phase, the lower plate of the sampling capacitor is connected to the input signal V in The top plate is connected to V com After sampling is completed, the upper plate of the sampling capacitor is disconnected from V com At this time, the charge stored on the upper plate of the sampling capacitor is Q out =C total ×(V com -V in ). After the sampling is completed, the successive approximation analog-to-digital converter enters the hold phase, at which time the lower plates of all capacitors are connected to Gnd. After the lower plates of all sampling capacitors are connected to Gnd, the output voltage V out =V com -V in (2) During the successive approximation process, the charge stored on the upper plate is redistributed as the voltage on the lower plate changes. In the first decision cycle, the lower plate of the highest-order capacitor of the differential capacitor array is connected to V ref , the remaining capacitor lower plate is connected to Gnd. At this time, according to the charge conservation on the capacitor upper plate, we can get:

[0034]

[0035] Simplifying, we get:

[0036]

[0037] Then we can get:

[0038]

[0039] In the formula, , N is between 5 and 1, is the conversion result.

[0040] The binary weighted capacitor array inside the successive approximation analog-to-digital converter is prone to mismatch during manufacturing, which will cause the nonlinearity of the successive approximation analog-to-digital converter. The emergence of the last-bit re-averaging technology provides a new way to improve the noise in the conversion stage. By adding a set of carefully designed redundant weights at the end of the differential capacitor array, the average output result is played through repeated judgment, ultimately achieving the goal of reducing the impact of conversion noise. See Figure 3 Ideally, during the conversion process, the residual voltage will continue to decrease as the conversion progresses until the residual voltage reaches a minimum value of ±1LSB at the last bit. In practice, due to noise ( Figure 3 Due to the influence of medium-Gaussian conversion noise, the residual voltage cannot reach the minimum value of ±1LSB when the conversion reaches the last bit. After adding the re-averaging bit, the residual voltage will fluctuate around zero. At this time, the sum of all the P-end and N-end weights set to Vref is taken as normal bits, and the result obtained by subtracting them will be closer to the correct result without noise influence. During the design process, it was found that the main causes of judgment errors are clock jitter, differential capacitor array output result establishment errors, noise and other non-ideal factors. In order to repair the judgment errors caused by the above reasons, adding appropriate redundant bits can optimize the fault tolerance of the conversion process, but redundant bits still cannot completely solve all set errors caused by judgment errors. For example, after the judgment error causes the residual voltage to rise, even if all the remaining positions are set to a state that makes the residual voltage drop, the residual voltage still cannot return to the correct state.

[0041] In view of this, an embodiment of the present invention provides a successive approximation analog-to-digital converter with mismatch calibration, so that the capacitor array can be effectively calibrated within the input voltage range. The overall structure of the successive approximation analog-to-digital converter with mismatch calibration proposed by the present invention is still as follows: Figure 1 As shown, but the implementation circuit is different. Figure 4 4 is a schematic diagram of a principle circuit of a successive approximation analog-to-digital converter with mismatch calibration according to an embodiment of the present invention.

[0042] like Figure 4As shown, the successive approximation analog-to-digital converter with mismatch calibration can be composed of a sampling and holding capacitor digital-to-analog converter (S / H CDAC), a comparator, a successive approximation logic circuit, a calibration logic circuit and a main control logic. The S / H CDAC can include a sampling and holding circuit and a differential capacitor array. The analog part and the digital part of the successive approximation analog-to-digital converter can work as a whole. The sampling and holding circuit is used to sample the analog signal to obtain an analog input voltage. The differential capacitor array includes a successive approximation capacitor array, an automatic balancing capacitor array and a calibration capacitor array, which will be further described in detail later. The input ends of the comparator module are respectively connected to the sampling and holding circuit and the differential capacitor array, and the comparator module is used to compare the analog output signal with the analog input signal and output the comparison result. The successive approximation logic circuit is connected to the output end of the comparator and the differential capacitor array, and the successive approximation logic circuit is used to control and manage the state of the capacitors in the successive approximation capacitor array according to the comparison result, so that the analog output voltage successively approaches the analog input voltage. The calibration logic circuit is connected to the output terminal of the comparator and the differential capacitor array, and can be used to control and manage the automatic balancing capacitor array and the calibration capacitor array.

[0043] Please continue reading Figure 4 , the successive approximation analog-to-digital converter can also generally include an adjustable clock generation module, a weight memory, a user interaction logic circuit, etc., to improve performance, flexibility, and ease of use, but the present invention is not limited thereto. The adjustable clock generation module can be used to provide each circuit module with a clock signal with a cycle and duty cycle suitable for operation. The successive approximation logic circuit, the calibration logic circuit, and the serial peripheral interface circuit can be integrated in the digital logic circuit module. The user interaction logic circuit can allow a microcontroller or other host device to read the conversion result through the serial peripheral interface, and can also allow the configuration of the ADC's operating parameters.

[0044] As an example, the embodiment of the present invention can use three power supplies. The reference voltage Vref is from 2.5 to 5V. The logic circuit is powered by 2.5 V (power supply voltage Vdd). The serial peripheral interface power supply voltage is 1.8 ~ 3.3 V. In this embodiment, in order to reduce the interaction between the digital module and the analog module, GND, Vref and Vdd are strictly separated. This variable can provide a more flexible signal input range. Similarly, this voltage variable is convenient for users to select the operating voltage of the digital logic without the need for a complex level conversion structure. The digital logic, SAR logic and control logic of the internal and analog parts are powered by Vdd (for example, 2.5 V). As a result, these circuits can be designed to have the smallest area. And all use digital modules, and the performance does not affect the conversion accuracy. In terms of utilization, three different power supplies can be selected to obtain the best performance, or only a 2.5 V power supply can be used to simply drive this design. When the ADC is powered on, the calibration process is automatically started and the results are saved in the weight memory. The weight value in the weight memory is then used to correctly convert the input signal, and the final converted digital value is sent to the downstream device through the serial peripheral interface.

[0045] Figure 5 4 is a schematic diagram of a differential capacitor array of a successive approximation analog-to-digital converter with mismatch calibration according to an embodiment of the present invention.

[0046] like Figure 5 As shown, the differential capacitor array may include a successive approximation capacitor array, an automatic balancing capacitor array, and a calibration capacitor array. The successive approximation capacitor array may include two completely symmetrical sub-circuits of the P end and the N end. The successive approximation capacitor array may include redundant bits capacitors, which are used to calibrate the digital deviation in the quantization process. The automatic balancing capacitor array and the calibration capacitor array are respectively connected to the P end and the N end of the successive approximation capacitor array. The automatic balancing capacitor array is used to balance the common mode voltage of the P end and the N end, and the calibration capacitor array is used to calibrate the digital weight of the successive approximation capacitor array.

[0047] In some embodiments, the successive approximation bit capacitor array may include a low-segment capacitor array, a middle-segment capacitor array, and a high-segment capacitor array. The low-segment capacitor array generally includes a smaller capacitance value for representing a smaller analog voltage change. The middle-segment capacitor array is located between the low segment and the high segment, and the introduction of the middle-segment capacitor array can further subdivide the steps of the analog voltage and improve the resolution and accuracy of the ADC. The high-segment capacitor array may include a larger capacitance value for representing a larger analog voltage change. It is understandable that the two symmetrical sub-paths of the successive approximation bit capacitor array include low-segment, middle-segment, and high-segment capacitor arrays. Through this segmented design, the successive approximation analog-to-digital converter can more quickly establish the charge state of the ADC capacitor array, especially in the initial high-bit estimation stage, which can reduce the number of iterations required, thereby improving the overall conversion speed and efficiency. In addition, the segmented capacitor array can also help reduce power consumption, such as only activating the capacitor unit of the corresponding segment in each conversion cycle, rather than the entire capacitor array.

[0048] The low-segment capacitor array, the middle-segment capacitor array, and the high-segment capacitor array are composed of capacitor arrays with non-binary coded integer weights. Non-binary coded integer weights mean that the weight of each capacitor is not a simple power of 2, but an integer selected according to a specific algorithm or optimization goal. In this way, a more flexible quantization ladder can be provided than traditional binary weights, which helps to reduce quantization errors and improve ADC performance.

[0049] In this embodiment, sampling can be performed through the lower plate of the high-segment capacitor array to ensure the accuracy and stability of the sampling process. In some embodiments, the weight of any non-lowest-order weight capacitor in the high-segment capacitor array is less than the sum of the weights of all weight capacitors that are lower than any non-lowest-order weight capacitor. That is to say, in the high-segment capacitor, the weight of any non-lowest-order capacitor must be less than the sum of the weights of all capacitors below it. In this way, when performing analog-to-digital conversion, even if there is a slight deviation in a certain capacitance value, it will not lead to serious errors in the conversion result. This is because if the weight of a capacitor is too large, its contribution to the output will be disproportionate, which may lead to significant deviations in the conversion result.

[0050] In some embodiments, the lower part of the low-segment capacitor array may include a sub-minimum unit capacitor array. The sub-minimum unit capacitor array typically includes a capacitance value that is smaller than the smallest capacitor in the low-segment capacitor array. The addition of these capacitors allows for finer adjustments during the quantization process of the ADC, thereby reducing errors caused by factors such as capacitor mismatch and switch parasitics. Specifically, in the initial stage of successive approximation, the high-segment and mid-segment capacitor arrays can first be used for coarse quantization to determine the approximate range of the analog input signal. As the approximation process deepens, the low-segment capacitor array is gradually used for fine quantization. At this point, the sub-minimum unit capacitor array begins to play a role, and the quantization results of the low-segment capacitor array are fine-tuned by the tiny capacitance values ​​thereon. By controlling the switches of the sub-minimum unit capacitor array, a fine division of the quantization steps can be achieved, thereby improving the resolution and accuracy of the ADC.

[0051] like Figure 5 As shown, as an example, the high-segment capacitor array may include the 9th to 15th capacitors, the middle-segment capacitor array may include the 5th to 8th capacitors, and the low-segment capacitor array may include the 0th to 4th capacitors, wherein the 0th and 0rth capacitors are sub-minimum unit capacitor arrays.

[0052] In some embodiments, redundant capacitors may be added to each capacitor array segment, so that the low-segment capacitor array, the middle-segment capacitor array, and the high-segment capacitor array are all composed of capacitor arrays with non-binary coded integer weights. Figure 5 As shown, the 9rth and 11rth redundant position capacitors can be added to the high-segment capacitor array, the 7rth and 8rth redundant position capacitors can be added to the middle-segment capacitor array, and the 1rth and 3rth redundant position capacitors can be added to the low-segment capacitor array. It should be emphasized that the present invention does not limit the specific position and number of redundant position capacitors in each segment of the capacitor array, and those skilled in the art can reasonably set them according to specific circumstances. By increasing the number of redundant capacitor bits, the impact of non-ideal factors such as noise imbalance on the analog-to-digital conversion results can be minimized.

[0053] Please continue reading Figure 5 As an example, the differential capacitor array may also include a plurality of capacitors C b1 ~C b6 and a plurality of switches S1 to S12, but the present invention is not limited thereto. b1 ~C b4 It is the bridge capacitor between the high-segment, middle-segment, and low-segment capacitor arrays. C b5 and C b6It is a weight multiplication capacitor used to adjust the weight externally when the differential capacitor array has excessive mismatch. Switches S1~S4 and switches S5~S8 are boost switches between the differential capacitor array and the comparator. These switches can be composed of a boost switch connected to the comparator and an NMOS (N-channel Metal-Oxide-Semiconductor) to disconnect the differential capacitor array from the comparator during high-level suspension and comparator automatic zeroing, reset and other operations. Switches S9~S12 and S13~S16 are voltage-controlled oscillator switches used to generate voltage Vcom when the voltage Vdd reference is sampled. The auto-balance capacitor array (Auto-balance CDAC) and calibration capacitor array (calibration capacitance array) circuits are used to implement on-chip digital weight calibration.

[0054] In some embodiments, the successive approximation analog-to-digital converter further includes a disturbance signal injection module, and the calibration logic circuit further includes a pure analog jitter circuit implemented based on a residual voltage control strategy, wherein the disturbance signal injection module is used to inject a pseudo-random disturbance signal into the redundant bit capacitor through the pure analog jitter circuit. For example, a pseudo-random signal can be a tiny voltage or current change, whose amplitude and polarity are random but controllable. By introducing this randomness, the fixed pattern error that may exist in the quantization process can be broken, thereby improving the linearity of the ADC and reducing the quantization noise.

[0055] See also Figure 6 and Figure 7 , Figure 6 It is a schematic diagram of the startup items and redundant bits of the residual voltage control strategy. Figure 7 This is a schematic diagram comparing the simulation results of the background noise level with and without the redundant bit-based dithering technology.

[0056] The present invention adds RS (redundant) bits to redundant bits to reduce the situation where the comparator makes repeated decisions and cannot distinguish input voltages. The startup state after adding the RS bit can be as follows Figure 6 As shown. In the present invention, the second RS bit, the third RS bit and the fourth RS bit are used as dithering bits. The pseudo-random sequence drives the dithering bits to affect the transfer function of the circuit system. During the conversion process, when the previous RS dithering position is used as the comparison result, the dithering position is set to the RS bit value, and the transformation result is affected by the RS dithering bit. The RS dithering bit can be used like a normal bit in the entire conversion process, and the digital result does not need to subtract the weight of the dithering bit. In the simulation, non-ideal factors such as noise and comparator offset can be used. From Figure 7It can be seen that the noise floor of the SAR ADC with RS-based (redundant bit based) jitter is around 90db, and the noise floor of the SAR ADC without RS-based jitter is around 114db. It can be seen that the noise floor of the SAR ADC with RS-based jitter is better than that without RS-based jitter.

[0057] Figure 8 Schematic diagram of residual voltage curve using residual voltage control strategy.

[0058] like Figure 8 As shown, four residual voltage curves of the same input signal of the present invention are listed, namely, the error residual curve 1, the error residual curve 2, the ideal residual curve and the last-bit re-averaged residual curve. The error residual curve 1 (error resident curve) is a non-ideal situation using the residual voltage control strategy, and the error occurs at the 13th bit. The error residual curve 2 is a situation of misjudgment due to insufficient residual voltage, and the error occurs at the 9th bit. After point P1, due to the wrong judgment at the 13th bit, the error residual curve 1 has an erroneous rise. When the judgment of the 12rth bit ends, the RS bit helps the error residual curve 1 drop to the ideal residual curve. This additional drop is the pre-offset voltage of the 12th bit. Similarly, after point P2, a similar situation exists. It can be seen that these additional redundant bits help the residual curve return to the correct range close to the ideal residual curve.

[0059] See also Figure 4 , Figure 5 In some embodiments, the calibration logic circuit may include a self-measurement calibration circuit for controlling and managing the calibration capacitor array. The self-measurement calibration circuit uses a specific bit of the differential capacitor array as a base point, measures and calculates the weights of the P terminal and the N terminal respectively through the calibration capacitor array, and uses half of the difference between the weights of the P terminal and the N terminal as the calibrated weight. Since the P terminal and the N terminal should have the same weight (or capacitance value) under ideal conditions, there may be differences between them due to factors such as manufacturing errors. In order to eliminate this difference, half of the difference between the weights of the P terminal and the N terminal is used as the calibrated weight, which can make the weights of the calibrated P terminal and the N terminal equal, thereby improving the measurement accuracy and stability of the circuit.

[0060] As an example, in Figure 5In the differential capacitor array shown, the self-measurement calibration circuit can start from the 5th bit of the differential capacitor array, that is, take the 5th bit as the base point. First, the 5th bit of the P terminal is used as the reference voltage Vref, and then the weights of the 4th bit to the last bit of the P terminal and the N terminal are used to measure the digital weight of the 5th bit of the P terminal. After the digital weight measurement of the 5th bit of the P terminal is completed, the 5th bit of the N terminal is used as the reference voltage Vref to complete the measurement. The weight of the P terminal is:

[0061]

[0062] In the formula, is the i-th bit weight of the P terminal, Dpj is the low-bit quantized digital signal, Wj is the low-bit weight, and os is the error size.

[0063] The N-terminal weight is:

[0064]

[0065] In the formula, is the i-th bit weight of the P terminal, Dpj is the low-bit quantized digital signal, Wj is the low-bit weight, and os is the error size.

[0066] The final weights after calibration are:

[0067]

[0068] In the formula, is the final weight. From the above formula, we can see that by subtracting the weight at the P end from the weight at the N end, the error os can be eliminated, thereby improving the measurement accuracy.

[0069] Fig. 9 Schematic diagram of an automatic balancing capacitor array and a successive approximation capacitor array of a successive approximation analog-to-digital converter with mismatch calibration according to an embodiment of the present invention.

[0070] like Fig. 9 As shown, the automatic balancing capacitor array is connected to the middle capacitor array, and the equivalent of 6 C u Due to the limitation of chip area and power consumption and the requirement of automatic balancing voltage range, 6C is added in this embodiment. u The equivalent capacitance array is only 6C at most. u , when not needed, it can be connected to less than 6C u In some other possible embodiments, by setting the number and size of capacitors in the automatic balancing capacitor array, the equivalent C u The quantity of can also be other values. That is, the equivalent C of other quantities u It should also be included in the protection scope of the present invention.

[0071] Before the successive approximation analog-to-digital converter starts sampling, it can be checked whether the common-mode voltages at both ends of P and N are equal. If they are not equal, the size of the automatic balancing capacitor connected to the N end is changed to change Vcom-n to make it equal to Vcom-p. Figure 5 In the embodiment shown, the automatic balancing capacitor array can correct the Vcom-p (i.e. Figure 5 Voutp) and Vcom-n (i.e. Figure 5 The deviation voltage of Voutn in the circuit reaches 8mV, Vcom-p is the common mode voltage of the P terminal, and Vcom-n is the common mode voltage of the N terminal.

[0072] In some embodiments, the automatic balancing capacitor array may include a low-segment balancing capacitor array and a mid-segment balancing capacitor array. The low-segment balancing capacitor array has the same weight configuration as the low-segment capacitor array, and the mid-segment balancing capacitor array has a weight configuration of 2:1:1. Since the offset voltage across P and N is usually not very large, 2:1:1 can make the balancing accuracy greater. Figure 5 As shown, the capacitor C b3 The last is the low section of the auto-balancing capacitor array, which has the same weight configuration as the low section of the successive approximation capacitor array to ensure the highest accuracy of the auto-balancing effect. During the auto-balancing process, the successive approximation loop works twenty times longer than normal operation to minimize decision and settling errors. The auto-balancing strategy adjusts the mismatch voltage between the P and N terminals of the differential capacitor array to less than 1 LSB before the calibration process.

[0073] In some embodiments, the operation mode of the successive approximation analog-to-digital converter with mismatch calibration may include a calibration mode and a normal operating mode. The calibration mode may be completed before the normal operating mode begins. The calibration mode may include a common mode voltage automatic balancing phase, a self-measurement calibration phase, and a jitter injection phase. The normal operating mode may include a sampling phase, a holding phase, and a quantization phase.

[0074] The various stages of the calibration mode have been described in the previous article, so I will not repeat them here. In the sampling stage, the common-mode voltage can be connected to the upper plate of the high-segment capacitor array and the lower plate of the low-segment capacitor array, and the sampling signal can be connected to the lower plate of the high-segment capacitor array; in the holding stage, the upper plate of the high-segment capacitor array and the common-mode voltage can be disconnected, and the lower plates of all weight capacitors can be connected to the common-mode voltage; in the quantization stage, the lower plates of all weight capacitors can be connected to the reference voltage or ground.

[0075] In summary, the present invention provides a successive approximation analog-to-digital converter with mismatch calibration. A differential capacitor array is used, including a low-segment capacitor array, a middle-segment capacitor array, a high-segment capacitor array and a calibration capacitor array, wherein the low-segment, middle-segment and high-segment capacitor arrays are composed of capacitor arrays with non-binary coded integer weights, the middle-segment capacitor array includes an automatic balancing capacitor array and an approximation capacitor array, each segment capacitor array includes redundant bit capacitors, and a sub-minimum unit capacitor array is added to the lower part of the low-segment capacitor array to improve the accuracy of the calibration digital bit weight. The calibration logic circuit includes a pure analog jitter circuit implemented based on a residual voltage control strategy, a self-measurement calibration circuit and an automatic balancing circuit. The present invention improves the redundancy range and calibration accuracy by improving the binary weighted capacitor array. At the same time, the calibration logic is adjusted to achieve the effect of suppressing the circuit noise error.

[0076] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A successive approximation analog-to-digital converter with mismatch calibration, characterized in that: include: A sample-and-hold circuit is used to sample the analog signal to obtain an analog input voltage; A differential capacitor array, comprising a successive approximation capacitor array, an automatic balancing capacitor array and a calibration capacitor array, wherein the successive approximation capacitor array is used to quantize the analog input voltage to generate an analog output voltage, the successive approximation capacitor array comprises redundant capacitors, the redundant capacitors are used to calibrate digital deviations in a quantization process, the automatic balancing capacitor array and the calibration capacitor array are respectively connected to a P terminal and an N terminal of the successive approximation capacitor array, the automatic balancing capacitor array is used to balance the common mode voltage of the P terminal and the N terminal, and the calibration capacitor array is used to calibrate the digital weight of the successive approximation capacitor array; A comparator module, wherein the input ends of the comparator module are respectively connected to the sample-and-hold circuit and the differential capacitor array, and the comparator module is used to compare the analog output signal with the analog input signal and output a comparison result; A successive approximation logic circuit is connected to the output terminal of the comparator and the differential capacitor array, and the successive approximation logic circuit is used to control and manage the state of the capacitors in the successive approximation capacitor array according to the comparison result, so that the analog output voltage gradually approaches the analog input voltage; A calibration logic circuit is connected to the output end of the comparator and the differential capacitor array, and the calibration logic circuit is used to control and manage the automatic balancing capacitor array and the calibration capacitor array.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that: The successive approximation capacitor array includes a low-segment capacitor array, a middle-segment capacitor array and a high-segment capacitor array, wherein the low-segment capacitor array, the middle-segment capacitor array and the high-segment capacitor array are composed of capacitor arrays with non-binary coded integer weights; The sample-and-hold circuit performs sampling via the lower plate of the high-segment capacitor array.

3. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The calibration logic circuit includes a self-measurement calibration circuit for controlling and managing the calibration capacitor array; The self-measurement calibration circuit uses a specific position of the differential capacitor array as a base point, measures and calculates the weights of the P terminal and the N terminal respectively through the calibration capacitor array, and uses half of the difference between the weights of the P terminal and the N terminal as the calibrated weight.

4. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The automatic balancing capacitor array is connected to the P terminal and the N terminal of the middle capacitor array; The calibration logic circuit includes an automatic balancing circuit for controlling and managing the automatic balancing capacitor array, wherein the automatic balancing circuit makes the automatic balancing capacitor array equivalent to adding a capacitance of at most 6 capacitance units in the middle capacitor array.

5. The successive approximation analog-to-digital converter according to claim 4, characterized in that: The automatic balancing capacitor array includes a low-segment balancing capacitor array and a middle-segment balancing capacitor array, the low-segment balancing capacitor array has the same weight configuration as the low-segment capacitor array, and the middle-segment balancing capacitor array has a weight configuration of 2:1:1; The automatic balancing circuit controls the weight of the capacitor of the automatic balancing capacitor array connected to the P terminal or the N terminal so that the deviation value of the common mode voltage of the P terminal and the N terminal is within a preset difference.

6. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The low-segment capacitor array, the middle-segment capacitor array and the high-segment capacitor array all include the redundant bit capacitors.

7. The successive approximation analog-to-digital converter according to any one of claims 1 or 6, characterized in that: The successive approximation analog-to-digital converter also includes a disturbance signal injection module, and the calibration logic circuit also includes a pure analog dithering circuit implemented based on a residual voltage control strategy, wherein the disturbance signal injection module is used to inject a pseudo-random disturbance signal into the redundant bit capacitor through the pure analog dithering circuit.

8. The successive approximation analog-to-digital converter according to claim 7, characterized in that: The operation mode of the successive approximation analog-to-digital converter includes a calibration mode and a normal working mode, wherein the calibration mode is completed before the start of the normal working mode, wherein the calibration mode includes a common-mode voltage automatic balancing stage, a self-measurement calibration stage and a jitter injection stage, and the normal working mode includes a sampling stage, a holding stage and a quantization stage.

9. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The weight of any non-lowest-order weighted capacitor in the high-segment capacitor array is less than the sum of the weights of all weighted capacitors at lower orders than the any non-lowest-order weighted capacitor.

10. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The lower portion of the low-segment capacitor array includes a sub-minimum unit capacitor array for improving the accuracy of calibrating digital bit weights.

Images