Digital energy adapter, DESS system and processing method thereof

Abstract

The invention provides a digital energy adapter, a DESS system and a processing method of the DESS system. The adapter comprises an adapter CPU and an adapter FPGA. One end of the adapter CPU is connected with the adapter FPGA, and the other end of the adapter CPU is in two-way communication connection with an upper cloud end or a host through a network. The adapter FPGA comprises a data cache region, an information flow control module, an analog quantity control module and an optical fiber communication module; and the adapter FPGA is connected with the digital energy switch through an optical fiber. The adapter FPGA is respectively connected with the energy assembly and the energy storage converter PCS through the DC input and output unit, and controls the input and output of energy. According to the digital energy adapter, the DESS system and the processing method of the DESS system, the communication speed and the real-time performance of the digital energy adapter are improved, the flexibility of the digital energy adapter for dealing with abnormal conditions and the accuracy of monitoring the system are enhanced, and the task load borne by a CPU (Central Processing Unit) can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of encoding, decoding or code conversion in an energy storage system, and in particular to a digital energy adapter, a DESS system and a processing method thereof. Background Art

[0002] At present, as the core device for realizing energy digitization and efficient management, the digital energy exchange system DESS is increasingly widely used in the energy field. However, the digital energy adapter in the existing DESS system has significant shortcomings.

[0003] Since the existing digital energy switch and digital energy adapter use RS485 half-duplex communication, this communication method has many limitations, such as low data transmission rate, which makes it difficult to cope with the growing demand for large-scale data transmission. It performs poorly in terms of real-time performance. Due to the half-duplex characteristics and limited communication rate, there is a significant delay in data update and transmission, which cannot meet the requirements of energy management systems for rapid response and precise control. Most importantly, in the actual application environment of DESS battery dynamic reconstruction, electromagnetic interference is particularly serious, and the electrical signals of RS485 communication are easily interfered, resulting in data transmission errors, which in turn affects the normal operation and decision-making of the system. This not only reduces the performance and efficiency of the DESS system, but also increases the maintenance cost and operation risk of the system, limiting its application and development in more key areas.

[0004] In addition, the communication protocol used by existing digital energy adapters is relatively simple, and it is impossible to effectively detect and correct errors during data transmission. Once data errors occur, the system may make wrong decisions based on the wrong data, thus affecting the normal operation of the entire energy exchange system. Moreover, since there is no verification mechanism, the integrity and accuracy of the data cannot be ensured, which may cause data loss or damage, further reducing the reliability and stability of the system.

[0005] The existing digital energy adapter adopts a single CPU, which leads to limited computing power, poor real-time performance, difficult function expansion, uneven resource utilization, insufficient flexibility, poor power consumption and heat dissipation, and high safety and reliability risks. Specifically, first, in the face of multi-source complex data from electrochemical energy storage systems, photovoltaic systems, photovoltaic storage complementary systems, etc., a single CPU may be difficult to cope with large-scale computing needs, resulting in slow data processing speed and affecting the real-time response of the system. Second, in critical tasks that require rapid decision-making and control in energy systems, such as completing precise adjustment of energy flow in an instant, a single CPU may be delayed due to being busy processing other matters, making it difficult to meet strict real-time requirements. Third, when adding new functions to the digital energy adapter, such as supporting new communication protocols or introducing complex control algorithms, the single CPU architecture usually requires major modifications to the entire hardware and software, which is not only costly but also has a long development cycle. Fourth, when the CPU performs different tasks, it is easy to have unreasonable resource allocation, resulting in inefficiency of some tasks, while other tasks are delayed due to resource waiting. Fifth, the single CPU architecture is subject to significant restrictions in hardware upgrades or functional expansion, and performance improvements or functional additions can often only be achieved by replacing the entire processor, which significantly increases the cost and complexity of system upgrades. Sixth, when running at high load, the power consumption of a single CPU increases significantly, generating a large amount of heat, and placing more stringent requirements on the system's heat dissipation design. Seventh, as the only core, once a single CPU fails, the entire system will be paralyzed, making it difficult to ensure the system's continued operation.

[0006] In addition, since the CPU chips in the digital energy adapters in the prior art use imported chips, they are not only expensive, but also seriously affected by international trade frictions. The uncertainty of the international trade situation makes the supply of imported chips risky. Factors such as changes in trade policies, tariff adjustments, and supply chain disruptions may make it difficult and unstable to obtain imported CPU chips. This will not only affect the production progress of the product, but may also increase production costs. Once the supply of imported chips is cut off, it will directly affect the production and operation of the company, and even threaten the survival of the company. Therefore, it is of great significance to study how to improve the communication speed and real-time performance of the digital energy adapter, enhance the flexibility of the digital energy adapter to deal with abnormal situations, and the accuracy of system monitoring. Summary of the invention

[0007] In view of this, the present invention aims to propose a digital energy adapter, a DESS system and a processing method thereof, so as to solve the problems existing in the prior art that a single CPU has a weak monitoring force on the entire energy storage system, has a poor flexibility in the processing method after an abnormality occurs in the system, and the use of a single CPU is prone to limited computing power, poor real-time performance, difficult function expansion, uneven resource utilization, insufficient flexibility, poor power consumption and heat dissipation, and high safety and reliability risks. In this way, the communication speed and real-time performance of the digital energy adapter are improved, the flexibility of the digital energy adapter to deal with abnormal situations, and the accuracy of system monitoring are enhanced. The structure of the digital energy adapter is optimized, the anti-interference ability of the adapter is enhanced, the accuracy and reliability of data transmission are ensured, and the perfection of information statistics is improved. It can also overcome the limitations of the single CPU setting method and reduce the amount of tasks that the CPU needs to undertake. Through the setting of the processing method, the data processing efficiency and the stability of the system can also be improved.

[0008] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0009] The present invention relates to a digital energy adapter, a DESS system and a processing method thereof, wherein the digital energy adapter comprises an adapter CPU and an adapter FPGA. One end of the adapter CPU is connected to the adapter FPGA, and the other end of the adapter CPU is bidirectionally connected to an upper cloud or a host through a network. The adapter FPGA comprises a data cache area, an information flow control module, an analog quantity control module, and an optical fiber communication module; the adapter FPGA is connected to a digital energy switch through an optical fiber; the adapter FPGA is connected to an energy component and an energy storage converter PCS through a DC input and output unit to control the input and output of energy.

[0010] Furthermore, the data buffer area includes a CPU data buffer area, a switch data buffer area, and an analog data buffer area.

[0011] Furthermore, one end of the information flow control module and the analog quantity control module are connected to the adapter CPU through the CPU data buffer area, and the other end of the information flow control module and the analog quantity control module communicate with the switch data buffer area and the analog quantity data buffer area respectively. The switch data buffer area is connected to the digital energy switch through the optical fiber communication module, and the analog quantity data buffer area communicates with the internal sensor of the adapter through the analog quantity acquisition and processing module.

[0012] Furthermore, an AD converter is provided between the analog quantity acquisition and processing module and the sensor.

[0013] Furthermore, the adapter FPGA also includes an analysis and processing module and an energy control unit. The analysis and processing module communicates bidirectionally with the information flow control module and the analog quantity control module respectively, and the analysis and processing module communicates bidirectionally with the DC input and output unit through the energy control unit.

[0014] Furthermore, the adapter CPU includes a recording function for recording and analyzing historical data and operating conditions in detail, allowing users to view multiple key information within a week and provide a data basis for the system.

[0015] Furthermore, the adapter FPGA also includes a fan control unit. One end of the fan control unit is bidirectionally connected to the analysis and processing module, and the other end of the fan control unit is connected to the fan. The fan is arranged inside the adapter.

[0016] Furthermore, the adapter FPGA also includes an abnormal feedback module. One end of the abnormal feedback module communicates bidirectionally with the information flow control module and the analysis and processing module respectively, and the other end of the abnormal feedback module communicates bidirectionally with the adapter CPU.

[0017] A DESS system includes a digital energy adapter as described above. It includes a digital energy hub and a digital energy network card. The digital energy hub is connected to a digital energy switch and a digital energy network card respectively through Ethernet, and the digital energy switch and the digital energy adapter are connected by optical fiber communication. The digital energy network card is connected to energy components one by one. The DC side of the digital energy network card and the energy storage converter PCS is connected to the positive and negative poles of the digital energy adapter respectively.

[0018] A processing method for a digital energy adapter, the method is applied to the digital energy adapter, the method comprises the following steps:

[0019] Step 1: Data acquisition and preprocessing by adapter FPGA: The analog quantity from the system is acquired in real time through the parallel processing capability of adapter FPGA; and preliminary preprocessing operations are performed on the acquired data according to preset algorithms and rules;

[0020] Step 2: The adapter FPGA performs data caching and processing;

[0021] Step 3: CPU processing and decision-making: After the adapter CPU obtains data from the CPU data buffer, it performs in-depth calculations and analysis on the currently acquired data; and uses the required algorithms and models to generate corresponding control instructions and decision results;

[0022] Step 4: Instruction transmission and execution: The adapter CPU temporarily stores the generated control instructions and processing results in the CPU data buffer area, and transmits them to the adapter FPGA through the data address bus; after receiving the instructions, the adapter FPGA executes the corresponding operation;

[0023] Step 5: Exception handling and feedback: Through the setting of the dual interrupt mechanism in the system, the adapter FPGA and the adapter CPU can send interrupt requests to each other and perform exception handling and feedback.

[0024] Furthermore, in step one, the analog quantity includes any one or more analog quantity data of current, voltage, and temperature.

[0025] Compared with the prior art, the digital energy adapter, optical fiber communication system and processing method thereof described in the present invention have the following beneficial effects:

[0026] Through the setting of the adapter, the communication speed and real-time performance of the digital energy adapter are improved, the flexibility of the digital energy adapter in dealing with abnormal situations and the accuracy of system monitoring are enhanced, the structure of the digital energy adapter is optimized, the anti-interference ability of the adapter is enhanced, the accuracy and reliability of data transmission are ensured, and the perfection of information statistics is improved. It can also overcome the limitations of the single CPU setting method and reduce the amount of tasks that the CPU needs to undertake. It is then beneficial to improve the computing power, real-time performance, functional scalability, resource utilization efficiency, flexibility, heat dissipation effect, security and reliability of the system. It can also reduce dependence on imported CPU chips and ensure the stability and autonomous controllability of chip supply. By setting the processing method, optimizing the communication protocol, and introducing the verification and error correction mechanism, it can also improve the data processing efficiency and system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which constitute part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations of the present invention.

[0028] In the figure:

[0029] Figure 1 It is the overall structure diagram of the DESS system;

[0030] Figure 2 A schematic diagram of the circuit connection between the digital energy network card and the energy components in the communication system;

[0031] Figure 3 This is a schematic diagram of the internal structure of the digital energy adapter;

[0032] Figure 4 The figure is a flowchart diagram of a processing method of a digital energy adapter. DETAILED DESCRIPTION

[0033] The inventive concepts of the present disclosure will be described below using terms commonly used by those skilled in the art to convey the essence of their work to other persons skilled in the art. However, these inventive concepts can be embodied in many different forms and should not be considered limited to the embodiments described herein.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0036] A DESS system includes a digital energy adapter as described above. The DESS system is a soft-defined dynamic topology energy exchange system. The system includes a digital energy hub and a digital energy network card. The digital energy hub is connected to a digital energy switch and a digital energy network card respectively through Ethernet. The digital energy switch and the digital energy adapter are connected through optical fiber communication. The digital energy network card is connected to the energy components one by one (such as Figure 2 As shown in FIG. 1 , the DC side of the digital energy network card and the energy storage converter PCS are connected to the positive and negative electrodes of the digital energy adapter respectively. The AC side of the energy storage converter PCS is connected to the power grid.

[0037] Through the DESS system, combined with power electronics technology, information technology, and a variety of isolation sampling technologies, the energy informatization settings are realized to realize the digital processing of energy systems such as electrochemical energy storage systems, photovoltaic systems, and photovoltaic storage complementary systems, and realize software-defined dynamic topology structures. After the energy components are connected through the DESS system, the system will perform online dynamic digital integration based on the energy status information of each subunit, so as to form an intrinsically safe, highly available, and highly efficient energy system.

[0038] like Figure 1 As shown, N digital energy hubs are provided, where N is a positive integer. Each digital energy hub is communicatively connected to a corresponding digital energy network card. Each digital energy hub is connected to m energy components and digital energy network cards, where m is a positive integer and m≤16.

[0039] like Figure 1As shown, when m=9, each digital energy hub is connected to 9 energy components and digital energy network cards, and the 9 energy components are connected to the 9 digital energy network cards one by one. The 9 digital energy network cards are respectively recorded as NIC0-NIC8. After NIC0, NIC1, and NIC2 are connected in parallel, one end is connected to the digital energy adapter or the digital energy network card connected to the adjacent digital energy hub. After NIC0, NIC1, and NIC2 are connected in parallel, the other end is connected to the end of NIC3, NIC4, and NIC5 connected in parallel. After NIC3, NIC4, and NIC5 are connected in parallel, the other end is connected to the end of NIC6, NIC7, and NIC8 connected in parallel. After NIC6, NIC7, and NIC8 are connected in parallel, the other end is connected to the digital energy network card or digital energy adapter connected to the adjacent digital energy hub.

[0040] Through the cascade setting of digital energy network cards, dynamic topology switching of energy components can be realized. It is also beneficial to timely isolate or handle the energy components through digital energy network cards in the event of failure or abnormality of energy components, so as to realize dynamic energy scheduling of energy components in the system.

[0041] The original digital energy adapter cannot meet the actual work requirements well. In order to solve the problems in the prior art that a single CPU has weak monitoring power over the entire energy storage system, has poor flexibility in handling abnormalities in the system, and that the use of a single CPU easily leads to limited computing power, poor real-time performance, difficult function expansion, uneven resource utilization, insufficient flexibility, poor power consumption and heat dissipation, and high safety and reliability risks; this embodiment proposes a digital energy adapter.

[0042] like Figure 3 As shown, the digital energy adapter includes an adapter CPU and an adapter FPGA. One end of the adapter CPU is connected to the adapter FPGA, and the other end of the adapter CPU is connected to the upper cloud or host through a network in a two-way communication. The adapter FPGA includes a data cache area, an information flow control module, an analog quantity control module, and an optical fiber communication module. The adapter FPGA is connected to the digital energy switch through an optical fiber; the adapter FPGA is connected to the energy component and the energy storage converter PCS through a DC input and output unit to control the input and output of energy. A full-duplex optical fiber communication connection is used between the optical fiber communication module and the digital energy switch. In this embodiment, the host is a PC.

[0043] In this embodiment, the adapter CPU includes a recording and broadcasting function, and the setting of the recording and broadcasting function is implemented by the adapter CPU, which is used to record and analyze historical data and operating conditions in detail, so that users can view multiple key information within a week, providing a solid data foundation for accurate monitoring, performance evaluation, fault diagnosis and optimization and improvement of the system. The adapter CPU uses Nanjing Qinheng's CH32F103 CPU chip, and the adapter FPGA uses the domestic Anlu EG4D20EG FPGA to ensure hardware performance and reliability and reduce dependence on imported chips. The adapter FPGA is connected to the adapter CPU through the data address bus to achieve efficient collaborative work. The data width of the data address bus is 16 bits.

[0044] By setting the adapter CPU and adapter FPGA in the adapter, the communication speed and real-time performance of the digital energy adapter can be improved. Enhance the flexibility of the digital energy adapter in dealing with abnormal situations, as well as the accuracy of system monitoring, and optimize the structure of the digital energy adapter. Enhance the anti-interference ability of the adapter, ensure the accuracy and reliability of data transmission, and improve the perfection of information statistics. It can also overcome the limitations of the single CPU setting method and reduce the amount of tasks that the CPU needs to undertake. It is conducive to improving the computing power, real-time performance, functional scalability, resource utilization efficiency, flexibility, heat dissipation effect, security and reliability of the system. It can also reduce the dependence on imported CPU chips and ensure the stability and autonomous controllability of chip supply. In addition, unlike the half-duplex communication method often used in the prior art for transmission, full-duplex optical fiber communication is used in this application, which means that data can be sent and received simultaneously between the digital energy adapter and the digital energy switch, realizing bidirectional high-speed data transmission. Greatly improve the real-time and efficiency of communication. In scenarios with high real-time requirements such as energy management, it can ensure timely transmission and response of data, avoiding delays and blockages in data transmission. And it is conducive to improving the overall operating efficiency of the system. In addition, the real-time nature of full-duplex fiber optic communication enables the system to quickly respond to various changes, thereby improving the communication stability and reliability of the system.

[0045] The functions of the adapter FPGA are described as follows:

[0046] The data cache includes the CPU data cache, the switch data cache, and the analog data cache. One end of the information flow control module and the analog control module are connected to the adapter CPU through the CPU data cache in a two-way communication manner; the other ends of the information flow control module and the analog control module communicate with the switch data cache and the analog data cache respectively. The switch data cache is connected to the digital energy switch through the optical fiber communication module, and the analog data cache communicates with the internal sensor of the adapter through the analog acquisition and processing module. Among them, an AD converter is set between the analog acquisition and processing module and the sensor to realize the conversion of the analog data collected in the sensor into a digital signal that can be recognized by the adapter FPGA.

[0047] By opening up different high-speed cache areas on the adapter FPGA, the digital energy adapter can achieve fast and accurate data storage and interaction under the settings of each cache area, thereby improving the performance and stability of the entire system, better meeting the needs of the DESS system; improving the speed and efficiency of data processing. Among them, the CPU data cache area is used to store data processed by the CPU, so as to achieve a fast response between the CPU and FPGA inside the adapter, and to be able to process various requests within the system in a timely manner, thereby reducing the workload of the adapter CPU inside the adapter, and enabling the adapter FPGA to effectively share the tasks of the adapter CPU. Improve the speed and accuracy of switch data transmission and processing, and reduce the probability of data errors. In addition, the switch data cache area is used to temporarily store data communicated between the digital energy switch and the digital energy adapter.

[0048] Working process of switch data buffer: When the digital energy adapter needs to send data to the digital energy switch, the adapter FPGA will first write the data into the switch data buffer. According to the requirements of the communication protocol and communication coding, the data in the switch data buffer is sent out through the optical fiber communication module. When receiving data from the digital energy switch, the data is first stored in the switch data buffer, and then passed to the adapter FPGA or adapter CPU for processing.

[0049] Analog data buffer working process: The adapter FPGA collects analog data at a high frequency, and the collected data is immediately stored in the analog data acquisition buffer. When the data in the buffer reaches a certain amount or meets specific conditions, the adapter FPGA will transfer the data to the CPU data buffer, or process and analyze it.

[0050] The setting of different buffer areas can help improve the data processing efficiency in the adapter, ensure the integrity and accuracy of the data, and realize fast data interaction. Among them, the switch data buffer area can temporarily store the data interacting with the digital energy switch, avoid the blockage and delay of data transmission, make the sending and receiving of data smoother, thereby improving the communication efficiency. The analog data buffer area can quickly store the collected analog data, reduce the waiting time in the data collection process, and enable the adapter FPGA to continue to collect data without waiting for data processing and transmission. The CPU buffer area provides temporary storage space for data for the adapter CPU. It enables the adapter CPU to quickly obtain and process data, reduces the time to read data from the external memory, and thus improves the processing speed of the adapter CPU. In addition, the cache can temporarily store and buffer the data, reducing the loss and error of data during transmission and processing. Especially when the data volume is large or the transmission speed is unstable, the cache can play the role of data buffering and verification to ensure the integrity and accuracy of the data. Different cache areas provide a bridge for data interaction between the adapter FPGA and the adapter CPU, enabling them to quickly exchange data, work together, and improve the operating efficiency of the entire system.

[0051] The data in the CPU data cache includes any one or more data types of the relevant data transmitted by the digital energy switch and the relevant data transmitted by various sensors inside the digital energy adapter. The relevant data transmitted by the digital energy switch includes any one or more data of the system component status and energy parameters collected by the switch. The relevant data transmitted by the digital energy switch can provide a basis for the adapter CPU to evaluate the input and output of the system; the relevant data transmitted by the upper cloud or host include the upper control instructions and the comprehensive information of the system that needs to be uploaded to the upper layer. After the CPU data cache obtains various analog data from the analog data acquisition cache, the adapter CPU will store it in its own cache and perform in-depth calculations and analysis, including any one or more of statistical analysis based on historical data and formulation of control strategies. The control instructions and processing results generated by the adapter CPU will also be temporarily stored in the cache so that they can be transmitted to the adapter FPGA in time to perform corresponding operations.

[0052] By gathering data from different sources in the CPU data cache, the adapter CPU can perform comprehensive analysis and processing. The adapter can also adjust the system's operating mode according to the upper-level instructions. Through efficient processing and integration of these data, the adapter CPU can make more accurate decisions to ensure the stable and efficient operation of the entire system.

[0053] Preferably, the adapter FPGA also includes an analysis and processing module and an energy control unit. The analysis and processing module and the energy control unit are integrated on the adapter FPGA. The analysis and processing module communicates bidirectionally with the information flow control module and the analog quantity control module respectively. The analysis and processing module communicates bidirectionally with the DC input and output unit through the energy control unit. The adapter FPGA also includes a fan control unit. One end of the fan control unit is bidirectionally connected to the analysis and processing module, and the other end of the fan control unit is connected to the fan, and the fan is arranged inside the adapter. The adapter FPGA also includes an abnormal feedback module. The abnormal feedback module is integrated inside the adapter FPGA. One end of the abnormal feedback module communicates bidirectionally with the information flow control module and the analysis and processing module respectively, and the other end of the abnormal feedback module communicates bidirectionally with the adapter CPU.

[0054] In addition, through the setting of the adapter FPGA, the full-duplex optical fiber communication mode is adopted, which is conducive to improving the real-time data transmission in the system and enhancing the efficiency of data sending and receiving in the system. Different from the half-duplex communication mode of RS485, the data transmission rate is low. It is also conducive to achieving the data transmission rate between the digital energy adapter and the digital energy switch, and enhancing the security of data transmission. In addition, the adapter FPGA has powerful parallel processing capabilities and flexible programmability, and can quickly process large amounts of data and implement complex communication protocols and algorithms. By implementing data encoding, decoding, frame format processing and error checking functions in the adapter FPGA, the speed and efficiency of data processing can be significantly improved, thereby solving the problems of slow communication rate and poor real-time performance. Optical fiber communication uses optical signals to transmit data in optical fibers. Compared with traditional electrical signal communication methods, it has extremely high bandwidth and anti-electromagnetic interference capabilities. By adopting optical fiber communication technology, data can be transmitted quickly and accurately without electromagnetic interference, thereby solving the problem that the existing RS485 communication method is susceptible to interference in complex electromagnetic environments. It is conducive to enhancing the stability of system operation and reducing the cost of the system.

[0055] Regarding the optical fiber communication module in the adapter FPGA, the optical fiber communication module includes a sending processing logic module and a receiving processing logic module. The sending processing logic module and the receiving processing logic module are both integrated inside the optical fiber communication module to provide an optical fiber communication channel for data exchange between the digital energy switch and the digital energy adapter. The sending processing logic module is connected to the optical fiber sending device, and the receiving processing logic module is connected to the optical fiber receiving device. Figure 3 As shown, the optical fiber receiving device (RX) of the adapter is connected to the optical fiber transmitting device (TX) of the digital energy switch via optical fiber communication; the optical fiber transmitting device (TX) of the adapter is connected to the optical fiber receiving device (RX) of the digital energy switch via optical fiber communication.

[0056] The sending processing logic module includes a sending framing processing module, an encoding module, and a parallel-to-serial conversion module. One end of the sending framing processing module is connected to the data buffer area, and is used to fetch data through the data buffer area; the other end of the sending framing processing module is connected to the optical fiber sending device through the encoding module and the parallel-to-serial conversion module in turn, and is used to send data out through the optical fiber sending device. The receiving processing logic module includes a receiving analysis processing module, a decoding module, and a serial-to-parallel conversion module. One end of the optical fiber receiving device is connected to the optical fiber, and the other end of the optical fiber receiving device is connected to the data buffer area through the serial-to-parallel conversion module, the decoding module, and the receiving analysis processing module in turn, and is used to store data in the data buffer area. Among them, the encoding module and the decoding module both adopt the 8B / 10B data encoding method. When sending data, 8B / 10B is used for encoding and then sending the data. This encoding method expands 8-bit data to 10 bits for transmission. The advantage of this is that the redundancy of the data is increased and the anti-interference ability of the signal is improved. In optical fiber communication, the signal may be subject to various interferences, and 8B / 10B encoding can reduce the impact of interference on the data to a certain extent and ensure reliable data transmission. When receiving data, 8B / 10B is used for decoding before receiving the data. The decoding method is to restore 10-bit data to 8 bits. Then, the decoded data is parsed to extract any one or more information of address command, specific data, frame sequence number and CRC check data. By analyzing and processing this information, the digital energy switch can understand the working status of the digital energy adapter and the operation of the system, and make corresponding control and decisions. The optical fiber transmitting device and the optical fiber receiving device use domestic devices FT-1629Z and FT-2529Z respectively. It is used to achieve high-speed and stable data transmission, and improve communication performance and anti-interference ability.

[0057] By selecting the domestic FPGA chip, optical fiber transmitting device and optical fiber receiving device in this embodiment, the system risk caused by the limited supply of foreign chips can be avoided. It can also reduce the chip cost and improve the market competitiveness of the product. And by adopting the setting of the adapter FPGA, the transmission of data in the system can be made more efficient and the delay time in the data transmission process can be reduced. In addition, the data buffer area set by the adapter FPGA can play a key role during the operation of the system. The existence of the data buffer area greatly liberates the burden of the CPU, so that the CPU no longer needs to consume resources to process complex communication protocols. It is beneficial for the CPU to devote more energy and computing power to other important tasks of the system; such as the execution of more complex energy management algorithms, in-depth analysis of system status, and rapid decision-making. This optimized resource allocation method significantly improves the operating efficiency and response speed of the entire system.

[0058] The communication protocol between the digital energy adapter and the digital energy switch adopts the proprietary communication protocol based on the DESS system. The data length of each data frame corresponding to the proprietary communication protocol is 64 bits. The structure of each data frame includes address command information, data segment, frame sequence number and CRC check data. The data in the address command information, data segment, frame sequence number and CRC check data are arranged in sequence to form the data of each data frame. Among them, the data length of the address command information is 16 bits; it is used to indicate the target address and operation type of the data to ensure that the data can be accurately delivered to the destination and perform the corresponding operation. The specific data carries the actual business information, which includes any one or more of energy parameters and equipment status. The data length of the data segment is 32 bits, the data length of the frame sequence number is 8 bits, and the data length of the CRC check data is 8 bits, which is used to check the previous 56 bits of data to ensure the accuracy and integrity of the data. By setting the above data frame format, the accuracy, integrity and orderliness of data transmission can be effectively ensured. Reduce data transmission conflicts and confusion. Ensure that each data frame can be accurately sent, received and processed, providing solid technical support for the refined energy management and intelligent control of the DESS system. The 8-bit frame number starts from 0 and goes to 255 in a cycle, which is used to identify the order of the data frames and ensure the orderly transmission of the data. The last 8-bit CRC check data is the CRC check data of the previous 56-bit data.

[0059] By setting up the DESS system's own communication protocol, effective communication between the digital energy adapter and the digital energy switch can be ensured. This protocol is specifically set up for the characteristics and requirements of the DESS system, and can better meet the communication requirements between various devices in the system. In addition, the fixed frame length of each frame is fixed to 64 bits, which helps to improve the efficiency and stability of data transmission. During the data transmission process, both parties can accurately identify and process each frame of data to avoid transmission errors caused by inconsistent frame lengths. Through the coordination of frame sequence numbers and CRC check data, errors that may occur during data transmission can be effectively detected and corrected, thereby ensuring the accuracy, integrity and orderliness of data transmission. This enables the digital energy adapter to accurately obtain digital energy switch instructions. If the receiver finds that the frame sequence number is discontinuous or the CRC check fails, it can be determined that the data has been lost or damaged, and appropriate measures can be taken for retransmission or error correction.

[0060] The tasks of the adapter FPGA include high-speed real-time data acquisition and preprocessing, direct control and rapid response of hardware interfaces, and communication interaction with digital energy switches. Specifically, high-speed real-time data acquisition and preprocessing is to quickly collect various types of real-time data in the system through the parallel processing capabilities in the adapter FPGA. Real-time data includes any one or more analog quantities of voltage, current, and temperature. And any one or more preliminary processing methods of filtering and amplification are performed in a timely manner. Provide a high-quality data source for subsequent analysis and decision-making. Direct control and rapid response of hardware interfaces is to directly control the hardware interface connected to external devices, and quickly and accurately control the input and output signals to ensure that the system can respond quickly in a rapidly changing environment. Analog quantities include any one or more data of voltage, current, and temperature. Communication interaction with the digital energy switch is through full-duplex optical fiber communication, using the DESS system-based proprietary communication protocol to achieve high-speed, stable, and accurate data transmission between the digital energy switch, ensuring real-time information sharing and system collaborative operation.

[0061] The tasks of the adapter CPU include complex strategy formulation and advanced analysis, global resource management and scheduling, advanced fault recording and broadcasting diagnosis, and historical problem analysis. Specifically, complex strategy formulation and advanced analysis are based on the large amount of data accumulated by the system over a long period of time, and conduct in-depth statistical analysis and trend prediction to provide macro-guidance for the system's operating strategy and development direction; global resource management and scheduling are to coordinate and reasonably allocate the software and hardware resources of the entire digital energy adapter to ensure that each module can work collaboratively and efficiently; advanced fault diagnosis and historical problem analysis is to deeply explore the root causes of system failures, and through a comprehensive analysis of past failure cases, form a comprehensive fault diagnosis system to provide decision-making support for preventing and solving similar problems that may arise in the future. The above-mentioned adapter CPU focuses on advanced strategy formulation.

[0062] Through the setting of the adapter CPU and adapter FPGA redundancy mechanism. When the adapter FPGA detects an abnormality in the adapter CPU, the adapter FPGA can work independently without the adapter CPU. Specifically, the adapter CPU is responsible for complex logic and algorithm processing, and the adapter FPGA performs high-speed parallel data processing and real-time control. By reasonably allocating tasks, the advantages of both are fully utilized. For example, the parallel processing capability of FPGA improves the computing speed, and its programmability facilitates functional expansion, and can optimize resource allocation and reduce power consumption. The dual system backup design enhances the reliability and fault tolerance of the system. Among them, the basic functions of the adapter FPGA, such as communication, analog acquisition and preliminary processing, and connection control with functional devices, are sufficient to maintain the safe operation of the product in a temporary state. As a result, the adapter FPGA can independently control the operation of the entire system, thereby reducing the risk of unexpected situations such as abnormal freezes of the adapter CPU in actual operation.

[0063] When the adapter CPU fails, the adapter FPGA can immediately take over the control of the system without waiting for the adapter CPU's instructions. It relies on its own processing power and pre-set control logic to continue to communicate with the digital energy switch to ensure normal data transmission and interaction. At the same time, the adapter FPGA can continue to collect and preliminarily process analog quantities and monitor key system parameters in real time. Make basic control decisions based on preset thresholds and rules; for example, take timely protective measures in emergency situations such as overvoltage and overcurrent to prevent the system from suffering more serious damage.

[0064] This redundant mechanism effectively reduces the risk of system failure due to adapter CPU failure. It greatly improves the stability and reliability of the digital energy adapter in complex working environments, providing a solid guarantee for the continuous and safe operation of the system. In addition, the clear division of labor between the adapter CPU and the adapter FPGA is conducive to the efficient operation and functional optimization of the system.

[0065] In addition, through the dual-chip setting of the adapter CPU and the adapter FPGA, 1) it is conducive to significantly enhancing the computing and processing capabilities of the adapter, which is mainly reflected in the adapter FPGA's ability to process multiple tasks in parallel and work in conjunction with the adapter CPU, thereby greatly improving the computing and processing capabilities; and it can more efficiently process complex energy management algorithms and massive data, and quickly make accurate decisions and controls. 2) It is conducive to improving the flexibility of adjusting and expanding functions within the system. Based on the programmable characteristics of the adapter FPGA, the adjustment and expansion of system functions are more flexible and convenient, and can quickly adapt to new needs and technological developments; 3) It is conducive to achieving independent and controllable production, and can ensure the security of the adapter's internal component supply chain; the use of domestic chips reduces dependence on imported chips and reduces the risk of supply chain interruptions caused by international relations, trade restrictions and other factors. The control of key technologies and data is more independent, which ensures the information security of the national energy field. 4) It is conducive to reducing the energy consumption of the adapter and improving the reliability and stability of the adapter's operation; 5) It is conducive to reducing the cost of the adapter. The use of domestic chips is conducive to reducing the cost of the import link and the emergence of potential risks; 6) It is conducive to improving the compatibility between the adapter and other domestic equipment, and in the event of an adapter failure, the manufacturer can provide corresponding after-sales service in a timely manner, so that the adapter can be stably operated and maintained, thereby driving the coordinated progress of the upstream and downstream industrial chains and forming a good industrial ecology.

[0066] A processing method for a digital energy adapter, the method is applied to the digital energy adapter. Figure 4 As shown, the method comprises the following steps:

[0067] Step 1: Data acquisition and preprocessing by adapter FPGA: The analog quantity from the system is acquired in real time through the high-speed parallel processing capability of the adapter FPGA. And according to the preset algorithms and rules, the collected data is preprocessed to extract valuable information and reduce the amount of data for subsequent processing. Among them, the preprocessing operation includes any one or more operation modes of screening, filtering and conversion. The analog quantity includes any one or more analog quantity data of current, voltage and temperature.

[0068] Step 2: The adapter FPGA performs data caching and processing: The pre-processed data is quickly stored in the high-speed data cache area opened up inside the adapter FPGA, which includes the digital energy switch communication cache area and the analog data acquisition cache area. When the data in the cache area reaches a certain amount or meets specific conditions, the required data is transferred to the CPU cache area, or it is preliminarily processed and analyzed.

[0069] Step 3: CPU processing and decision-making: After the adapter CPU obtains data from the CPU data cache, it performs in-depth calculations and analysis on the currently acquired data based on long-term historical data, and uses the required algorithms and models to generate corresponding control instructions and decision results. The calculation and analysis methods used include statistical analysis, and any one or more analysis methods in the formulation of advanced control strategies.

[0070] Step 4: Instruction transmission and execution: The adapter CPU temporarily stores the generated control instructions and processing results in the CPU data cache area. The adapter CPU is connected to the adapter FPGA through a two-way communication via the data address bus. After receiving the instruction, the adapter FPGA performs the corresponding operation to achieve precise control and regulation of the system; the corresponding operation includes adjusting the acquisition parameters and controlling the output signal. The data width of the data address bus is 16 bits.

[0071] Step 5. Exception handling and feedback: Through the setting of the dual interrupt mechanism within the system, the adapter FPGA and the adapter CPU can send interrupt requests to each other, and perform exception handling and feedback; specifically, the system sets up a dual interrupt mechanism. When an abnormal situation occurs, the abnormal situation includes that the adapter FPGA detects that the analog quantity exceeds the threshold or the adapter CPU fails. The adapter FPGA can send an interrupt request to the adapter CPU to let the adapter CPU handle the exception first. At the same time, the adapter CPU can also issue an interrupt in certain critical situations, instructing the adapter FPGA to perform specific tasks first. When the adapter CPU freezes abnormally, the adapter FPGA can rely on its own functions to work independently to ensure the basic operation of the system, and promptly feedback the abnormal information for subsequent fault diagnosis and recovery.

[0072] By setting the processing method, optimizing the communication protocol, and introducing the verification and error correction mechanism, the data processing efficiency and system stability can be improved. By coordinating the adapter CPU and the adapter FPGA in the digital energy adapter, using optical fiber materials to realize optical fiber communication, and through reasonable hardware configuration and software assistance, the digital energy adapter in this application can be made efficient, accurate, stable, and anti-interference.

[0073] Step one includes:

[0074] Step S11: the adapter FPGA collects analog data: the adapter FPGA collects current, voltage and temperature data respectively;

[0075] Step S12: The adapter FPGA processes the analog data: the adapter FPGA processes the current, voltage and temperature data respectively; and executes step 2.

[0076] Step S11 includes:

[0077] Step S111: The adapter FPGA collects voltage and current data: the adapter FPGA can use a time-sharing 3-point filtering method and / or a time-sharing 6-point filtering method to collect current; the adapter FPGA can use a time-sharing 6-point filtering method to collect voltage.

[0078] Step S112: The adapter FPGA collects temperature data: When collecting temperature data, the adapter FPGA appropriately extends the sampling time. Using 6-point filtering, data is collected every 2ms, and data is also collected continuously at 6 time points. Subsequently, the 6 data are sorted, the maximum and minimum values, which are two possible abnormal values, are removed, and then the average value of the remaining 4 data is calculated, and finally the average value is used as the final measurement value of the temperature. This collection and processing method based on the characteristics of temperature data effectively reduces the resource consumption of the system while ensuring the accuracy of measurement, and improves the operating efficiency of the entire system. In this embodiment, because the temperature changes relatively slowly in the system unlike the current, the sampling time is specifically set according to the needs during the temperature collection process. Temperature sampling time>current sampling time.

[0079] In step S111, the three-point filtering collects one data point every 200 ns, and collects data at three time points continuously. Then, the three data are averaged to obtain a relatively smooth and accurate current value.

[0080] The adapter FPGA collects data at a high frequency of every 200ns to ensure that it can capture rapid changes in current. In order to improve the accuracy and stability of the data, if one of the data values ​​differs too much from the average value during the time-sharing 3-point filtering process, it indicates that the data may be affected by strong electromagnetic interference or other abnormal factors, causing it to deviate from the true current value. In order to avoid this erroneous data from misleading fault identification, the adapter FPGA will decisively discard this abnormal value and continue to perform average calculations based on the remaining two data to obtain more reliable current measurement results. This processing method not only ensures that current data can be accurately collected in a strong electromagnetic interference environment and avoids fault identification errors caused by interference, but also gives full play to the high-speed processing capabilities of the adapter FPGA and realizes fast current data processing.

[0081] The time-sharing 6-point filtering collects data once every 300ns, and collects data at 6 time points continuously. Then, the 6 data are sorted. Through sorting, the maximum and minimum values ​​can be clearly identified. These two values ​​may be abnormal values ​​caused by instantaneous interference or measurement errors. After removing these two abnormal values, the average value of the remaining 4 data is calculated. Finally, this average value is used as the final measurement result of the current or voltage. This processing method further improves the accuracy and reliability of the current or voltage measurement, and provides strong support for the precise control and fault diagnosis of the system.

[0082] Step five includes:

[0083] Step S51: The adapter FPGA sends an interrupt to the adapter CPU: Determine whether the adapter CPU receives the interrupt processing signal from the adapter FPGA. If so, the data is abnormal, and step S52 is executed; if not, the data is normal, and step S51 is repeated for continuous monitoring; wherein the data abnormality type is any one or more abnormality types including analog quantity abnormality, communication failure, and other hardware failures.

[0084] Step S52: Determine the data anomaly type and perform corresponding processing actions.

[0085] Step five also includes:

[0086] Step S51': The adapter CPU sends an interrupt to the adapter FPGA: determine whether the adapter FPGA receives the interrupt processing signal from the adapter CPU. If so, the system is abnormal, and execute step S52'; if not, the system is normal, and repeat step S51' for continuous monitoring; wherein, the system abnormality type is any one or more of the abnormality types including emergency task issuance, key operation instruction issuance, and system resource adjustment instruction issuance.

[0087] Step S52': determine the system abnormality type and perform corresponding processing actions.

[0088] Step S52 includes:

[0089] Step S521: Determine whether the data anomaly type is an analog anomaly. If yes, the analog data collected by the adapter FPGA exceeds the preset safety range, that is, any one or more of the collected current, voltage, and temperature analog data exceeds the preset safety range, indicating that the system may have an abnormal situation. Execute step S522; if no, execute step S523;

[0090] Step S522: The adapter FPGA will immediately send an interrupt signal to the adapter CPU to notify the adapter CPU to perform corresponding processing.

[0091] Step S523: Determine whether the data anomaly type is a communication failure. If yes, execute step S524; if no, the data anomaly type is other hardware failure, execute step S525;

[0092] Step S524: During the communication between the digital energy adapter and the digital energy switch, if the adapter FPGA detects a communication error, the communication error includes any one or more of data transmission interruption, frame sequence number abnormality, or CRC check failure, the adapter FPGA will send an interrupt to the adapter CPU to allow the adapter CPU to intervene and solve the communication failure problem;

[0093] Step S525: When the adapter FPGA detects other hardware faults related to itself, including any one or more of cache read and write errors, internal logic operation abnormalities, etc., the adapter FPGA will also send an interrupt to the adapter CPU, and the adapter CPU will take corresponding measures, including adjusting system parameters, starting backup devices, or recording faults.

[0094] Among them, in steps S522, S524, and S525, the adapter FPGA interrupt processing: when the adapter FPGA sends an interrupt to the adapter CPU, the adapter FPGA will suspend the current non-urgent task and pass the interrupt-related information to the adapter CPU. The interrupt-related information includes the type of exception and / or the specific value of the analog quantity. After receiving the interrupt signal, the adapter CPU will quickly switch to the interrupt handler, perform corresponding analysis and processing based on the interrupt information, and take measures to restore the normal operation of the system or avoid further expansion of the fault.

[0095] Step S52' comprises:

[0096] Step S521': determine whether the system abnormality type is an emergency task, if yes, execute step S522'; if no, execute step S523';

[0097] Step S522': When the adapter CPU receives an emergency instruction from the upper system and needs to immediately adjust the working mode of the digital energy adapter or the preset value of the required parameters, the adapter CPU will send an interrupt to the adapter FPGA, requiring the adapter FPGA to change quickly to meet specific monitoring requirements. The preset value of the required parameters includes the frequency or range of analog quantity acquisition.

[0098] Step S523': Determine whether the system abnormality type is a key operation instruction. If yes, execute step S524'; if no, the system data abnormality is a system resource adjustment instruction, execute step S525';

[0099] Step S524': According to the key instruction information issued, the adapter CPU will send an interrupt to the adapter FPGA, instructing the adapter FPGA to prioritize the execution of these key operations. Preferably, in certain key situations, when the system needs to perform rapid energy scheduling or execute a specific control strategy, the adapter CPU will send an interrupt to the adapter FPGA, instructing the adapter FPGA to prioritize the execution of these key operations, to ensure that the system can respond to important control instructions in a timely manner;

[0100] Step S525': When the adapter CPU determines that the resource allocation of the adapter FPGA needs to be adjusted according to the overall operation of the system, it will send an interrupt to the adapter FPGA to make the adapter FPGA work according to the new resource allocation scheme. The resource adjustment type includes any one or more resource types of adjusting the operating frequency of the adapter FPGA, shutting down certain non-critical functions to reduce power consumption.

[0101] Among them, in steps S522', S524', and S525', the adapter CPU interrupts processing: when the adapter CPU sends an interrupt to the adapter FPGA, the adapter FPGA will immediately stop the current work and give priority to executing the task specified by the adapter CPU. After executing the task, the adapter FPGA will feedback the result of the task execution to the adapter CPU so that the adapter CPU can understand the response of the system.

[0102] The setting of the dual interrupt mechanism is conducive to improving the system response speed, enhancing the system stability, and improving the flexibility to adapt to various situations. Improving the system response speed is to ensure that the system can respond quickly when an abnormality occurs or when a critical task needs to be performed through timely interrupt signal transmission, reducing the system response time and improving the real-time performance of the system. Enhancing the system stability is to be able to take timely measures to deal with abnormal situations to avoid further deterioration of the fault, thereby enhancing the stability and reliability of the system. Flexible adaptation to various situations is that the dual interrupt mechanism can flexibly respond to hardware abnormalities detected by the adapter FPGA or external instructions received by the adapter CPU, allowing the system to maintain efficient operation in different situations.

[0103] It should be noted that the recording and broadcasting function in the adapter CPU can record and analyze historical data and operating conditions in detail, allowing users to view multiple key information within a week, providing a solid data foundation for accurate system monitoring, performance evaluation, fault diagnosis and optimization and improvement.

[0104] a. The recording and broadcasting function can make the bus voltage show a clear trend of changes in the past. Users can not only intuitively see the real-time fluctuation curve of the bus voltage within a week, but also obtain detailed information such as the specific time point and duration of the highest and lowest voltages. This helps to deeply analyze the power supply stability of the system and promptly detect possible abnormal voltage fluctuations, such as momentary voltage spikes or long-term voltage offsets, so as to take targeted control measures in advance to ensure the normal and stable operation of the system. In addition, the recording and broadcasting function can also provide statistical data of the bus voltage, including any one or more of the voltage average value, root mean square value, and standard deviation, to help users evaluate the quality and stability of the bus voltage from multiple angles.

[0105] b. The recording function can also accurately record the changing trend of the current in the past week. Users can clearly observe the dynamic change process of the current, including the peak and valley values ​​of the current and the time nodes of their occurrence. This is of great guiding significance for in-depth understanding of the load characteristics of the system, detection of possible overload conditions, and optimization of energy distribution strategies. In addition, the recording function can also provide relevant statistical information of the current, including any one or more information of the effective value, harmonic content, and power factor of the current. These data help to comprehensively evaluate the quality of the current and the energy efficiency of the system.

[0106] c. The recording and broadcasting function can also make the historical output and input power curves of the digital energy adapter be fully recorded. Users can use the recording and broadcasting function to view the real-time change curve of power within a week, including the peak and valley values ​​of power and the stability of power. This plays a key role in evaluating the energy utilization efficiency, load matching degree and operation economy of the system. The recording and broadcasting system can also provide detailed statistical data on power application, including any one or more data of total energy output and input, average power, power factor and load rate, which provides an important reference for system performance evaluation and optimization.

[0107] d. The recording function can also accurately record the energy input and output of the system within a week. Users can view the cumulative change curve of energy and understand the flow direction and amount of energy in different time periods. This is of great significance for evaluating the energy utilization efficiency of the system, calculating costs, and formulating energy-saving strategies. It can also obtain relevant statistical data on energy, such as total input energy, total output energy, energy loss, etc., to help users fully understand the energy balance of the system.

[0108] e. The recording and broadcasting function can also record the changes in ambient temperature in detail. Users can use the recording and broadcasting function to view the continuous change curve of ambient temperature within a week, understand the periodic change law of ambient temperature and the period when extreme temperature occurs. This is of great significance for evaluating the thermal stability of the system environment and predicting system performance fluctuations that may be caused by changes in ambient temperature. It can also obtain statistical data of ambient temperature, including any one or more data of average temperature, temperature fluctuation range, and temperature change rate, providing strong support for the environmental adaptability analysis of the system.

[0109] f. The recording function can also make the temperature distribution of different locations inside the chassis known, and understand the hot spots and temperature gradients. Optimize the chassis air duct design, improve the heat sink layout or adjust the fan strategy to improve the working stability and life of each component in the chassis.

[0110] g. The recording and broadcasting function can also accurately record the historical changes in IGBT temperature. Users can use the recording and broadcasting function to closely monitor the changing trend of IGBT temperature within a week and promptly discover the time period when the temperature rises abnormally, which is crucial for protecting the safe operation of IGBT devices and preventing device damage caused by overheating. The recording and broadcasting function can also provide relevant statistical data on IGBT temperature, including any one or more of the highest temperature, average temperature, and temperature change range, which helps to evaluate the working status and reliability of the IGBT.

[0111] h. The recording and broadcasting function can also record the operation of the fan in detail. Users can view the fan speed change curve through the recording and broadcasting function to understand the fan's operating status under different working conditions. This is of great significance for evaluating the fan's working efficiency, predicting fan failures, and optimizing the control strategy of the cooling system. It can also obtain relevant statistical data of the fan, including any one or more data of average speed, maximum speed, speed fluctuation range, etc., which helps to judge the performance and stability of the fan.

[0112] i. The recording function can also analyze the historical heat dissipation of the chassis. Users can view the change curve of the chassis heat dissipation within a week and understand the chassis heat dissipation performance under different environments and working conditions. This is of great significance for evaluating the heat dissipation effect of the chassis, optimizing the system layout, and preventing system failures caused by poor heat dissipation. It can also obtain relevant statistical data on the heat dissipation of the chassis, including any one or more data of average heat dissipation, maximum heat dissipation, and heat dissipation efficiency, providing a basis for improving the heat dissipation design of the chassis and the thermal management strategy of the system.

[0113] j. The recording and playback function can also monitor the temperature changes of the adapter CPU in real time to ensure that it works within a safe temperature range. Heat dissipation measures can be taken in a timely manner, including adjusting the fan speed, optimizing the system load distribution or improving the heat sink contact, so as to maintain the system's efficient processing capabilities.

[0114] k. The recording and playback function can also monitor the temperature of the adapter FPGA to prevent performance degradation or hardware damage caused by high temperature. Take appropriate heat dissipation measures in time to ensure the stable operation of the adapter FPGA.

[0115] l. The recording and broadcasting function can also monitor the electromagnetic interference intensity and spectrum distribution during the operation of the system, so as to take measures such as shielding and filtering to reduce the impact of electromagnetic interference and ensure the normal operation of the system without causing interference to other equipment.

[0116] m. The recording and broadcasting function can also record changes in environmental humidity and evaluate its impact on the insulation performance of the equipment and the reliability of electronic components. This allows for the adoption of moisture-proof or humidification measures to ensure reliable operation of the equipment in an environment with suitable humidity. It can also monitor changes in communication quality indicators within a week. Communication quality indicators include any one or more of the bit error rate, signal strength, and signal-to-noise ratio, which are used to evaluate the stability and reliability of optical fiber communications. It can also promptly detect potential communication failures, adjust communication parameters, optimize optical path connections, or replace faulty components to ensure accurate data transmission.

[0117] n. The recording function can also count the cumulative running time of the equipment, providing a reference for maintenance and replacement of parts. Formulate a reasonable maintenance plan, perform preventive replacement of vulnerable parts, and reduce the risk of sudden equipment failure.

[0118] o. The recording function can also record the alarm time, type and recovery time of various faults and abnormal situations. Quickly locate the fault point, analyze the cause of the fault, optimize the system design and operation strategy, and improve the ability to respond to faults.

[0119] In summary, the comprehensive recording and broadcasting functions and rich parameter records of the digital energy adapter provide strong support for system operation monitoring, performance evaluation, fault diagnosis and optimization and improvement, which helps to ensure the stable, efficient and reliable operation of the system and meet the needs of various complex application scenarios.

[0120] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital energy adapter, characterized in that: It includes an adapter CPU and an adapter FPGA, one end of the adapter CPU is connected to the adapter FPGA, and the other end of the adapter CPU is connected to the upper cloud or host through a network for two-way communication; the adapter FPGA includes a data cache area, an information flow control module, an analog quantity control module, and an optical fiber communication module; The adapter FPGA is connected to the digital energy switch via optical fiber; The adapter FPGA is connected to the energy component and the energy storage converter PCS through the DC input and output units to control the input and output of energy.

2. A digital energy adapter according to claim 1, characterized in that: The data buffer area includes a CPU data buffer area, a switch data buffer area, and an analog data buffer area.

3. A digital energy adapter according to claim 2, characterized in that: One end of the information flow control module and the analog quantity control module are connected to the adapter CPU through the CPU data cache area for bidirectional communication, and the other ends of the information flow control module and the analog quantity control module communicate with the switch data cache area and the analog quantity data cache area respectively. The switch data cache area is connected to the digital energy switch through the optical fiber communication module, and the analog quantity data cache area communicates with the internal sensor of the adapter through the analog quantity acquisition and processing module.

4. A digital energy adapter according to claim 3, characterized in that: An AD converter is arranged between the analog quantity acquisition and processing module and the sensor.

5. A digital energy adapter according to claim 1, characterized in that: The adapter FPGA also includes an analysis and processing module and an energy control unit. The analysis and processing module communicates bidirectionally with the information flow control module and the analog quantity control module respectively, and the analysis and processing module communicates bidirectionally with the DC input and output unit through the energy control unit.

6. A digital energy adapter according to claim 1, characterized in that: The adapter CPU includes a recording and broadcasting function for recording and analyzing historical data and operating conditions in detail, allowing users to view multiple key information within a week and providing a data basis for the system.

7. A digital energy adapter according to claim 5, characterized in that: The adapter FPGA also includes a fan control unit, one end of which is bidirectionally connected to the analysis and processing module, and the other end of which is connected to the fan, and the fan is arranged inside the adapter.

8. A digital energy adapter according to claim 5, characterized in that: The adapter FPGA also includes an abnormal feedback module, one end of the abnormal feedback module bidirectionally communicates with the information flow control module and the analysis and processing module respectively, and the other end of the abnormal feedback module bidirectionally communicates with the adapter CPU.

9. A DESS system, characterized in that: The system comprises a digital energy adapter according to any one of claims 1 to 8, the system comprises a digital energy hub and a digital energy network card, the digital energy hub is respectively connected to the digital energy switch and the digital energy network card via Ethernet, and the digital energy switch and the digital energy adapter are connected via optical fiber communication; The digital energy network card is connected to the energy components one by one, and the DC side of the digital energy network card and the energy storage converter PCS is connected to the positive and negative poles of the digital energy adapter respectively.

10. A processing method for a digital energy adapter, characterized in that: The method is applied to a digital energy adapter according to any one of claims 1 to 8, and the method comprises the following steps: Step 1: Data acquisition and preprocessing by adapter FPGA: The analog quantity from the system is acquired in real time through the parallel processing capability of adapter FPGA; and preliminary preprocessing operations are performed on the acquired data according to preset algorithms and rules; Step 2: The adapter FPGA performs data caching and processing; Step 3: CPU processing and decision-making: After the adapter CPU obtains data from the CPU data buffer, it performs in-depth calculations and analysis on the currently acquired data; and uses the required algorithms and models to generate corresponding control instructions and decision results; Step 4: Instruction transmission and execution: The adapter CPU temporarily stores the generated control instructions and processing results in the CPU data buffer area, and transmits them to the adapter FPGA through the data address bus; after receiving the instructions, the adapter FPGA executes the corresponding operation; Step 5: Exception handling and feedback: Through the setting of the dual interrupt mechanism in the system, the adapter FPGA and the adapter CPU can send interrupt requests to each other and perform exception handling and feedback.

11. A processing method for a digital energy adapter according to claim 10, characterized in that: In the step 1, the analog quantity includes any one or more analog quantity data of current, voltage, and temperature.

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