On-chip high-density capacitor

Abstract

The invention provides an on-chip high-density capacitor which comprises a substrate and two metal oxide variable capacitors formed on the substrate, a grid electrode GATE of a first metal oxide variable capacitor Q1 is connected with a top plate PLUS, and a grid electrode GATE of a second metal oxide variable capacitor Q2 is connected with a bottom plate MINUS; the N well contact end of the Q1 is connected to a base plate MINUS; the grid electrode GATE of the Q2 is connected to the MINUS end, and the N well contact end of the Q2 is connected to the PLUS end; the on-chip high-density capacitor further comprises a metal capacitor CAPMOM. According to the on-chip high-density capacitor, the two metal oxide variable capacitors of the CAPGATE capacitor are reversely connected, so that the CAPGATE capacitor basically does not change along with the change of voltage, the stability is higher, and the coupling capability is stronger. Furthermore, the density of the on-chip high-density capacitor is improved by superposing the CAPMOM capacitor.

Description

Technical Field

[0001] The present invention relates to the field of capacitor technology, and in particular to an on-chip high-density capacitor. Background Art

[0002] In deep submicron technology, as device size continues to shrink, the digital logic area of ​​integrated circuits (chips) continues to decrease. However, due to application function and performance requirements, analog devices need to add sufficient capacitors for filtering, denoising, coupling and other functions to ensure that different modules operate in their respective optimal operating ranges. This will increase the area and increase costs.

[0003] The advantage of on-chip high-density capacitor devices over ordinary capacitors is that they have a larger capacitance per unit area under the same area.

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0005] In view of the above technical problems in the related art, the present invention proposes an on-chip high-density capacitor, which includes a substrate and two metal oxide variable capacitors formed on the substrate, the gate GATE of the first metal oxide variable capacitor Q1 is connected to the top plate PLUS, and the gate GATE of the second metal oxide variable capacitor Q2 is connected to the bottom plate MINUS; the N-well contact end of Q1 is connected to the bottom plate MINUS; the gate GATE of Q2 is connected to the MINUS end, and the N-well contact end of Q2 is connected to the PLUS end; the on-chip high-density capacitor also includes: a metal capacitor CAP_MOM, which is vertically arranged on the GATE layer of Q1 and Q2.

[0006] Specifically, the metal capacitor is connected to the N-wells of Q1 and Q2 through the metal contact layer CT.

[0007] Specifically, the metal layer of the metal capacitor is multi-layered.

[0008] Specifically, the metal layers of the metal capacitor are stacked in an interdigitated manner.

[0009] Specifically, the metal in the CAP_MOM capacitor generates capacitance between the positive and negative plates alternating with multiple metal layers in the same layer, and generates capacitance between the positive and negative plates alternating with multiple different metal layers.

[0010] Specifically, a plurality of metal strips horizontally and alternately connecting the plates are stacked on the gate of the metal oxide variable capacitor.

[0011] Specifically, the positive and negative plates are connected alternately horizontally and vertically on the side of the metal layer, and the "+" plate is connected to the PLUS terminal and the "-" plate is connected to the MINUS terminal.

[0012] Specifically, it includes 2N metal oxide variable capacitors, where N is a positive integer greater than or equal to 2.

[0013] Specifically, the metal layers in the vertical direction of the CAP_MOM capacitor are connected through contact holes.

[0014] The on-chip high-density capacitor of the present invention includes: a CAP_GATE capacitor and a metal capacitor CAP_MOM, wherein the CAP_MOM capacitor is perpendicular to the CAP_GATE capacitor and does not occupy the component area. The two metal oxide variable capacitors of the CAP_GATE capacitor are reversely connected, so that the CAP_GATE capacitor does not change substantially with the change of voltage, has higher stability and stronger coupling capability. Further, a CAP_MOM capacitor is superimposed on the CAP_GATE capacitor, and the CAP_MOM capacitor includes capacitors between alternating positive and negative plates in the horizontal direction of multiple metal layers in the same layer, and capacitors between alternating positive and negative plates in the vertical direction of multiple different metal layers, which are connected in parallel with each other through multiple coupling capacitors in different directions to form a high-density CAP_MOM capacitor, thereby further improving the density of the on-chip high-density capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 is a three-dimensional diagram of an on-chip capacitor provided by an embodiment of the present invention; Figure 2 is a perspective view of an on-chip capacitor provided by an embodiment of the present invention; Figure 3 The CV characteristic changes of the metal oxide variable capacitor, the CV characteristic changes of the metal oxide semiconductor field effect transistor, and the CV characteristic changes of the CAP_GATE capacitor provided by the embodiments of the present invention; the number 1 in the figure represents the metal oxide variable capacitor; the number 2 in the figure represents the metal oxide semiconductor field effect transistor; the number 3 in the figure represents the CAP_GATE capacitor composed of two metal oxide variable capacitors connected in reverse; Figure 4is a cross-sectional view of an on-chip capacitor provided by an embodiment of the present invention; Figure 5 is a perspective view of a PLUS end of a CAP_MOM structure provided by an embodiment of the present invention; Figure 6 is a perspective view of the MINUS end of a CAP_MOM structure provided by an embodiment of the present invention; Figure 7 It is a top view of the CAP_GATE structure with M1 provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0018] refer to Figure 1-2 7. This embodiment provides an on-chip high-density capacitor, including a substrate and two metal oxide variable capacitors formed on the substrate. Specifically, the gate GATE of the first metal oxide variable capacitor Q1 is connected to the top plate PLUS, and the gate GATE of the second metal oxide variable capacitor Q2 is connected to the bottom plate MINUS; the N-well contact terminal of Q1 is connected to the bottom plate MINUS; the gate GATE of Q2 is connected to the MINUS terminal, and the N-well contact terminal of Q2 is connected to the PLUS terminal; the on-chip high-density capacitor also includes: a metal capacitor CAP_MOM, which is vertically arranged on the GATE layer of Q1 and Q2.

[0019] The on-chip high-density capacitor of this embodiment includes a MOS capacitor CAP_GATE and a metal capacitor CAP_MOM formed by two metal oxide variable capacitors connected in reverse.

[0020] refer to Figure 3 , for MOSFET metal oxide semiconductor field effect transistors, the capacitance is relatively small near 0V, while the metal oxide variable capacitor increases with the increase of voltage and is greatly affected by voltage. This structure still has defects, but when two metal oxide variable capacitors are connected in reverse, their capacitance value is relatively stable regardless of how the voltage changes, and the coupling ability is stronger.

[0021] The CAP_GATE capacitor of this embodiment connects two metal oxide variable capacitors in reverse, so that the capacitance thereof does not change substantially with the voltage.

[0022] In this embodiment, the unit capacitance density of the CAP_GATE capacitor is about 3fF / um2.

[0023] The on-chip high-density capacitor of this embodiment must have at least two metal oxide variable capacitors, where the two metal oxide variable capacitors are similar to Fingger. When Fingger is 1, the devices are Q1 and Q2, and when Fingger is 2, the devices are Q1, Q2, Q3, and Q4. The connection mode of Q3 is consistent with that of Q1, and the connection mode of Q4 is consistent with that of Q2.

[0024] Specifically, the metal capacitor of this embodiment is connected to the N-wells of Q1 and Q2 through the metal contact layer CT.

[0025] Specifically, the metal layer of the metal capacitor of this embodiment is multi-layered, and the capacitance of the metal capacitor can be effectively increased by setting the multi-layered metal layer. Figure 1-2 , the metal layer of this embodiment is 4 layers, but it is not limited to 4 layers. The more metal layers are stacked, the higher the density of the CAP_MOM capacitor. In the example, the unit capacitance density of the CAP_MOM capacitor composed of 4 layers of metal is about 2.4fF / um2. If the metal layer is 6 layers, the unit capacitance density of the CAP_MOM capacitor is about 3.6 fF / um2.

[0026] That is, the on-chip high-density capacitor of this embodiment can increase the capacitance density by stacking multiple metal layers, and the CAP_MOM capacitor is perpendicular to the CAP_GATE capacitor and does not occupy the component area.

[0027] For further reference, Figure 2 In the CAP_MOM capacitor of this embodiment, the metal stacking adopts an interdigital method, and each metal layer in the vertical direction is alternately connected to the PLUS and MINUS terminals, and each metal layer in the horizontal direction is alternately connected to the PLUS and MINUS terminals.

[0028] refer to Figure 2, the metal layer of the CAP_MOM capacitor of the present embodiment is 4 layers, namely M1, M2, M3, Mx, wherein M1 is connected to the N well of metal oxide variable capacitor Q1, Q2 through CT. There are 15 layers from left to right, that is, there are 15 layers in the horizontal direction, namely the 1st ... 15th layers. Wherein for the 1st layer in the horizontal direction, its metal layer in the vertical direction alternately adopts "-", "+", "-", "+" plates, wherein the "+" plate is connected to the PLUS end and the "-" plate is connected to the MINUS end. For the M1 layer, its metal layer in the horizontal direction alternately adopts "-", "+", "-", "+" ... "-" plates, wherein the "+" plate is connected to the PLUS end and the "-" plate is connected to the MINUS end. Capacitance can be generated between the "+" and "-" plates in the vertical direction, and capacitance can also be generated between the "+" and "-" plates in the horizontal direction. That is, the metal superposition in the CAP_MOM capacitor of this embodiment adopts an interdigital crossover method, which not only generates capacitance between alternating positive and negative plates in the horizontal direction of multiple metal layers in the same layer, but also generates capacitance between alternating positive and negative plates in the vertical direction of multiple different metal layers.

[0029] from Figure 2 It can be seen that the metal layer of this embodiment is a strip-shaped metal strip, which is superimposed on the CAP_GATE capacitor in the vertical direction. The strip-shaped metal strips are arranged at intervals in the horizontal direction, thereby forming polar plates in the horizontal and vertical directions.

[0030] In the CAP_MOM capacitor of this example, the metal stacking adopts the interdigital cross-linking method to further increase the capacitance density of the CAP_MOM.

[0031] The metal layers in the CAP_MOM capacitor of this embodiment are connected through the V1 layer, and the V1 is a contact hole between metal layers, providing an electrical channel between adjacent metal layers, and is an interface connecting two layers of interconnection lines. Similarly, V2 represents the interface of the interconnection line between M2 and M3, and VNX represents the interface of the interconnection line between M3 and MnX.

[0032] according to Figure 5 and 6 As shown, metal M1 and M2 need to be connected through the V1 layer, metal M2 and M3 need to be connected through the V2 layer, and metal M3 and MnX need to be connected through the VNX layer. The PLUS and MINUS terminals connected on the side, M1 to MnX are all connected, while the front marks 11 (MnX), 22 (M3), 33 (M2), 44 (M1) are not connected to each other, and marks 55 (MnX), 66 (M3), 77 (M2), 88 (M1) are not connected to each other. These marks alternately connect the positive and negative plates horizontally and vertically, and finally the "+" plate is connected to the PLUS terminal, and the "-" plate is connected to the MINUS terminal.

[0033] refer to Figure 2 , 4 , the gate of device Q1 is connected to the PLUS terminal, and three metal M1s are stacked on the gate to alternately connect the "+", "-" and "+" plates horizontally (add multiple metal M1s with alternating positive and negative plates horizontally according to the width and length of the gate). The N well of Q1 is connected to the MINUS terminal through M1. The substrate terminal of device Q1 is connected to the MINUS terminal through M1, and metal M1 is inserted between the N well of Q1 and the P+ substrate terminal to connect to the PLUS terminal, and metal M1 is inserted between the N well of Q1 and the P+ substrate terminal to connect to the PLUS terminal.

[0034] The gate of device Q2 is connected to the MINUS terminal through GATE, and three metal M1s are stacked on the gate to alternately connect the "-", "+" and "-" plates horizontally. The N well of device Q2 is connected to the PLUS terminal through M1. The substrate terminal of device Q2 is connected to the MINUS terminal through M1.

[0035] The technical solution of this embodiment is a high-density capacitor device composed of a CAP_GATE capacitor and a CAP_MOM capacitor in parallel. This structure has multiple advantages: First, the CAP_MOM capacitor is perpendicular to the CAP_GATE capacitor and does not occupy the component area. Second, the CAP_MOM capacitor is composed of metal, including capacitors between alternating positive and negative plates in the horizontal direction of multiple metal layers in the same layer, and capacitors between alternating positive and negative plates in the vertical direction of multiple different metal layers. With the superposition of metal layers, these multiple coupling capacitors in different directions are connected in parallel to form a high-density CAP_MOM capacitor. Third, the CAP_GATE capacitor does not change substantially with changes in voltage, has higher stability, and has stronger coupling capability.

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An on-chip high-density capacitor, comprising a substrate and two metal oxide variable capacitors formed on the substrate, characterized in that: The gate GATE of the first metal oxide variable capacitor Q1 is connected to the top plate PLUS, and the gate GATE of the second metal oxide variable capacitor Q2 is connected to the bottom plate MINUS; the N-well contact terminal of Q1 is connected to the bottom plate MINUS; the gate GATE of Q2 is connected to the MINUS terminal, and the N-well contact terminal of Q2 is connected to the PLUS terminal; The on-chip high-density capacitor further includes: a metal capacitor CAP_MOM, which is vertically arranged on the GATE layer of Q1 and Q2.

2. The on-chip high-density capacitor according to claim 1, characterized in that: The metal capacitor is connected to the N-wells of Q1 and Q2 through the metal contact layer CT.

3. The on-chip high-density capacitor according to claim 2, characterized in that: The metal capacitor has multiple metal layers.

4. The on-chip high-density capacitor according to claim 3, characterized in that: The metal layers of the metal capacitor are superimposed in a finger-cross manner.

5. The on-chip high-density capacitor according to claim 4, characterized in that: The metal in the CAP_MOM capacitor generates capacitance between the positive and negative plates alternating with multiple metal layers in the same layer, and also generates capacitance between the positive and negative plates alternating with multiple different metal layers.

6. The on-chip high-density capacitor according to claim 5, characterized in that: A plurality of metal strips horizontally and alternately connecting the plates are stacked on the gate of the metal oxide variable capacitor.

7. The on-chip high-density capacitor according to claim 6, characterized in that: On the side of the metal layer, the positive and negative plates are connected alternately horizontally and vertically, the "+" plate is connected to the PLUS terminal, and the "-" plate is connected to the MINUS terminal.

8. The on-chip high-density capacitor according to claim 1, characterized in that: It includes 2N metal oxide variable capacitors, where N is a positive integer greater than or equal to 2.

9. The on-chip high-density capacitor according to claim 7, characterized in that: The metal layers in the vertical direction of the CAP_MOM capacitor are connected through contact holes.

10. The on-chip high-density capacitor according to claim 8, characterized in that: The unit capacitance density of the capacitor composed of two metal oxide variable capacitors is 3.6 fF / um2.

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