A waveform generation circuit and method based on FPGA

Abstract

The application discloses a waveform generation circuit and method based on FPGA, and relates to the technical field of waveform generation.The waveform generation circuit comprises a field programmable gate array and a digital-to-analog conversion chip.In the field programmable gate array, a memory access module is used to access the memory to obtain configuration information and data information corresponding to a self-defined waveform.A selection module and a control module are used to generate selection signals and control signals according to the configuration information and the data information in sequence, so that the output of a waveform generation module is controlled, the waveform generation module outputs a self-defined waveform digital signal according to the data information, and finally, the digital-to-analog conversion chip outputs the self-defined waveform according to the self-defined waveform digital signal.The application uses the FPGA to replace a special hardware circuit, reduces the production and development cost, and can generate waveforms of different types of print heads by modifying the configuration information in the memory, so that the update and replacement are simple.

Description

Technical Field

[0001] This application relates to the field of waveform generation technology, and in particular to an FPGA-based waveform generation circuit and waveform generation method. Background Technology

[0002] The printhead is a core component of a printer, responsible for converting electronic data into physical printed output. In existing technologies, printhead waveform generation typically relies on dedicated hardware circuitry, lacking flexibility and programmability. Furthermore, different types of printheads require different waveform generation circuits, increasing development and production costs. With the continuous advancement of printing technology and the growth of diverse demands, the market urgently needs a universal waveform generator capable of flexible configuration and efficient output of multiple waveform modes. Summary of the Invention

[0003] The purpose of this application is to provide an FPGA-based waveform generation circuit and waveform generation method, which can generate waveforms of different types of printheads through flexible configuration.

[0004] To achieve the above objectives, this application provides the following solution:

[0005] In a first aspect, this application provides a waveform generation circuit based on FPGA, including: a field-programmable gate array and a digital-to-analog converter chip; the field-programmable gate array includes a memory access module, a selection module, a control module and a waveform generation module.

[0006] The memory access module is used to access memory to obtain the configuration information and data information corresponding to the custom waveform, and then send the configuration information and data information to the selection module, control module, and waveform generation module.

[0007] The selection module is used to generate a selection signal based on the memory access module's read end signal, configuration information, and data information, in order to select the control signal generated by the control module.

[0008] The control module is used to generate control signals based on the selection signal, configuration information, and data information from the selection module, so as to control the output of the waveform generation module.

[0009] The waveform generation module is used to output custom waveform digital signals based on the control signals and data information from the control module.

[0010] A digital-to-analog converter chip is used to output a custom waveform based on a custom digital waveform signal.

[0011] Optionally, the selection signal includes: a selection module clock signal, a selection module latch signal, and a selection module data signal; the control signal includes: a control module clock signal, a control module latch signal, and a control module data signal.

[0012] Optionally, the configuration information includes: the number of clock pulses, the number of waveform outputs, and the waiting time; the data information includes the selection module data signal, the control module data signal, the waveform array, the voltage array, and the time array.

[0013] Optionally, a selection signal is generated based on the memory read end signal, configuration information, and data information from the memory access module, specifically including the following steps:

[0014] The memory access module's read end signal is used as the selection module's start signal.

[0015] The selection module generates a selection signal based on the number of clock pulses, the number of waveform outputs, the waiting time, and the selection module data signal.

[0016] Optionally, a control signal is generated based on the selection signal, configuration information, and data information of the selection module, specifically including the following steps:

[0017] The inverted value of the selection module latch signal in the selection signal is used as the start signal of the control module.

[0018] The control module generates control signals based on the number of clock pulses, the number of waveform outputs, the waiting time, and the control module data signals.

[0019] Optionally, based on the control signals and data information from the control module, a custom waveform digital signal is output, specifically including the following steps:

[0020] The inverted value of the control module latch signal in the control signal is used as the start signal of the waveform generation module.

[0021] The waveform generation module outputs a custom waveform digital signal based on the waveform array, voltage array, and time array.

[0022] Secondly, this application provides a waveform generation method based on FPGA, including the following steps:

[0023] The memory access module accesses the memory to obtain the configuration and data information corresponding to the custom waveform, and then sends the configuration and data information to the selection module, control module, and waveform generation module.

[0024] The selection module generates a selection signal based on the memory access module's read end signal, configuration information, and data information, in order to select the control signal generated by the control module.

[0025] The control module generates control signals based on the selection signals, configuration information, and data information from the selection module, thereby controlling the output of the waveform generation module.

[0026] The waveform generation module outputs a custom waveform digital signal based on the control signals and data information from the control module.

[0027] A digital-to-analog converter chip outputs a custom waveform based on a custom digital signal.

[0028] Optionally, the configuration information includes: the number of clock pulses, the number of waveform outputs, and the waiting time; the data information includes the selection module data signal, the control module data signal, the waveform array, the voltage array, and the time array.

[0029] The selection module generates a selection signal based on the memory access module's read end signal, configuration information, and data information, in order to select the control signal generated by the control module. This process includes the following steps:

[0030] The memory access module's read end signal is used as the selection module's start signal.

[0031] The selection module generates a selection signal based on the number of clock pulses, the number of waveform outputs, the waiting time, and the selection module data signal. The selection signal includes the selection module clock signal, the selection module latch signal, and the selection module data signal.

[0032] Optionally, the control module generates a control signal based on the selection signal, configuration information, and data information from the selection module to control the output of the waveform generation module, specifically including the following steps:

[0033] The inverted value of the selection module latch signal in the selection signal is used as the start signal of the control module.

[0034] The control module generates control signals based on the number of clock pulses, the number of waveform outputs, the waiting time, and the control module data signals. The control signals include: the control module clock signal, the control module latch signal, and the control module data signals.

[0035] Optionally, the waveform generation module outputs a custom waveform digital signal based on the control signals and data information from the control module, specifically including the following steps:

[0036] The inverted value of the control module latch signal in the control signal is used as the start signal of the waveform generation module.

[0037] The waveform generation module outputs a custom waveform digital signal based on the waveform array, voltage array, and time array.

[0038] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0039] This application provides a waveform generation circuit and method based on FPGA. The waveform generation circuit includes a field-programmable gate array (FPGA) and a digital-to-analog converter (DAC). In the FPGA, a memory access module accesses memory to obtain configuration and data information corresponding to a custom waveform. A selection module generates a selection signal based on the memory access module's end-of-memory signal, configuration and data information, to select a control signal generated by a control module. The control module then generates a control signal based on the selection signal, configuration and data information to control the output of the waveform generation module. The waveform generation module outputs a custom waveform digital signal based on the control signal and data information from the control module. Finally, the DAC outputs the custom waveform based on the custom waveform digital signal. This application, through the above circuit structure, uses an FPGA to replace dedicated hardware circuits, reducing production and development costs. Furthermore, by modifying the configuration information in memory, waveform generation for different types of printheads can be achieved. Updating the FPGA program is sufficient to adapt to the waveform requirements of new printheads, simplifying upgrades. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a functional block diagram of an FPGA-based waveform generation circuit provided in one embodiment of this application.

[0042] Figure 2 This is a schematic diagram showing the layout of data in memory in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0043] Figure 3 This is a schematic diagram of the state machine of the accessMem module memory access function in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0044] Figure 4 This is a schematic diagram of the state machine of the accessMem module for reading BRAM in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0045] Figure 5 This is a schematic diagram of the input and output of the accessMem module in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0046] Figure 6This is a waveform diagram of each output signal of the XGenerator in an FPGA-based waveform generation circuit provided in an embodiment of this application.

[0047] Figure 7 This is a schematic diagram of the state machine of the XGenerator module in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0048] Figure 8 This is a schematic diagram of the input and output of the XGenerator module in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0049] Figure 9 This is a schematic diagram of the state machine of the VGenerator module in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0050] Figure 10 This is a schematic diagram illustrating the process of generating a vcom waveform using a VGenerator module and a DAC chip in an FPGA-based waveform generation circuit, as provided in an embodiment of this application.

[0051] Figure 11 This is a schematic diagram illustrating the connection relationship between modules in an FPGA-based waveform generation circuit according to an embodiment of this application.

[0052] Figure 12 This is a flowchart of an FPGA-based waveform generation method provided in an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] This application provides an FPGA-based waveform generation circuit, comprising: a field-programmable gate array (FPGA) and a digital-to-analog converter (DAC); the FPGA includes a memory access module, a selection module, a control module, and a waveform generation module. Figure 1As shown, the memory access module is the accessMem module, which stores data into memory through the CPU, and then retrieves this data from memory, including configuration information and data information; the selection module is the SGenerator module, the control module is the MGenerator module, the waveform generation module is the VGenerator module, and the digital-to-analog converter chip is the DAC chip.

[0056] Specifically, the memory access module accesses memory to obtain configuration and data information corresponding to the custom waveform, and then sends the configuration and data information to the selection module, control module, and waveform generation module. In this embodiment, the configuration information includes: the number of clock pulses, the number of waveform outputs, and the waiting time; the data information includes selection module data signals, control module data signals, waveform arrays, voltage arrays, and time arrays.

[0057] The selection module generates a selection signal based on the memory access module's read end signal, configuration information, and data information, to select the control signal generated by the control module. For example... Figure 1 As shown, the selection signals generated by the SGenerator module include: the selection module clock signal SCK, the selection module latch signal SL_n, and the selection module data signal SD.

[0058] The control module generates control signals based on the selection signal, configuration information, and data information from the selection module, thereby controlling the output of the waveform generation module. For example... Figure 1 As shown, the control signals generated by the MGenerator module include: the control module clock signal MCK, the control module latch signal ML_n, and the control module data signal MD.

[0059] The waveform generation module is used to output custom waveform digital signals based on the control signals and data information from the control module.

[0060] A digital-to-analog converter chip is used to output a custom waveform based on a custom digital signal. For example... Figure 1 As shown, the final output of vcom through the DAC chip is the custom waveform.

[0061] In an exemplary embodiment, the accessMem module communicates with memory using the AXI4 protocol. This module is responsible for reading data from memory, first storing the data in a Block Random Access Memory (BRAM), and then retrieving data from the BRAM and allocating it to other modules. The data layout in memory is as follows... Figure 2As shown, Rstart is a read flag, notifying the waveform generator that it can begin reading configuration and data information. After reading is complete and waveform generation is finished, the waveform generator needs to write 1 to Rend to notify the CPU that waveform generation is complete. conflen is the length of the configuration information, in 4-byte units. datalen is the length of the data information, in 4-byte units. The configuration information consists of configuring WAIT_TIME, LOOP, and PULSES for XGenerator. The data information consists of multiple printed data arranged sequentially (one printed data set includes data needed for one waveform generated by SGenerator, one LOOP waveform generated by MGenerator, and data needed for one waveform generated by VGenerator).

[0062] The memory access functionality of the accessMem module is as follows: Figure 3 The state machine shown is a formal description of the state machine. Figure 3 In the state machine shown, IDLE, READ, RCONF, RDATA, and WRITE represent the empty state, the read flag and length information (Rstart, Rend, conflen, and datalen) state, the read configuration information state, the read data information state, and the write memory state, respectively. Rstart, Rend, conflen, and datalen represent the Rstart, Rend, conflen, and datalen values ​​read from memory, respectively. len is a counter that records the amount of data read, in units of 4 bytes. start == 1 indicates the start of memory access, end == 1 indicates the end of memory access, and bend == 1 indicates the end of BRAM read (this signal is generated by the BRAM read state machine).

[0063] The specific execution flow is as follows: The state machine is in the IDLE state. When start == 1, it transitions to the READ state. In this state, the module continuously reads the values ​​of Rstart, Rend, conflen, and datalen until Rstart is 1 and Rend is 0. The read values ​​of Rstart, Rend, conflen, and datalen are then stored in registers, and the state transitions to RCONF. In the RCONF state, the module continuously reads configuration information and stores it in BRAM. For every 4 bytes read, len is incremented by 1 until len equals conflen. The state then transitions to RDATA, and len is cleared to zero. In the RDATA state, the module reads data information and places it in BRAM. For every 4 bytes read, len is incremented by 1 until len equals datalen and bend == 1. The state then transitions to WRITE, and end is set to 1. In the WRITE state, the module writes 1 to the memory location of Rend and sets end to 0, then transitions back to IDLE.

[0064] In addition, the accessMem module also needs to read data from the BRAM and transfer it to other modules. The function of reading from the BRAM is described in the form of a state machine as follows: Figure 4 As shown, in the state machine, IDLE, READF, READD, and WAIT represent the empty state, reading configuration information, reading data information, and waiting state, respectively. `end` is the output of the memory access state machine. `bend == 1` indicates the end of reading BRAM. `rend == 1` indicates the end of reading one printout of data from BRAM. `mend == 1` indicates the end of one waveform generation (this signal is the `end` signal output by MGenerator). `gen_end == 1` indicates the end of waveform generation (this signal is the `end` signal output by SGenerator).

[0065] The specific execution flow is as follows: The state machine is in the IDLE state, and `bend` is set to 0. When `end` equals 1, indicating the end of memory read, the state transitions to READF. In this state, this module reads the configuration information for the SGenerator and MGenerator modules, stores it in registers, and transmits it to these two modules. After reading the configuration information, the state transitions to READD and `rend` is set to 0. In the READD state, this module reads the data required for printing from BRAM once, stores it in registers, and transmits it to SGenerator, MGenerator, and VGenerator. After reading, it transitions to the WAIT state and sets `rend` to 1. In the WAIT state, `rend` is set to 0. If not all data information has been read and `mend` equals 1, the state transitions to READD to continue the next printing; if all data information has been read and `gen_end` equals 1, it indicates the waveform generation is complete, the state transitions to IDLE, and `bend` is set to 1. The input / output diagram of the accessMem module is shown below. Figure 5 As shown.

[0066] The waveforms output by SGenerator and MGenerator are similar. In this embodiment, a general-purpose module XGenerator is used to illustrate the processing of both. This XGenerator module takes some configuration signals as input, and the data for these configuration signals comes from memory. This allows for convenient and flexible control of the waveforms generated by XGenerator without changing the hardware or with only minor hardware modifications. Furthermore, SGenerator and MGenerator can be instantiated from XGenerator. Some printheads transmit selection and control signals together; using a general-purpose module allows for the instantiation and combination of different modules, resulting in better versatility. In this embodiment, XCK represents SCK and MCK, XL_n represents SL_n and ML_n, and XD represents SD and MD. The waveforms of the XCK, XL_n, and XD signals are as follows: Figure 6 The part within the dashed box represents the basic waveform, followed by a repetition of that part.

[0067] The functionality of the XGenerator module is as follows Figure 7 The formal description of the state machine shown is as follows: Figure 7 In the state machine shown, IDLE, CLOCK, LATCH, and WAIT represent the empty state, clock generation state, latch state, and wait state, respectively. start == 1 indicates the start of waveform generation, and end == 1 indicates the end of waveform generation. XCK, XD, and XL_n represent the output clock, data, and latch signals, respectively. clk is a clock signal of a specific frequency. pluses and loop are counters; pluses records the number of output clock pulses, and loop records the number of times XCK, XD, and XL_n waveforms are output. PULSES, LOOP, and WAIT_TIME are waveform generation configuration information read from memory, representing the total number of output clock pulses, the total number of output waveforms, and the total wait time, respectively.

[0068] The specific execution flow is as follows: Initially, the state machine is in the IDEL state, with end set to 0. When the start signal is 1, the state transitions to the CLOCK state. At this time, XCK outputs the clk clock (XCK is low in other states), and simultaneously outputs XD, incrementing pulses by 1 on the rising edge of XCK. When the number of output clock pulses pulses reaches the required total number of pulses PLUSES, the machine must wait for the falling edge of XCK before transitioning to the LATCH state to ensure the integrity of the last high level of XCK. In the LATCH state, simply pulling XL_n low completes the latch (XL_n signal is high in other states), and on the next rising edge of the clk clock, the machine switches to the WAIT state while incrementing loop by 1. In the WAIT state, a counter counts on each rising edge of clk until it equals WAIT_TIME, at which point the wait ends. If the loop value is not equal to the total number of waveform generation counts LOOP, the state transitions to CLOCK, and waveform generation continues; if the loop value equals LOOP, it indicates the waveform generation is complete, the state transitions to the IDLE empty state, and outputs end = 1, indicating that the waveform output is complete.

[0069] In the selection module, a selection signal is generated based on the memory read end signal, configuration information, and data information of the memory access module. This process includes the following steps:

[0070] The memory access module's read end signal is used as the selection module's start signal.

[0071] The selection module generates a selection signal based on the number of clock pulses, the number of waveform outputs, the waiting time, and the selection module data signal.

[0072] In the control module, control signals are generated based on the selection signal, configuration information, and data information from the selection module. This process includes the following steps:

[0073] The inverted value of the selection module latch signal in the selection signal is used as the start signal of the control module.

[0074] The control module generates control signals based on the number of clock pulses, the number of waveform outputs, the waiting time, and the control module data signals.

[0075] The input and output of the XGenerator module are as follows: Figure 8 As shown, by changing WAIT_TIME, LOOP, and PULSES, the waiting time, the number of waveform outputs, and the number of clock pulses can be flexibly controlled to form different waveforms. Different instances of XGenerator can then be created to implement combinations of different modules.

[0076] For the VGenerator module, three arrays are used to describe the waveform to be generated. These three arrays are: a waveform array SEQ describing the waveform to be generated (falling edge / rising edge / horizontal waveform), an array VSEQ describing the voltage at the falling or rising edge, and a time array TSEQ describing the duration of the falling, rising, or horizontal waveform. In this way, VGenerator can generate various forms of waveforms without changing the hardware, enhancing the versatility of the waveform generator.

[0077] The VGenerator module takes the three arrays mentioned above as input: SEQ, VSEQ, and TSEQ. SEQ consists of the numbers 0 / 1 / 2 / 3, where 0 represents a falling edge, 1 represents a stable horizontal state, 2 represents a rising edge, and 3 represents the end. VSEQ is a voltage array, where each value represents the voltage at the next point in the falling / rising / horizontal waveform to be generated. TSEQ is a time array, where each value represents the duration of the falling / rising / horizontal waveform to be generated. These three arrays together describe a waveform.

[0078] The functionality of the VGenerator module is as follows: Figure 9 The formal description of the state machine shown is as follows: Figure 9 In the state machine shown, IDLE, FALL, FLAT, and RAISE represent the empty state, falling edge state, horizontal steady state, and rising edge state, respectively. start == 1 indicates the start of waveform generation. end == 1 indicates the end of waveform generation. component represents the value pointed to by the current SEQ index.

[0079] The specific execution flow is as follows: Initially, the state machine is in the IDLE state, and end is set to 0. When start == 1, if component == 0, it transitions to the FALL state, based on the value pointed to by the VSEQ index and TSEQ; if component == 2, it transitions to the RAISE state. In the FALL or RAISE state, if the output's falling or rising edge ends and component == 2, it transitions to the FLAT state. Similarly, in the FLAT state, when the output's horizontal stable state ends, if component == 1, the state transitions to RAISE; if component = 0, the state transitions to FALL. When the state is FALL, FLAT, or RAISE, if the output's falling edge, horizontal, or rising edge waveform ends and component == 3, the state transitions to IDLE, and end = 1 is output. The falling edge, rising edge, and horizontal waveform are all generated based on the value pointed to by the current index of VSEQ and the current index of TSEQ.

[0080] In the waveform generation module, a custom waveform digital signal is output based on the control signals and data information from the control module. This includes the following steps:

[0081] The inverted value of the control module latch signal in the control signal is used as the start signal of the waveform generation module.

[0082] The waveform generation module outputs a custom waveform digital signal based on the waveform array, voltage array, and time array.

[0083] The process by which the VGenerator module and the DAC chip jointly generate the vcom waveform is as follows: Figure 10 As shown. By adjusting the values ​​in SEQ, VSEQ, and TSEQ, VGenerator can flexibly output different waveforms to adapt to the different waveforms of different printheads and ink droplets.

[0084] In an exemplary embodiment, the connection relationship between the modules in the waveform generation circuit is shown in the diagram below. Figure 11 As shown, the start signal input to the accessMem module can be a signal generated by a switch. When the start signal is 1, the system starts working, and the processor writes data to memory. Figure 2 The accessMem module reads the data from memory and stores it in BRAM. Then, it reads data from BRAM and transmits it to SGenerator, MGenerator, and VGenerator respectively. After each read of data for printing, it notifies the SGenerator module to generate a waveform (via the rend signal). The SGenerator generates a basic waveform (e.g., ...). Figure 6 The SGenerator will then notify the MGenerator module to generate a waveform (by inverting the SL_n signal). Once the MGenerator has generated the LOOP waveforms specified in the configuration, it will notify accessMem that waveform generation is complete (via the end signal generated by the SGenerator). After generating a basic waveform, the MGenerator will notify the VGenerator module to generate a waveform (by inverting the ML_n signal). Once the VGenerator has generated the LOOP waveforms specified in the configuration, it will notify accessMem to continue reading the data needed for the next waveform generation (via the end signal generated by the MGenerator). However, the LOOP waveforms generated by the MGenerator must be completed before the SGenerator's waiting time expires. Upon receiving the notification from the MGenerator, the VGenerator module will begin generating the waveforms required by the DAC, but these waveforms must be completed before the MGenerator's waiting time expires.

[0085] In one exemplary embodiment, such as Figure 12 The flowchart shown illustrates an FPGA-based waveform generation method, comprising the following steps:

[0086] A1. The memory access module accesses the memory to obtain the configuration information and data information corresponding to the custom waveform, and then sends the configuration information and data information to the selection module, control module, and waveform generation module. Specifically, in this embodiment, the configuration information includes: the number of clock pulses, the number of waveform outputs, and the waiting time; the data information includes the selection module data signal, the control module data signal, the waveform array, the voltage array, and the time array.

[0087] A2. The selection module generates a selection signal based on the memory access module's read end signal, configuration information, and data information, to select the control signal generated by the control module. In this embodiment, step A2 specifically includes the following steps:

[0088] A21. Use the memory read end signal of the memory access module as the start signal for the selection module.

[0089] A22. The selection module generates a selection signal based on the number of clock pulses, the number of waveform outputs, the waiting time, and the selection module data signal. The selection signal includes the selection module clock signal, the selection module latch signal, and the selection module data signal.

[0090] A3. The control module generates a control signal based on the selection signal, configuration information, and data information from the selection module, thereby controlling the output of the waveform generation module. In this embodiment, step A3 specifically includes the following steps:

[0091] A31. The inverted value of the selection module latch signal in the selection signal is used as the start signal of the control module.

[0092] A32. The control module generates control signals based on the number of clock pulses, the number of waveform outputs, the waiting time, and the control module data signals. The control signals include: the control module clock signal, the control module latch signal, and the control module data signal.

[0093] A4. The waveform generation module outputs a custom waveform digital signal based on the control signals and data information from the control module. In this embodiment, step A4 specifically includes the following steps:

[0094] A41. The inverted value of the control module latch signal in the control signal is used as the start signal of the waveform generation module.

[0095] A42. Using the waveform generation module, output a custom waveform digital signal based on the waveform array, voltage array, and time array.

[0096] A5. The digital-to-analog converter chip outputs a custom waveform based on the custom waveform digital signal.

[0097] The solution provided by this method is similar to the solution described in the circuit above. Therefore, the specific limitations of the waveform generation method embodiment provided here can be found in the limitations of the waveform generation circuit above, and will not be repeated here.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An FPGA-based waveform generation circuit, characterized by, The application relates to a self-defined waveform generation system. The system comprises: a field programmable gate array and a digital-to-analog conversion chip; the field programmable gate array comprises a memory access module, a selection module, a control module and a waveform generation module; the memory access module is used for accessing a memory to obtain configuration information and data information corresponding to a self-defined waveform, and transmitting the configuration information and the data information to the selection module, the control module and the waveform generation module; the memory access module is responsible for reading data from the memory, storing the data in a block random access memory (BRAM) and then distributing the data from the BRAM to other modules; the function of reading the BRAM is described in the form of a state machine, wherein IDLE, READF, READD and WAIT are used to respectively represent an idle state, reading configuration information, reading data information and a waiting state; when reading the memory ends, the state machine is transferred from the IDLE state to the READF state; when reading the configuration information ends, the state machine is transferred from the READF state to the READD state; when reading the BRAM data ends, the state machine is transferred from the READD state to the WAIT state; in the WAIT state, if all the data information is not read and it is judged that a waveform generation ends once through a mend signal, the state is transferred to the READD state to continue the next printing; if all the data information is read and it is judged that the waveform generation ends through a gen_end signal, the state is transferred to the IDLE state and the reading of the BRAM is marked as ending by setting bend to 1; the configuration information comprises the number of clock pulses, the number of waveform outputs and the waiting time; the data information comprises selection module data signals, control module data signals, a waveform array for describing a waveform to be generated currently, a voltage array for describing the end of a falling or rising edge and a time array for describing the duration of a falling edge, a rising edge or a horizontal waveform; wherein the waveform comprises a falling edge, a rising edge or a horizontal waveform; the selection module is used for generating selection signals according to the reading memory end signal of the memory access module, the configuration information and the data information, so as to select control signals generated by the control module; the control module is used for generating control signals according to the selection signals of the selection module, the configuration information and the data information, so as to control the output of the waveform generation module; the waveform generation module is used for outputting self-defined waveform digital signals according to the control signals of the control module and the data information; the digital-to-analog conversion chip is used for outputting a self-defined waveform according to the self-defined waveform digital signals; when starting to work, the memory access module reads the printing data from the memory and stores the data in the BRAM, and then reads the data from the BRAM and respectively transmits the data to the selection module, the control module and the waveform generation module; the memory access module informs the selection module to generate a waveform every time the printing data is read completely, the selection module informs the control module to generate a waveform every time a basic waveform is generated, and the memory access module is informed to end the waveform generation when the selection module generates the waveforms for LOOP times set in the configuration information. The control module generates a basic waveform and then notifies the waveform generation module to generate a waveform, and when the control module generates the LOOP times set in the configuration information, the memory access module is notified to continue reading data required for the next waveform generation; wherein the LOOP times of waveforms generated by the control module need to be completed before the waiting time of the selection module ends; the waveform generation module starts to generate the waveform required by the DAC after receiving the notification of the control module, but the waveform needs to be generated and completed before the waiting time of the control module ends.

2. The FPGA-based waveform generation circuit of claim 1, wherein, The selection signal includes: The selection module clock signal, the selection module latch signal and the selection module data signal; the control signal includes: the control module clock signal, the control module latch signal and the control module data signal.

3. The FPGA-based waveform generation circuit of claim 2, wherein, According to the end of memory reading signal of the memory access module, the configuration information and the data information, the selection signal is generated, specifically including: The end of memory reading signal of the memory access module is used as the start signal of the selection module; Through the selection module, the selection signal is generated according to the clock pulse number, the waveform output times, the waiting time and the selection module data signal.

4. The FPGA-based waveform generation circuit of claim 3, wherein, According to the selection signal of the selection module, the configuration information and the data information, the control signal is generated, specifically including: The inverse value of the selection module latch signal in the selection signal is used as the start signal of the control module; Through the control module, the control signal is generated according to the clock pulse number, the waveform output times, the waiting time and the control module data signal.

5. The FPGA-based waveform generation circuit of claim 4, wherein, According to the control signal of the control module and the data information, the self-defined waveform digital signal is output, specifically including: The inverse value of the control module latch signal in the control signal is used as the start signal of the waveform generation module; Through the waveform generation module, the self-defined waveform digital signal is output according to the waveform array, the voltage array and the time array.

6. A waveform generation method based on FPGA, characterized by, Including: The memory access module accesses the memory to obtain the configuration information and the data information corresponding to the self-defined waveform, and sends the configuration information and the data information to the selection module, the control module and the waveform generation module; The memory access module is responsible for reading data from the memory, storing the data into the block random access first, and then taking the data from the block random access for use by other modules; the function of reading the block random access is described in the form of a state machine, in which IDLE, READF, READD and WAIT are used to represent the idle state, reading configuration information, reading data information and waiting state respectively; when the memory reading is completed, the state machine is transferred from the IDLE state to the READF state; when the configuration information reading is completed, the state machine is transferred from the READF state to the READD state; When reading BRAM data ends, the state machine is transferred from the READD state to the WAIT state; in the WAIT state, if all data information is not read and a waveform generation is determined to end through the mend signal, the state is transferred to the READD state to continue the next printing; if all data information is read and the waveform generation is determined to end through the gen_end signal, the state is transferred to the IDEL state and the bend is set to 1 to mark the end of reading BRAM; the configuration information includes the number of clock pulses, the number of waveform outputs and the waiting time; the data information includes the selection module data signal, the control module data signal, the waveform array describing the current waveform to be generated, the voltage array describing the falling or rising edge end and the time array describing the duration of the falling edge, the rising edge or the horizontal waveform; wherein the waveform includes the falling edge / rising edge / horizontal waveform; The selection module generates a selection signal according to the read memory end signal of the memory access module, the configuration information and the data information, to select the control signal generated by the control module; The control module generates a control signal according to the selection signal of the selection module, the configuration information and the data information, to control the output of the waveform generation module; The waveform generation module outputs a custom waveform digital signal according to the control signal of the control module and the data information; The digital-to-analog conversion chip outputs a custom waveform according to the custom waveform digital signal; When starting to work, the memory access module reads the printing data from the memory and stores it in the BRAM, and then reads the data from the BRAM and transmits it to the selection module, the control module and the waveform generation module respectively; The memory access module notifies the selection module to generate a waveform every time it reads the printing data once; the selection module notifies the control module to generate a waveform every time it generates a basic waveform once; when the selection module generates the LOOP waveforms set in the configuration information, it notifies the memory access module that the waveform generation is completed; The control module notifies the waveform generation module to generate a waveform every time it generates a basic waveform once; when the control module generates the LOOP waveforms set in the configuration information, it notifies the memory access module to continue to read the data required for the next waveform generation; wherein the LOOP waveforms generated by the control module need to be completed before the waiting time of the selection module ends; the waveform generation module starts to generate the waveform required by the DAC after receiving the notification of the control module, but the waveform needs to be generated and completed before the waiting time of the control module ends.

7. The FPGA-based waveform generation method of claim 6, wherein, The selection module generates a selection signal according to the read memory end signal of the memory access module, the configuration information and the data information, to select the control signal generated by the control module, specifically including: The read memory end signal of the memory access module is used as the start signal of the selection module; The selection module generates a selection signal according to the clock pulse number, the waveform output number, the waiting time and the selection module data signal; the selection signal includes a selection module clock signal, a selection module latch signal and a selection module data signal.

8. The FPGA-based waveform generation method of claim 7, wherein, The control module generates a control signal according to the selection signal of the selection module, the configuration information and the data information, to control the output of the waveform generation module, specifically including: The inverse value of the selection module latch signal in the selection signal is taken as the start signal of the control module; The control module generates a control signal according to the clock pulse number, the waveform output number, the waiting time and the control module data signal; the control signal includes a control module clock signal, a control module latch signal and a control module data signal.

9. The FPGA-based waveform generation method of claim 8, wherein, The waveform generation module outputs a self-defined waveform digital signal according to the control signal of the control module and the data information, specifically including: The inverse value of the control module latch signal in the control signal is taken as the start signal of the waveform generation module; The waveform generation module outputs a self-defined waveform digital signal according to the waveform array, the voltage array and the time array.

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