A parameterized controller that reduces the number of pins used by DFT

Abstract

The present invention belongs to the field of chip testing, and relates to a parameterized controller that can reduce the number of pins used by DFT, which includes a PR_DFT control module, a Clock_ctrl clock control module, and a Reset_ctrl reset control module; on the output side of the PR_DFT control module, control signals for reset control logic and clock control logic are generated, and scan chain signals for compressor decompressors are generated; the Reset_ctrl reset control module performs a DC test on the reset signal by controlling a function reset; the Clock_ctrl clock control module selects whether to add AC test-related logic. The present invention can be freely applied in various test modes, without the need for a traditional JTAG control interface, and without too many DFT-related pins; the controller has a small number of pins and a low hardware cost.

Description

Technical Field

[0001] The invention relates to a parameterized controller capable of reducing the number of pins used by DFT, belonging to the technical field of chip testing. Background Art

[0002] Now, with the increasing complexity of integrated circuits and the increasingly advanced processes, the controllability and observability coefficients of circuits have decreased, circuit testing has become very complex and difficult, and the cost of test generation has also increased exponentially. Traditional testing methods have been unable to fully and effectively verify the correctness of complex integrated circuit design and manufacturing, leading to the emergence of testability design methods. The core idea of ​​testability design methods is to consider testing issues at the beginning of design, and to improve the controllability and observability of circuits by appropriately adding some circuits specifically used for testing, thereby reducing the difficulty and complexity of circuit testing, improving circuit testing efficiency, and reducing testing costs.

[0003] DFT technology improves the controllability and observability of circuits by introducing test logic in the design phase, thereby reducing the difficulty and cost of testing. In DFT, test logic usually requires a large number of chip pins, which increases design complexity and cost. Reducing the number of pins used by DFT can significantly reduce the manufacturing and testing costs of chips.

[0004] Currently, most of the methods for reducing pins are focused on multiplexing functional pins, but this method also uses a lot of pins because it involves JTAG configuration pins and pins used by compression logic.

[0005] The current mainstream chip design is based on IJTAG for DFT control, which requires the chip to have additional JTAG pins and pins required for compression logic.

[0006] If the chip itself has very few pins, then this method obviously does not conform to the original intention of DFT.

[0007] There are also related technologies being developed to reduce pins in this technical field. However, for designs with complex internal logic, a large number of clocks, and reset module testing requirements, the existing technologies are clearly not sufficient to handle these tests.

[0008] For designs with complex internal logic, a large number of clocks, and test requirements, not only the most basic DC test but also AC test is required. Existing technologies cannot handle AC tests related to functional clocks and tests related to reset logic modules, resulting in incomplete testing, a large loss in coverage, and possibly a low chip yield.

[0009] Based on this, the present invention is proposed. Summary of the invention

[0010] In order to be compatible with AC and DC tests and to minimize the number of logics inserted by DFT according to design requirements, the present invention provides a parameterized controller that can reduce the number of pins used by DFT. The specific technical solution is as follows:

[0011] A parameterized controller capable of reducing the number of pins used by a DFT includes a PR_DFT control module, a Clock_ctrl clock control module and a Reset_ctrl reset control module;

[0012] On the output side of the PR_DFT control module, control signals for the reset control logic and the clock control logic are generated, as well as scan chain signals for the compressor and decompressor;

[0013] The reset control module resets through the control function and performs a DC test on the reset signal;

[0014] The Clock_ctrl clock control module selects whether to add AC test related logic.

[0015] As a further improvement, the PR_DFT control module includes a state machine, a decoder and a setting parameter register, wherein the state machine generates various states according to the test requirements; the decoder performs encoding and decoding actions in a specific state; the decoder generates an enable signal and a selection signal required by the peripheral circuit;

[0016] The setting parameter register latches a specific value according to the test environment, the value is identified from the control vector by the decoder, and is output to the setting parameter register and latched therein;

[0017] The reset and clock of the decoder and the setting parameter register are uniformly generated and controlled by the state machine;

[0018] During the test, the control vector enters the controller through scan_channel_input, and the control vector will be received by the decoder and the state machine at the same time;

[0019] The state machine parses the control variable value according to the content of the test vector and the content of the setting parameter register, enters the corresponding state, and outputs the state value to the decoder;

[0020] The decoder parses the shifted-in control vector and the state signal of the state machine in a specific state and generates a corresponding signal.

[0021] As a further improvement, the workflow of the state machine includes the following steps:

[0022] Step 1: Determine whether to perform DFT test according to the high and low levels of the test_mode signal;

[0023] Step 2: During the DFT test, determine whether to start PRE_SHIFT according to DFT_BEGIN in the parameter register.

[0024] Step 3: After the PRE_SHIFT count is full, directly enter SHIFT;

[0025] Step 4. After SHIFT is completed, enter POST_SHIFT;

[0026] Step 5: In the POST_SHIFT state, it will determine whether to test the technology. If it is not finished, it will determine whether to capture data;

[0027] Step 6: After completing steps 1 to 5, a test vector is completed.

[0028] In a further improvement, the decoder includes a compare module, a shift_counter module, a capture_counter module and a vector_counter module;

[0029] The compare module is used to realize the comparison of the control vector, and judge whether the value coming from scan_channel is a parameter value, so as to judge whether to write into the setting parameter register;

[0030] The shift_counter module is a shift state counter, used to count the number of cycles in the shift state;

[0031] The capture_counter module is a capture state counter, which is used to count the number of cycles in the capture state;

[0032] The vector_counter module is a vector counter used to count the number of vectors in the pattern;

[0033] The compare module receives pattern data from the machine, finds configuration data after comparison, and combines the configuration data with the state signal to generate a count enable signal for the connected module; when the count is full, a full high-level signal is returned.

[0034] As a further improvement, the compare module implements the comparison of the state signal, thereby generating a DFT-related signal and a counter enable signal.

[0035] As a further improvement, during AC testing, the controller that can reduce the number of pins used by DFT can shield the accidental reset of the logic to be tested by Pattern by pulling Reset_disable high during AC testing.

[0036] or,

[0037] During DC testing, Reset_disable is always in a low state; when the Pattern is shifted, Scan_en is in a high level state;

[0038] In the DC Capture phase, Scan_en and Reset_disable are both in a low level state;

[0039] or,

[0040] During DFT testing, the OR gate will block the transmission of Func_reset_gen, so that Func_reset_after_dft is controlled by DFT related logic.

[0041] Beneficial effects of the present invention:

[0042] 1. The parameterized controller capable of reducing the number of pins used by DFT described in the present invention can be freely applied in various test modes, does not require a traditional JTAG control interface, and does not require too many DFT-related pins; the controller has a small number of pins and a low hardware cost.

[0043] 2. Clock_ctrl clock control module can choose whether to add AC test related logic. If only DC test is performed, some unused logic circuits can be reduced, saving hardware costs.

[0044] 3. The PR_DFT control module can generate a clock enable signal configured according to the parameters, and can configure the relevant pulse width to achieve the purpose of controllable number of clock pulses.

[0045] 4. The PR_DFT control module can generate a clock selection signal, so that the shift clock and capture clock can be freely selected according to the pattern requirements. It can also generate a functional clock pulse enable signal during AC testing.

[0046] 5. The Reset_ctrl reset control module can control the functional reset and perform DC test on the reset signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A test hardware architecture diagram of a parameterized controller capable of reducing the number of pins used by DFT;

[0048] Figure 2 This is the structure diagram of the Reset_ctrl reset control module;

[0049] Figure 3 This is the structural diagram of the Clock_ctrl clock control module;

[0050] Figure 4 This is the structural diagram of the PR_DFT control module;

[0051] Figure 5 It is the workflow diagram of the state machine;

[0052] Figure 6 This is the structural diagram of the decoder. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] Definitions of Abbreviations and Key Terms

[0055] DFT: Design for Testability. This refers to adding some specific design techniques to integrated circuit (IC) design to make it easier to test during manufacturing and debugging.

[0056] DC: Usually refers to testing at lower frequencies (such as 20MHz to 100MHz) to test for stuck-at defects.

[0057] AC: The full name is At-speed Clock, which is a test that the clock frequency is consistent with the actual operating frequency of the chip. It is usually used to test transition defects.

[0058] ICG: Integrated Clock Gating. ICG is a low-power design technique that reduces power consumption by turning off the clock signal when it is not needed.

[0059] FSM: Finite State Machine. FSM is an abstract model used to design and implement sequential logic circuits.

[0060] Free_running_clock: Free clock; refers to a clock signal that runs unconditionally after power-on.

[0061] PR-DFT: Pin Reduced DFT, refers to a DFT controller that reduces the number of pins.

[0062] Para_DC: Abbreviation of parameter. It is used to distinguish between DC and AC designs in the present invention. Para_DC here means the design is used in DC only test.

[0063] Para_AC: Same as above, except that Para_AC here represents the design used in AC testing.

[0064] PLL: Phase-Locked Loop. PLL is a control system that locks the phase of the output signal to the phase of the input signal.

[0065] ACK: Acknowledgment. This is a signal or message used to confirm that a data packet or command has been successfully received.

[0066] Ctrl: Control. It can be used to describe control signals, control pins or control registers, etc.

[0067] Shift: In the DFT field, it refers to the process of shifting the test vector to the test circuit.

[0068] Capture: In the field of DFT, it refers to the process by which a test circuit captures the response caused by a test vector.

[0069] Reg: register, register.

[0070] TEST_MODE: A signal set to put the chip into test mode. When it is at a high level, the chip enters the test function.

[0071] Scan_en: abbreviation of scan enable. Scan_en is pulled high when shifting data and pulled low when capturing data.

[0072] Pattern: In DFT (Design for Testability), pattern usually refers to test vectors, which are used to verify the correctness and manufacturability of chip design.

[0073] JTAG: Joint Test Action Group; is a standard protocol widely used in electronic design and testing, formally known as the IEEE 1149.1 standard.

[0074] IJTAG: Internal JTAG, also known as the IEEE 1687 standard, is an extension of traditional JTAG (IEEE 1149.1).

[0075] OSC: Oscillator; a circuit or device that can generate a periodic waveform (such as a sine wave, square wave, etc.).

[0076] Clock_ctrl: The abbreviation of Clock control, which is a circuit or device used for clock control.

[0077] Reset_ctrl: The abbreviation of Reset control, which is a circuit or device used for reset control.

[0078] Scan_channel_output: It is the test port that outputs the test vector to the machine when the chip is doing DFT testing.

[0079] Scan_channel_input: It is the input test vector port that the machine gives to the chip when the chip is performing DFT testing.

[0080] free_running_clock: refers to the clock that can run freely when the chip is working.

[0081] Func_reset: Reset signal of the internal functional logic of the chip.

[0082] OCC: stands for On-chip Clock Controllers. Example 1

[0083] The test hardware architecture of a parameterized controller (hereinafter referred to as the controller) capable of reducing the number of pins used by DFT according to the present invention is as follows: Figure 1 As shown:

[0084] The controller includes a PR_DFT control module, a Clock_ctrl clock control module, and a Reset_ctrl reset control module.

[0085] The entire test circuit only needs a dedicated chip pin for teset_mode to distinguish between test mode and functional mode. Functional mode refers to the mode when the chip is working normally, not test mode.

[0086] Scan_channel_output, scan_channel_input and free_running_clock pins can be shared with functional pins. free_running_clock can also be the reference clock generated by the internal OSC. Func_reset can be introduced by an external pin or generated inside the chip.

[0087] On the output side of the PR_DFT control module, control signals for the reset control logic and clock control logic are generated, as well as scan chain signals for the compressor and decompressor.

[0088] After the above processing, the clock, reset and scan chains are connected to the logic to be tested respectively.

[0089] exist Figure 1 middle:

[0090] Reset_disable: used to disable the reset signal.

[0091] Func_reset_gen: refers to the reset signal generated after the logic under test processes the external reset signal.

[0092] Func_reset_after_dft: refers to the reset signal output by DFT after processing the functional reset signal.

[0093] Reset generator: Reset_ctrl reset control module, which can process functional reset signals.

[0094] Scan_en: short form of scan enable, pulled high when DFT is in pattern input state.

[0095] Scan_output: It is the port for the PR_DFT control module to output the pattern, and will feed the processed pattern into the compression / decompression logic.

[0096] Scan_input: It is the port that the compression / decompression logic outputs to the PR_DFT control module, and it will give the test data captured inside the logic under test to the PR_DFT control module.

[0097] Compression / decompression logic: can decompress the pattern from scan_output to form data on multiple scanchains. Can compress the data input by scan_chain to form data on one scan input.

[0098] shift_capture_select: It is the selection signal of the multiplexer, which can select the shift clock or the capture clock.

[0099] capture_en: capture enable signal, which will be pulled high during the capture phase.

[0100] Shift_en: The shift enable signal, which will be pulled high during the shift phase.

[0101] PLL_clock: The clock output by the phase-locked loop.

[0102] Pin-reduced DFT Controller: is the full name of the PR_DFT control module.

[0103] Clock: The functional clock required by the logic under test.

[0104] Scan_chain_out{0…n}: Scan chain ports generated by compression / decompression logic, the number can be selected.

[0105] Scan_chain_in{0…n}: Scan chain output port in the logic under test, through which the captured test data is passed to the compression / decompression logic.

[0106] When DFT works normally, the Reset_ctrl module will further process the reset signal of the logic under test to achieve the purpose of DFT being able to test the reset signal. Example 2

[0107] Implementation of reset control module:

[0108] The Reset_ctrl reset control module resets the control function to achieve the purpose of control during DFT. Figure 2 As shown, during AC testing, the controller will pull Reset_disable high to prevent Pattern from causing an unexpected reset of the logic under test during AC testing.

[0109] In the case of DC testing, Reset_disable will always be in a low state. Therefore, when the pattern is shifted, Scan_en will be in a high level state, and the functional reset will also be in a shielded state. This operation allows the test vector to be smoothly shifted to each scan unit.

[0110] In the Capture phase of the DC test, Scan_en and Reset_disable are both in a low level state. In this way, the functional reset depends on the test vector value shifted in. In this way, it is possible to test whether the reset signal in the logic under test has any faults.

[0111] If in functional mode, the reset signal in the logic under test is connected to the functional reset terminal.

[0112] During DFT testing, the OR gate will block the transmission of Func_reset_gen, so that Func_reset_after_dft is controlled by the DFT related logic to achieve the purpose of testing the reset signal. In functional mode, Func_reset_after_dft is controlled by the Func_reset_gen signal. Example 3

[0113] Implementation of Clock_ctrl clock control module:

[0114] like Figure 3 As shown, the Clock_ctrl clock control module has parameterized settings. It is necessary to know the test requirements of the entire chip before doing DFT design. If only DC testing is required, the circuit shown in para_DC can be instantiated; if AC testing is required, the circuit shown in para_AC can be instantiated. This operation can minimize the insertion of test logic.

[0115] exist Figure 3 In the example, Shift_en is connected to the enable terminal of ICG, and capture_en is connected to the enable terminal of another ICG.

[0116] The free_running_clock is connected to the clock terminals of the two ICGs. The clock can be intercepted in a specific mode during normal operation.

[0117] Figure 3 In the OCC circuit, the input is capture_en and the output clock of PLL. During AC testing, the required functional clock can be choppered.

[0118] Clock Selector 1 ( Figure 3 The module corresponding to "1" in the clock selector 2 is selected as Shift_capture_select, and the input ends are from the outputs of ICG and OCC. Figure 3 The module corresponding to "2" in the figure) selects the signal Test_mode, and the input ends are the normal functional clock and the test clock. Example 4

[0119] The PR_DFT control module based on state machine design, such as Figure 4 As shown, the PR_DFT control module includes a state machine, a decoder and a parameter setting register. The state machine generates various states according to the test requirements. The decoder performs encoding and decoding actions in a specific state; the decoder generates the enable signal and selection signal required by the peripheral circuit.

[0120] The setting parameter register latches a specific value according to the test environment. The value is identified from the control vector by the decoder and output to the setting parameter register and latched therein.

[0121] The reset and clock of the decoder and setting parameter registers need to be uniformly generated and controlled by the state machine.

[0122] During the test, the control vector enters the controller through scan_channel_input, and the control vector will be received by the decoder and the state machine at the same time.

[0123] The state machine will parse the control variable value according to the content of the test vector and the content of the setting parameter register, enter the corresponding state, and output the state value to the decoder.

[0124] The decoder will analyze the shifted control vector and the state signal of the state machine in a specific state and generate corresponding signals. For example, the shift state generates the shift_en signal and pulls down the shift_capture_select signal, thereby outputting the shift clock. The capture state generates the capture_en signal and pulls up the shift_capture_select signal, thereby outputting the capture clock.

[0125] The Capture state in the AC test is similar to that in the DC test, but the decoder selectively controls the pulse width of capture_en according to the state of the state machine, thereby controlling the number of output clock pulses. Example 5

[0126] In Example 4, Figure 5 As shown, the workflow of the state machine includes the following steps:

[0127] Step 1: Determine whether to perform DFT test according to the high and low levels of the test_mode signal;

[0128] Step 2: During the DFT test, determine whether to start PRE_SHIFT according to DFT_BEGIN in the parameter register.

[0129] Step 3: After the PRE_SHIFT count is full, directly enter SHIFT;

[0130] Step 4. After SHIFT is completed, enter POST_SHIFT;

[0131] Step 5: In the POST_SHIFT state, it will determine whether to test the technology. If it is not finished, it will determine whether to capture data;

[0132] Step 6: After completing the above operations, a test vector is completed.

[0133] exist Figure 5 middle:

[0134] START: One of the state machine states, indicating that the state machine starts working.

[0135] TEST_MODE: Test mode status. When test_mode is high, TEST_MODE will be judged as YES and enter the next state.

[0136] RESET: Reset state, after the reset is completed, it will enter the next state.

[0137] DFT_BEGIN: Start executing DFT test.

[0138] PRE_SHIFT: One of the state machine states. Before entering the SHIFT state, the system needs to be configured in the current state.

[0139] SHIFT: Shift state. When PRE_SHIFT is completed, this state is entered. In this state, the pattern can be shifted to the logic to be tested.

[0140] SHIFT_END: ​​Shift stop state, in this state it is determined whether the shift stops.

[0141] POST_SHFIT: After confirming that the SHIFT state has stopped, enter the POST_SHIFT state.

[0142] TEST_DONE: Test completion status, in which it is determined whether the test is completed.

[0143] NO_CAPTURE: The capture state is disabled. In this state, it is determined whether to enter the capture state.

[0144] CAPTURE: Capture state, in which the scanning unit captures test data.

[0145] CAPTURE_DONE: Capture completion status. In this status, it is determined whether the capture process is completed.

[0146] TEST_END: ​​Test end state. Entering this state means the current pattern test is finished. Example 6

[0147] In Example 4, the structure of the decoder is as follows Figure 6 As shown, the decoder includes a compare module, a shift_counter module, a capture_counter module, and a vector_counter module.

[0148] 1. The compare module mainly realizes the comparison of control vectors, determines whether the value coming from scan_channel is the parameter value, and thus determines whether to write it into the setting parameter register;

[0149] scan_channel: A general term for scan_channel_input and scan_channel_output. The scan_channel mentioned in the text includes scan_channel_input and scan_channel_output.

[0150] 2. The compare module implements the comparison of state signals, thereby generating DFT-related signals (such as shift_en, capture_en, test_mode, reset_disable, scan_input, scan_output, shift_capture_select, etc.) and counter enable signals.

[0151] exist Figure 6 middle:

[0152] state: The current state of the state machine.

[0153] shift_counter: Shift state counter, capable of counting the number of cycles in the shift state.

[0154] capture_counter: Capture state counter, which can count the number of cycles in the capture state.

[0155] vector_counter: A vector counter that can count the number of vectors in a pattern.

[0156] compare: comparator, capable of parsing scan_channel data.

[0157] ACK: Abbreviation for Acknowledgment, which means confirmation signal.

[0158] Reg_read_write: Read and write control of setting parameter registers.

[0159] full: counter slow counting flag signal.

[0160] DFT_signal: refers to the collection of signals when DFT is working, including shift_en, capture_en, test_mode, reset_disable, scan_input, scan_output, shift_capture_select, etc.

[0161] Counter_en: refers to the count enable signal of the vector_counter module.

[0162] The compare module receives the pattern data from the machine and finds the configuration data after comparison. Combined with the configuration data, the state signal generates the count enable signal of the connected module. When the count is full, a full high-level signal is returned.

[0163] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A parameterized controller capable of reducing the number of pins used by a DFT, characterized in that: Including PR_DFT control module, Clock_ctrl clock control module and Reset_ctrl reset control module; On the output side of the PR_DFT control module, control signals for the reset control logic and the clock control logic are generated, as well as scan chain signals for the compressor and decompressor; The reset control module resets through the control function and performs a DC test on the reset signal; The Clock_ctrl clock control module selects whether to add AC test related logic; The PR_DFT control module includes a state machine, a decoder and a setting parameter register. The state machine generates various states according to the test requirements; the decoder performs encoding and decoding actions in a specific state; the decoder generates an enable signal and a selection signal required by the peripheral circuit; The setting parameter register latches a specific value according to the test environment, the value is identified from the control vector by the decoder, and is output to the setting parameter register and latched therein; The reset and clock of the decoder and the setting parameter register are uniformly generated and controlled by the state machine; During the test, the control vector enters the controller through scan_channel_input, and the control vector will be received by the decoder and the state machine at the same time; The state machine parses the control variable value according to the content of the test vector and the content of the setting parameter register, enters the corresponding state, and outputs the state value to the decoder; The decoder parses the shifted control vector and the state signal of the state machine in a specific state and generates a corresponding signal; The workflow of the state machine includes the following steps: Step 1: Determine whether to perform DFT test according to the high and low levels of the test_mode signal; Step 2: During the DFT test, determine whether to start PRE_SHIFT according to DFT_BEGIN in the parameter register. Step 3: After the PRE_SHIFT count is full, directly enter SHIFT; Step 4. After SHIFT is completed, enter POST_SHIFT; Step 5: In the POST_SHIFT state, it will determine whether to test the technology. If it is not finished, it will determine whether to capture data; Step 6: After completing steps 1 to 5, a test vector is completed.

2. A parameterized controller capable of reducing the number of pins used by DFT according to claim 1, characterized in that: The decoder comprises a compare module, a shift_counter module, a capture_counter module and a vector_counter module; The compare module is used to realize the comparison of the control vector, and judge whether the value coming from scan_channel is a parameter value, so as to judge whether to write into the setting parameter register; The shift_counter module is a shift state counter, used to count the number of cycles in the shift state; The capture_counter module is a capture state counter, which is used to count the number of cycles in the capture state; The vector_counter module is a vector counter used to count the number of vectors in the pattern; The compare module receives pattern data from the machine, finds configuration data after comparison, and combines the configuration data with the state signal to generate a count enable signal for the connected module; when the count is full, a full high-level signal is returned.

3. A parameterized controller capable of reducing the number of pins used by DFT according to claim 2, characterized in that: The compare module implements the comparison of the state signal, thereby generating a DFT-related signal and a counter enable signal.

4. A parameterized controller capable of reducing the number of pins used by DFT according to claim 2, characterized in that: During AC testing, the controller that can reduce the number of pins used by DFT can shield the unexpected reset of the pattern to the logic under test by pulling Reset_disable high during AC testing. or, During DC testing, Reset_disable is always in a low state; when the Pattern is shifted, Scan_en is in a high level state; In the DC Capture phase, Scan_en and Reset_disable are both in a low level state; or, During DFT testing, the OR gate will block the transmission of Func_reset_gen, so that Func_reset_after_dft is controlled by DFT related logic.

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