Cable early fault intelligent detection system

Abstract

The invention discloses a cable early fault intelligent detection system, which is characterized in that a hybrid architecture of an FPGA (Field Programmable Gate Array) and a domestic D2000CPU (Central Processing Unit) is combined, and efficient data processing and fault identification are realized. According to the system, cable current signals are accurately acquired through the FPGA, transient detection is performed by applying an accumulative summation algorithm, and transient occurrence and single-phase types thereof are effectively verified. Furthermore, the D2000CPU performs harmonic feature extraction by using an ADALINE algorithm, and realizes high-precision identification of the early fault of the cable in combination with a double-threshold judgment strategy. According to the invention, the data processing speed is fast, the anti-noise capability is strong, the real-time performance of the system is enhanced, and the significant advantage of the corresponding detection strategy is easy hardware realization, and has the advantages of high precision, fast speed and the like. And meanwhile, original current data are uploaded to the upper computer, and high flexibility and visualization capability are achieved.

Description

Technical Field

[0001] The present invention belongs to a multi-processor cable fault detection technology, and specifically relates to an intelligent cable early fault detection system, which combines a hybrid architecture of FPGA and domestic D2000 CPU to achieve efficient data processing and early fault identification. Background Art

[0002] In cable distribution systems, events are usually divided into two categories: normal events and abnormal events. Normal events do not require intervention, while abnormal events need to trigger a series of protection decisions and actions to ensure the reliability of system operation. Transient and abnormal events can be classified according to their severity, among which transient events caused by intermittent load changes are classified as low-level transients.

[0003] Early faults are usually detected as a fault phenomenon with a small fault current and a short duration, usually between 1 / 4 cycle and 4 cycles. This type of fault is difficult to be effectively detected by traditional protection schemes due to its short duration and relatively small current amplitude. However, the timely detection of early faults is crucial because it is not only a harbinger of cable insulation defects, but also reflects the aging of insulation materials due to thermal, electrical, mechanical and environmental factors. Among them, electrical stress is the main factor causing cable defects, while partial discharge is a typical defect mechanism, especially in organic insulators such as cross-linked polyethylene (XLPE) cables.

[0004] For the detection of early cable faults, existing methods cover a variety of technologies, such as machine learning algorithms based on KNN, SVM, and multi-scale detection technologies such as wavelet transform and Kalman filtering. These methods have certain effects in detecting early faults, but they still have limitations. Summary of the invention

[0005] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide an intelligent cable early fault detection system, which uses FPGA to collect cable current signals and perform transient detection based on cumulative summation. When the occurrence of the transient and its single-phase type are verified, the detection of the transient occurrence is completed; the CPU of D2000 is used to perform harmonic feature extraction and dual threshold judgment based on ADALINE to complete the task of identifying early faults.

[0006] To achieve the above object, the present invention provides a technical solution.

[0007] An intelligent cable early fault detection system is characterized by comprising:

[0008] The FPGA unit is used to perform transient detection on the current signal based on cumulative summation after collecting the cable current from the front-end current signal sensor. When the occurrence of the transient and its single-phase type are verified, the transient occurrence detection is completed, and the data is framed and cached before being sent to the domestic CPU-D2000. When framing the data, the framing format consists of a header bit, a data bit, and a checksum bit. The header includes a single phase, a sampling rate bit, a data length bit, a transient instruction bit, etc.

[0009] The CPU-D2000 unit is used to perform ADALINE-based harmonic feature extraction and dual-threshold judgment on the detected transient signal to complete the task of early fault identification.

[0010] Preferably, the FPGA unit comprises:

[0011] I 2 The C interface module converts multi-phase parallel current data into serial interface data for collection by selecting specific address bits, and collects data according to the multi-master control protocol.

[0012] The clock module is used to generate a controlled sampling clock to control the sampling clock of the front-end current signal sensor.

[0013] The transient detection module deserializes the received serial multi-phase data, parses out the single-phase current signal, performs transient detection on the current signal based on the cumulative summation method, and verifies whether it is a single-phase transient signal.

[0014] The data framing module frames the detected single-phase transient signal data into data packets.

[0015] The data cache module caches the framed data packets and sends them to the CPU-D2000 through the PCI-E interface module.

[0016] PCI-E interface module, used for data transmission between FPGA and CPU-D2000.

[0017] Preferably, the FPGA unit further includes:

[0018] The control instruction module is used to parse the instruction frame from CPU-D2000, which is the working status instruction of FPGA, the initial and final parameters and acquisition parameters of the front-end current signal sensor and FPGA, etc.

[0019] Preferably, in the framed data packet, the bit width length of the header bit is 64 bits, the bit width length of the data bit is 8*1024 bits, and the bit width length of the checksum bit is 32 bits.

[0020] Preferably, the CPU-D2000 unit comprises:

[0021] Framed data packet receiving, checking and de-framing module: used to receive framed data packets, check and de-packetize the data packets and transmit the data to the harmonic feature extraction module.

[0022] The harmonic feature extraction module is used to extract the harmonic features of the detected transient current data based on ADALINE, and transmit the extraction results to the dual threshold judgment module.

[0023] The dual threshold judgment module is used to judge the harmonic feature extraction results.

[0024] The control command and configuration command sending module is used to send the control commands for FPGA operation and the configuration commands for the front-end current signal sensor and FPGA.

[0025] The upload module is used to upload the current data before and after extraction and judgment, feature extraction and identification results.

[0026] In the control and configuration command data format, the header bit width is 48 bits, and the command data bit width is 64 bits.

[0027] Preferably, in the transient detection module, the specific working content of the cumulative summation method is as follows.

[0028] Define S(k) to be k th The current data sample at the moment is used to calculate the first detection parameter according to the following formula:

[0029] q1(k)=MAX(q1(k-1)+S1(k)-p)

[0030] Where p is the maximum regulated current of the relay. If q1(k) is greater than the threshold b for six consecutive samples, a transient current signal is detected.

[0031] The threshold is set to 50, and each corresponding first detection parameter is compared with the threshold to distinguish the fault phase. When the distinction result is single-phase, the data sample is transmitted to the data framing module.

[0032] Preferably, the harmonic feature extraction module specifically includes.

[0033] The harmonic feature extraction module includes three parts: defining a transient current signal model, constructing a harmonic feature extraction model based on ADALINE, training the harmonic feature extraction model based on ADALINE, and extracting harmonic features based on the harmonic feature extraction model based on ADALINE.

[0034] 1) Define the transient current signal model as:

[0035]

[0036] Among them, A dc (1-βkT s ) represents the first two terms of the Taylor expansion of the DC component in the transient signal, T s =2π / ωN s , N s is the sampling period, t(k) is the kth sampling point time, A m and B m Both represent the amplitude and phase information of harmonic components.

[0037] 2) Construct a harmonic feature extraction model based on ADALINE:

[0038]

[0039] Among them, θ(k) is the ADALINE weight vector, X(k) is the input vector of the harmonic feature extraction model of ADALINE, and N is the harmonic coefficient.

[0040] 3) The training process of the harmonic feature extraction model based on ADALINE is as follows:

[0041] Define the output error function as.

[0042]

[0043] in, and f(k) are the expected output and actual output of the ADALINE-based harmonic feature extraction model at the kth moment, respectively.

[0044] Define the weight update vector as.

[0045]

[0046] Among them, α is the learning rate.

[0047] 4) Harmonic feature extraction based on ADALINE’s harmonic feature extraction model.

[0048] The harmonic index HI of the kth transient current data sample is calculated according to the following formula.

[0049]

[0050] Among them, θ1 and θ2 are the weight factors of the harmonic feature extraction model based on ADALINE for the kth data sample.

[0051] Preferably, the dual threshold judgment module specifically includes.

[0052] If HI(k) is greater than a threshold value 600 and has a maximum duration of 0.25 power cycles, the transient signal is identified as a sub-cycle early fault.

[0053] If HI(k) is greater than a threshold value 600 and lasts for more than 0.25 power cycles and less than 4 cycles, the transient signal is identified as a multi-cycle early fault.

[0054] If HI(k) is greater than the threshold value 600 and lasts for more than 4 cycles, the transient signal is not an early fault.

[0055] Preferably, the cable early fault detection system based on FPGA and D2000 also includes a host computer.

[0056] Receive the transient current signal and analysis results uploaded by CPU-D2000 and display them in real time, and provide users with configuration command and control command editing interface, receive configuration commands and control commands input by users, and send them to CPU-D2000. The configuration commands include sampling rate setting, threshold setting, etc., and the control commands include start, stop, sampling clock, etc.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] The system uses PCI-E and Gigabit Ethernet technology for data transmission, which is stable, reliable and real-time. The hybrid architecture of FPGA and CPU is adopted, which has fast data processing speed and strong anti-noise ability, and enhances the real-time performance of the system. A significant advantage of the corresponding detection strategy is that it is easy to implement in hardware and has the advantages of high accuracy and high speed. At the same time, the original current data is uploaded to the host computer, which has strong flexibility and visualization ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a schematic diagram of a cable early fault detection system according to an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram of the inside of the FPGA unit;

[0061] Figure 3 is the test result of the cumulative summation method;

[0062] Figure 4 This is a schematic diagram of the interior of the CPU-D2000 unit.

[0063] Specific implementation cases

[0064] To make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation methods described herein are only used to explain the present invention and do not limit the scope of protection of the present invention.

[0065] See also Figure 1 , Figure 1 : This is a schematic diagram of the cable early fault detection system of the embodiment of the present invention. As shown in the figure, it includes a front-end current signal sensor, an FPGA unit, a CPU-D2000 unit and a host computer. Among them, the front-end current signal sensor is used to collect current signals in the cable and transmit these current signals to the FPGA unit for processing. As the core processing unit of the system, the FPGA is responsible for collecting cable current signals and transient detection based on cumulative summation. When the FPGA verifies the occurrence of the transient and its single-phase type, the detection of the transient occurrence is completed. Subsequently, the FPGA sends the detected data to the CPU-D2000 unit for further processing. The CPU-D2000 unit is responsible for performing harmonic feature extraction and dual threshold judgment based on ADALINE to complete the task of identifying early faults. Finally, the host computer receives the transient current signal and analysis results uploaded by the CPU-D2000 unit, and displays them in real time, while providing the user with an editing interface for configuration commands and control commands.

[0066] The FPGA unit contains multiple modules to realize its functions, such as Figure 2 As shown, including I 2 C interface module, clock module, transient detection module, data framing module, data cache module, PCI-E interface module and control instruction module. Among them, the I2C interface module is used to convert the multi-phase parallel current data output by the front-end current signal sensor into serial interface data for collection by selecting specific address bits. The collection process follows the multi-master control protocol to ensure the accuracy and reliability of the data. The clock module is responsible for generating a controlled sampling clock to control the sampling clock of the front-end current signal sensor. By accurately controlling the sampling clock, the accuracy and consistency of the collected current data can be ensured. The transient detection module receives the serial multi-phase data transmitted by the I2C interface module, and performs deserialization and analysis to extract the single-phase current signal. Then, the current signal is transiently detected based on the cumulative summation method, and it is verified whether it is a single-phase transient signal. Figure 3 The results of the cumulative summation method are shown. This method is fast and has strong noise immunity. Specifically, the transient detection module converts k th The current data sample at the moment is defined as S(k), and the first detection parameter is calculated according to the following formula:

[0067] q1(k)=MAX(q1(k-1)+S1(k)-p)

[0068] Where p is the maximum regulating current of the relay. When the first detection parameter of six consecutive samples is greater than the set threshold b (e.g., 50), the transient current signal is detected. Subsequently, the module will distinguish the fault phase and transmit the data sample to the data framing module when the distinction result is single-phase.

[0069] Data framing module: This module frames the detected single-phase transient signal data into data packets. The framing format of the data packet includes header bits, data bits and checksum bits. Among them, the header bit width length is 64 bits, which is used to contain information such as single phase, sampling rate bit, data length bit, transient instruction bit, etc.; the data bit width length is 8*1024 bits, which is used to store actual current data; the checksum bit width length is 32 bits, which is used to verify the data.

[0070] Data caching module: This module caches the framed data packets and sends them to the CPU-D2000 unit through the PCI-E interface module for further processing.

[0071] PCI-E interface module: used for data transmission between FPGA and CPU-D2000. Through the PCI-E interface, FPGA can quickly and stably transmit the detected data to CPU-D2000.

[0072] Control instruction module: used to parse the instruction frame from CPU-D2000, and adjust the working state of FPGA, the clock parameters of the front-end current signal sensor and FPGA, and the acquisition parameters according to the content of the instruction frame.

[0073] The CPU-D2000 unit contains the frame data packet receiving-checking and de-framing module, harmonic feature extraction module, dual threshold judgment module, control command and configuration command sending module, and upload module. Figure 4 As shown in the figure, the function is realized. Among them, the frame data packet receiving-checking and de-framing module is responsible for receiving the frame data packet transmitted by the FPGA unit through the PCI-E interface module, and checking and de-packetizing the data packet. The checking process is used to ensure the integrity and accuracy of the data, and the de-packetizing process is used to extract the actual current data.

[0074] The harmonic feature extraction module receives the unpacked current data and performs harmonic feature extraction based on ADALINE. ADALINE is a two-layer neural network with a simple structure and easy hardware implementation. The harmonic feature extraction module includes the steps of defining the transient current signal model, building a harmonic feature extraction model based on ADALINE, training the model, and extracting harmonic features.

[0075] Specifically, the transient current signal model is first defined as

[0076]

[0077] Among them, A dc (1-βkT s ) represents the first two terms of the Taylor expansion of the DC component in the transient signal, T s =2π / ωN s , N s is the sampling period, t(k) is the kth sampling point time, A m and B m Both represent the amplitude and phase information of harmonic components.

[0078] Then, a harmonic feature extraction model based on ADALINE is constructed:

[0079]

[0080] Among them, θ(k) is the ADALINE weight vector, X(k) is the input vector of the harmonic feature extraction model of ADALINE, and N is the harmonic coefficient.

[0081] Next, the model's weight vector is adjusted through the training process:

[0082] Define the output error function as.

[0083]

[0084] in, and f(k) are the expected output and actual output of the ADALINE-based harmonic feature extraction model at the kth moment, respectively.

[0085] The weight update vector is defined as:

[0086]

[0087] Among them, α is the learning rate.

[0088] Finally, the trained model is used to extract the harmonic features of the current data and calculate the harmonic index HI:

[0089]

[0090] Among them, θ1 and θ2 are the weight factors of the harmonic feature extraction model based on ADALINE for the kth data sample.

[0091] The dual threshold judgment module receives the harmonic index HI output by the harmonic feature extraction module and makes a judgment based on the set dual thresholds:

[0092] If HI(k) is greater than a threshold value 600 and has a maximum duration of 0.25 power cycles, the transient signal is identified as a sub-cycle early fault.

[0093] If HI(k) is greater than a threshold value 600 and lasts for more than 0.25 power cycles and less than 4 cycles, the transient signal is identified as a multi-cycle early fault.

[0094] If HI(k) is greater than the threshold value 600 and lasts for more than 4 cycles, the transient signal is not an early fault.

[0095] Finally, the current data before and after extraction and judgment, feature extraction and identification results are uploaded to the host computer for display and storage through the upload module. At the same time, the module also receives the configuration commands and control commands issued by the host computer and forwards them to the corresponding modules for processing.

[0096] The workflow of this embodiment is as follows:

[0097] The FPGA unit first controls the clock module, front-end sensor and other parameters according to the control instruction module, and then receives the multi-phase parallel current signal of the front-end current signal sensor through I 2 The C interface module selects specific address bits to convert multi-phase parallel current data into serial interface data for collection, collects data according to the multi-master control protocol, then deserializes the received serial multi-phase data, parses out the single-phase current signal, performs transient detection on the current signal based on the cumulative summation method and verifies whether it is a single-phase transient signal, then frames the detected single-phase transient signal data into a data packet, in which the header bit width length in the framing format is 64 bits, the data bit width length is 8*1024 bits, and the checksum bit width length is 32 bits, then caches the framed data packet and sends it to the CPU-D2000 unit through the PCI-E interface module.

[0098] The CPU-D2000 unit first issues the control command for FPGA operation and the configuration command for the front-end current signal sensor and FPGA through the control command and configuration command issuing module. After receiving the receiving instruction, the framed data packet is received through the framed data packet receiving-checking and de-framing module, and the data packet is checked and unpacked and the data is transmitted to the harmonic feature extraction module. After that, the detected transient current data is subjected to harmonic feature extraction based on ADALINE, and the extraction result is transmitted to the dual threshold judgment module. ADALINE is a two-layer neural network with n inputs and one output, and the output is equal to the linear combination of the inputs. ADALINE was first proposed by Windrow-Hoff of Stanford University. Its main features are: 1) online training based on input changes and target responses; 2) self-matching algorithm suitable for weight training; 3) simple structure, easy to implement in hardware.

[0099] The host computer receives the transient current signal and analysis results uploaded by CPU-D2000 and displays them in real time. At the same time, the host computer also provides users with an editing interface for configuration commands and control commands, allowing users to enter configuration commands such as sampling rate setting and threshold setting, as well as control commands such as start, stop, and sampling clock. These commands are sent to CPU-D2000 for processing through the host computer.

[0100] The cable early fault detection system provided by the present invention has the characteristics of stable and reliable data transmission, fast processing speed, strong anti-noise ability, and strong flexibility and visualization ability, and can realize effective detection and identification of early cable faults.

Claims

1. An intelligent cable early fault detection system, characterized in that: include: The FPGA unit is used to collect the cable current from the front-end current signal sensor, perform transient detection based on cumulative summation on the collected current signal, complete the detection of transient occurrence when verifying the occurrence of transient and its single-phase type, and send the detected single-phase transient signal data to the CPU-D2000 unit after data framing and caching; The CPU-D2000 unit is used to perform ADALINE-based harmonic feature extraction and dual threshold judgment on the detected transient signal.

2. The intelligent cable early fault detection system according to claim 1 is characterized in that: The FPGA unit comprises: I 2 C interface module, used to convert multi-phase parallel current data into serial interface data for collection by selecting specific address bits; The clock module is used to generate a controlled sampling clock to control the sampling clock of the front-end current signal sensor. The transient detection module is used to deserialize the received serial multi-phase data, parse out the single-phase current signal, perform transient detection on the current signal based on the cumulative summation method, and verify whether it is a single-phase transient signal; A data framing module, used for framing the detected single-phase transient signal data into data packets; A data cache module is used to cache the framed data packets and send them to the CPU-D2000 unit through the PCI-E interface module; PCI-E interface module, used for data transmission between FPGA unit and CPU-D2000 unit.

3. The intelligent cable early fault detection system according to claim 2 is characterized in that: The FPGA unit further comprises: The control instruction module is used to parse the instruction frame from the CPU-D2000 unit, wherein the instruction frame is the working status instruction of the FPGA, the initial and final parameters and the acquisition parameters of the front-end current signal sensor and the FPGA.

4. The intelligent cable early fault detection system according to claim 2 is characterized in that: When framing data, the framing format is a header bit, a data bit and a checksum bit, and the header includes a single phase, a sampling rate bit, a data length bit and a transient instruction bit.

5. The intelligent cable early fault detection system according to claim 4 is characterized in that: In the framed data packet, the header bit width length is 64 bits, the data bit width length is 8*1024 bits, and the checksum bit width length is 32 bits.

6. The intelligent cable early fault detection system according to claim 1 is characterized in that: The CPU-D2000 unit comprises: The framed data packet receiving, checking and de-framing module is used to receive the framed data packets, check and de-packetize the data packets, and transmit the data to the harmonic feature extraction module; A harmonic feature extraction module is used to extract harmonic features of the detected transient current data based on ADALINE, and transmit the extraction results to the dual threshold judgment module; A dual threshold judgment module is used to judge the results of harmonic feature extraction; A control command and configuration command issuing module, used to issue control commands for FPGA operation and configuration commands for the front-end current signal sensor and FPGA; The upload module is used to upload the current data before and after extraction and judgment, feature extraction and identification results.

7. The intelligent cable early fault detection system according to claim 6, characterized in that: In the control and configuration command data format, the header bit width length is 48 bits, and the command data bit width length is 64 bits.

8. The intelligent cable early fault detection system according to claim 6, characterized in that: The cumulative summation method of the transient detection module includes: Calculate the first detection parameter, the formula is as follows: q1(k)=MAX(q1(k-1)+S1(k)-p) Where S(k) is the current data sample at the kth moment, and p is the maximum regulating current of the relay; If q1(k) is greater than threshold b for six consecutive samples, a transient current signal is detected; The threshold is set to 50, and each corresponding first detection parameter is compared with the threshold to distinguish the fault phase. When the distinction result is single-phase, the data sample is transmitted to the data framing module.

9. The intelligent cable early fault detection system according to claim 2, characterized in that: The harmonic feature extraction module comprises: ①Define the transient current signal model: Among them, A dc (1-βkT s ) represents the first two terms of the Taylor expansion of the DC component in the transient signal, T s =2π / ωN s , N s is the sampling period, t(k) is the kth sampling point time, A m and B m Both represent the amplitude and phase information of harmonic components; ②Build a harmonic feature extraction model based on ADALINE: Among them, θ(k) is the ADALINE weight vector, X(k) is the ADALINE harmonic feature extraction model input vector, and N is the harmonic coefficient; ③The training process of the harmonic feature extraction model based on ADALINE is as follows: Define the output error function: in, and f(k) are the expected output and actual output of the ADALINE-based harmonic feature extraction model at the kth moment, respectively. Define the weight update vector: Among them, α is the learning rate; ④ Harmonic feature extraction based on ADALINE’s harmonic feature extraction model: The harmonic index HI of the kth transient current data sample is calculated according to the following formula: Among them, θ1 and θ2 are the weight factors of the harmonic feature extraction model based on ADALINE for the kth data sample.

10. The intelligent cable early fault detection system according to claim 2, characterized in that: The dual threshold judgment module receives the harmonic index HI output by the harmonic feature extraction module and makes a judgment according to the set dual thresholds, specifically including: If HI(k) is greater than the threshold value 600 and the maximum duration is 0.25 power cycles, the transient signal is identified as a sub-cycle early fault; If HI(k) is greater than a threshold of 600 and lasts for more than 0.25 power cycles and less than 4 cycles, the transient signal is identified as a multi-cycle early fault; If HI(k) is greater than the threshold value 600 and lasts for more than 4 cycles, the transient signal is not an early fault.

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