Radar data comprehensive processing method, device and equipment and storage medium

Abstract

The invention discloses a method for comprehensively processing radar data. The method comprises the following steps: acquiring a radar video signal, a trigger signal, a true north signal and an azimuth signal in real time through a special interface; the radar video signal is sent to an ADC module for AD sampling conversion; carrying out signal preprocessing on the data sampled by the AD through an FPGA (Field Programmable Gate Array) processor; carrying out comprehensive data processing on the preprocessed data through a CPU module of a built-in PC board; and packaging the data information after the comprehensive data processing, and outputting the data information in real time through the Ethernet. By adopting the technical scheme, radar data processing is carried out by using integrated equipment which works continuously and stably for a long time, and the method has the characteristics of convenience in deployment, high integration level, stability in operation, good processing effect and the like, so that the requirements of erecting equipment with high reliability and high integration degree in an unattended or severe environment are met, and the radar is convenient to install and use.

Description

Technical Field

[0001] The present invention relates to the technical field of radar data acquisition and processing, and in particular to a method, device, equipment and storage medium for comprehensive processing of radar data. Background Art

[0002] At present, the data processing of mainstream surveillance radar products installed in China, including shore-based surveillance, ship navigation and other non-coherent radars, is implemented in the form of "board + server (workstation)", with many and scattered devices, inconvenient deployment, waste of resources, and low integration. In recent years, with the rapid improvement of computer CPU and GPU performance and the rapid development of chip localization, it is technically feasible to use full software to complete radar signal processing, data processing, display and control, storage and other functions on one device. However, how to integrate data acquisition and processing in one device without affecting the processing speed has become a key research issue.

[0003] The current common data processing method is: the analog / digital video signal, azimuth information and trigger information output by the signal processing are connected to the board, the board performs data sampling, recording and storage, and is connected to the server through the PCI bus. The point track data is read to the server for data interconnection, filtering prediction, track smoothing and other processing, and finally a stable track is output to the display for display. This method involves many devices and takes up a large area for installation, including boards and servers. The data generation and transmission process are affected by many factors, the stability is insufficient, and the integration is not high.

[0004] In summary, the current problem is that the equipment for radar data collection and processing is scattered, and the radar data cannot be output in a centralized and simplified manner. We need a device that can achieve long-term, continuous and stable operation in harsh environments, and it is required to have the characteristics of easy deployment, high integration, stable operation, and good processing effect. Summary of the invention

[0005] The purpose of the present invention is to provide a method for comprehensive processing of radar data, and the technical problem to be solved is: considering the high maintenance cost and harsh installation conditions in unmanned or harsh environments, it is necessary to develop highly reliable and highly integrated equipment to facilitate radar installation and use, and to process and transmit radar data at low cost, high efficiency and high reliability.

[0006] The purpose of the present invention can be achieved through the following technical solutions:

[0007] A method for comprehensive processing of radar data comprises the following steps:

[0008] Step S1, obtaining radar video signals, trigger signals, true north signals, and azimuth signals in real time through a proprietary interface;

[0009] Step S2, sending the radar video signal to the ADC module for 14bit / 120MSPS high-speed, high-precision AD sampling conversion;

[0010] Step S3, the AD sampled data is subjected to signal preprocessing such as same-frequency interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold through an FPGA processor;

[0011] Step S4, performing comprehensive data processing on the pre-processed data through the CPU module of the built-in PC board, wherein the comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking;

[0012] Step S5: Pack the data information after comprehensive data processing and output it in real time via Ethernet.

[0013] As a further solution of the present invention: the AD sampling conversion in step S2 includes the following sub-steps:

[0014] S21, transmitting the radar video signal outputted from step S1 through a 75Ω matching circuit and a level shifting circuit, and sending the signal to an ADC module for high-speed and high-precision AD sampling conversion;

[0015] S22, when the ADC module performs sampling conversion processing, a selectable sampling rate of 1, 2, 4, 8, or 16 is used to extract the signal.

[0016] As a further solution of the present invention: the signal preprocessing in step S3 includes the following sub-steps:

[0017] S31, converting the AD sampled data and performing zero bias adjustment to transform the sampled converted data to 8bit to reduce the network data rate;

[0018] S32, converting the trigger signal, the bow signal and the azimuth signal, and interpolating the azimuth signal to 65536 to improve the azimuth resolution;

[0019] S33, accumulating the echo data at a preset decimation rate, and then storing it at high resolution;

[0020] S34, packaging the echo data together with the information of the azimuth, heading, pulse repetition interval, number of valid data points, starting distance, distance unit, module temperature and power supply voltage, and sending them to the Ethernet, and transmitting them to the integrated processing module on the PC board;

[0021] S35. Design a variety of analog signals to facilitate debugging and testing, wherein the analog signals include analog trigger, bow and azimuth signals.

[0022] As a further solution of the present invention: the comprehensive data processing in step S4 is used to process the echo data pre-processed in step S3 to achieve target detection and extraction, stable tracking of the track, and real-time PPI display and A display and B display, thereby achieving reliable detection and stable tracking of the target.

[0023] A device for comprehensive processing of radar data, comprising an ADC module, an FPGA processor, a CPU module and a communication module;

[0024] The ADC module is used to perform 14bit / 120MSPS high-speed and high-precision AD sampling conversion on the radar video signal acquired in real time;

[0025] The FPGA processor is used to perform signal preprocessing of co-channel interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold on the data used by the ADC module;

[0026] The CPU module is used to perform comprehensive data processing on the data preprocessed by the FPGA processor, and the comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking;

[0027] The communication module is used to output the data information after the comprehensive data processing of the CPU module in real time through Ethernet.

[0028] A terminal device for integrated processing of radar data, comprising an FPGA processor encapsulated in a metal box, a CPU memory, and a computer program stored in the CPU memory and configured to be executed by the FPGA processor, wherein the FPGA processor implements the method for integrated processing of radar data as described in any one of claims 1 to 4 when executing the computer program.

[0029] As a further solution of the present invention: a TVS overvoltage and electrostatic protection circuit is provided on the FPGA processor.

[0030] A computer-readable storage medium for integrated processing of radar data, the computer-readable storage medium comprising a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the method for integrated processing of radar data as claimed in any one of claims 1 to 4.

[0031] Beneficial effects of the present invention:

[0032] (1) The radar video signal acquired in real time through AD sampling conversion is pre-processed by the FPGA processor for co-channel interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold signal pre-processing, and then the CPU module performs comprehensive data processing. The comprehensive data processing includes threshold processing, image segmentation, contour extraction, point filtering, and track tracking. It can realize the integration of radar data acquisition and processing in one device, so as to facilitate the centralized and simplified output of radar data.

[0033] (2) Integrated equipment that can work continuously and stably for a long time is used for radar data processing. It has the characteristics of easy deployment, high integration, stable operation, and good processing effect. It can meet the requirements of setting up reliable and highly integrated equipment in unmanned or harsh environments, and facilitate radar installation and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be further described below in conjunction with the accompanying drawings.

[0035] Figure 1 It is a schematic flow chart of the method for comprehensive processing of radar data of the present invention;

[0036] Figure 2 yes Figure 1 Schematic diagram of AD sampling processing in step S2;

[0037] Figure 3 yes Figure 1 Schematic diagram of signal preprocessing in step S3;

[0038] Figure 4 yes Figure 1 Schematic diagram before comprehensive data processing in step S4;

[0039] Figure 5 yes Figure 1 Schematic diagram after comprehensive data processing in step S4;

[0040] Figure 6 The present invention is a schematic diagram of the circuit design of the radar data comprehensive processing device. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Example 1

[0043] See also Figures 1 to 5As shown, the present invention is a method for comprehensive processing of radar data, comprising the following steps:

[0044] Step S1, obtaining radar video signals, trigger signals, true north signals, and azimuth signals in real time through a proprietary interface.

[0045] Step S2, sending the radar video signal to the ADC module for 14bit / 120MSPS high-speed, high-precision AD sampling conversion; during the AD sampling conversion in this step, the radar video signal output in step S1 is transmitted through a 75Ω matching circuit and a level shift circuit, and sent to the ADC module for high-speed, high-precision AD sampling conversion; during the sampling conversion processing of the ADC module in this step, the signal is extracted using a sampling rate of 1, 2, 4, 8, or 16. The AD sampling processing result of this step is as follows: Figure 2 shown.

[0046] Step S3, the AD sampled data is subjected to signal preprocessing of same-frequency interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold through the FPGA processor; during the signal preprocessing in this step, the following functions are mainly completed in sequence: the AD sampled data is converted and zero bias adjustment is performed to transform the sampled and converted data to 8bit to reduce the network data rate; the trigger signal, the bow signal and the azimuth signal are converted, and the azimuth signal is interpolated to 65536 to improve the azimuth resolution; the echo data is accumulated at a preset decimation rate, and then stored with high resolution, and a maximum of 4096 data points are designed for storage; the echo data is packaged together with the information of azimuth, heading, pulse repetition interval, number of valid data points, starting distance, distance unit, module temperature and power supply voltage and sent to Ethernet, and transmitted to the integrated processing module on the PC board; a variety of analog signals are designed to facilitate debugging and testing, and the analog signals include analog trigger, bow and azimuth signals.

[0047] In this step, the FPGA processor can use a domestic high-performance FPGA, the model is the domestically produced Fudan Micro's XC7VX690T1927I 2 (not limited to this model, other qualified devices can also be used), which can complete azimuth interpolation, internal signal simulation and self-test functions, data packaging, Ethernet protocol, etc., and perform signal preprocessing, including interference suppression, adaptive CFAR constant false alarm processing based on clutter distribution model identification, correlation accumulation, target monitoring, tracking filtering, etc., combining statistical and machine learning signal processing methods to adaptively suppress clutter.

[0048] The signal preprocessing operation in this step is controlled as follows Figure 3 shown.

[0049] Step S4, the pre-processed data is subjected to comprehensive data processing by the CPU module of the built-in PC board, and the comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking; the comprehensive data processing in this step is used to process the echo data pre-processed in step S3 to achieve target detection and extraction, stable track tracking, and real-time PPI display and A display, B display, so as to achieve reliable detection and stable tracking of the target; the radar detection target obtained before the comprehensive data processing in this step is as follows Figure 4 As shown in Figure 1, the radar detection target before the comprehensive data processing is unclear, while the radar detection target obtained after the comprehensive data processing is as follows: Figure 5 As shown, the radar detected target is clear and complete after comprehensive data processing.

[0050] Step S5: Pack the data information after comprehensive data processing and output it in real time via Ethernet.

[0051] The present embodiment provides a method for comprehensive processing of radar data. The radar video signal acquired in real time through AD sampling conversion is subjected to co-channel interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold signal preprocessing through an FPGA processor, and then comprehensive data processing is performed through a CPU module. The comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking. The radar data acquisition and processing can be integrated in one device to facilitate centralized and simplified output of radar data. The method is used to process radar data using an integrated device that works continuously and stably for a long time, and has the characteristics of convenient deployment, high integration, stable operation, good processing effect, etc., thereby meeting the requirements for reliable and highly integrated equipment in unattended or harsh environments, and facilitating radar installation and use.

[0052] Example 2

[0053] like Figure 6 As shown, the present invention provides a device for comprehensive processing of radar data, including an ADC module, an FPGA processor, a CPU module and a communication module, wherein the ADC module is used to perform 14bit / 120MSPS high-speed and high-precision AD sampling conversion on the radar video signal acquired in real time, the FPGA processor is used to perform co-frequency interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold signal preprocessing on the data used by the ADC module, the CPU module is used to perform comprehensive data processing on the data preprocessed by the FPGA processor, the comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking, and the communication module is used to output the data information after the comprehensive data processing of the CPU module in real time through Ethernet.

[0054] The present embodiment provides a device for comprehensive processing of radar data. By using an ADC module, an FPGA processor, a CPU module and a communication module to process real-time acquired radar signals in sequence, radar data acquisition and processing are integrated in one device, so as to output radar data in a centralized and simplified manner. The present method uses an integrated device that works stably for a long time and continuously to process radar data. The method has the characteristics of convenient deployment, high integration, stable operation, good processing effect, etc., thereby meeting the requirements for reliable and highly integrated equipment in unattended or harsh environments, and facilitating radar installation and use.

[0055] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0056] It should be noted that the embodiment of the above-mentioned radar data integrated processing device is only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0057] Example 3

[0058] Based on the embodiment of the above-mentioned radar data comprehensive processing method, the present invention provides a terminal device for radar data comprehensive processing, including an FPGA processor encapsulated in a metal box, a CPU memory, and a computer program stored in the CPU memory and configured to be executed by the FPGA processor. When the FPGA processor executes the computer program, the radar data comprehensive processing method of any embodiment of the present invention is implemented.

[0059] Exemplarily, in this embodiment, the computer program can be divided into one or more modules, which are stored in the CPU memory and executed by the FPGA processor to complete the present invention. The one or more modules can be a series of computer program instruction segments that can complete specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device for integrated processing of radar data.

[0060] The terminal device in this embodiment can adopt advanced thermal design methods to encapsulate all circuits in a sealed metal box, which greatly improves the anti-interference ability and reliability, and can meet the requirements of long-term, continuous and stable operation in harsh environments; it also has the advantages of convenient deployment, high integration, stable operation, and good processing effect. The core is an integrated domestic processor, and the signal interfaces such as the transmission trigger, bow, and azimuth increment connected to the radar all adopt the RS422 / TTL standard; in addition, the FPGA processor is equipped with a TVS overvoltage and electrostatic protection circuit to prevent static electricity from causing damage to the device.

[0061] Example 4

[0062] The present invention provides a computer-readable storage medium for integrated processing of radar data, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute a method for integrated processing of radar data as in any embodiment of the present invention.

[0063] In this embodiment, the storage medium is a computer-readable storage medium, and the computer program includes computer program code, which may be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-On l yMemory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0064] In summary, the present invention discloses a method, device, equipment and storage medium for comprehensive processing of radar data. The radar video signal acquired in real time through AD sampling conversion is subjected to co-frequency interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold signal preprocessing through an FPGA processor, and then comprehensive data processing is performed through a CPU module. The comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking, and can realize the integration of radar data acquisition and processing in one device, so as to output radar data in a centralized and simplified manner. The method is to use an integrated device that works stably for a long time and continuously, and has the characteristics of convenient deployment, high integration, stable operation, good processing effect, etc., so as to meet the requirements of reliable and highly integrated equipment in unattended or harsh environments, and facilitate radar installation and use.

[0065] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for comprehensive processing of radar data, characterized in that: The following steps are involved: Step S1, obtaining radar video signals, trigger signals, true north signals, and azimuth signals in real time through a proprietary interface; Step S2, sending the radar video signal to the ADC module for 14bit / 120MSPS high-speed, high-precision AD sampling conversion; Step S3, the AD sampled data is subjected to signal preprocessing such as same-frequency interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold through an FPGA processor; Step S4, performing comprehensive data processing on the pre-processed data through the CPU module of the built-in PC board, wherein the comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking; Step S5: Pack the data information after comprehensive data processing and output it in real time via Ethernet.

2. The method for comprehensive processing of radar data according to claim 1, characterized in that: The AD sampling conversion in step S2 includes the following sub-steps: S21, transmitting the radar video signal outputted from step S1 through a 75Ω matching circuit and a level shifting circuit, and sending the signal to an ADC module for high-speed and high-precision AD sampling conversion; S22, when the ADC module performs sampling conversion processing, a selectable sampling rate of 1, 2, 4, 8, or 16 is used to extract the signal.

3. The method for comprehensive processing of radar data according to claim 2, characterized in that: The signal preprocessing in step S3 includes the following sub-steps: S31, converting the AD sampled data and performing zero bias adjustment to convert the sampled converted data to 8 bits to reduce the network data rate; S32, converting the trigger signal, the bow signal and the azimuth signal, and interpolating the azimuth signal to 65536 to improve the azimuth resolution; S33, accumulating the echo data at a preset decimation rate, and then storing it at high resolution; S34, packaging the echo data together with the information of the azimuth, heading, pulse repetition interval, number of valid data points, starting distance, distance unit, module temperature and power supply voltage, and sending them to the Ethernet, and transmitting them to the integrated processing module on the PC board; S35. Design a variety of analog signals to facilitate debugging and testing, wherein the analog signals include analog trigger, bow and azimuth signals.

4. The method for comprehensive processing of radar data according to claim 3, characterized in that: The comprehensive data processing in step S4 is used to process the echo data preprocessed in step S3 to achieve target detection and extraction, stable tracking of the track, and real-time PPI display and A display and B display, thereby achieving reliable detection and stable tracking of the target.

5. A device for comprehensive processing of radar data, characterized in that: Including ADC module, FPGA processor, CPU module and communication module; The ADC module is used to perform 14bit / 120MSPS high-speed and high-precision AD sampling conversion on the radar video signal acquired in real time; The FPGA processor is used to perform signal preprocessing of co-channel interference suppression, azimuth accumulation, distance accumulation, constant false alarm, clutter suppression and slow threshold on the data used by the ADC module; The CPU module is used to perform comprehensive data processing on the data preprocessed by the FPGA processor, and the comprehensive data processing includes threshold processing, image segmentation, contour extraction, point trace filtering, and track tracking; The communication module is used to output the data information after the comprehensive data processing of the CPU module in real time through Ethernet.

6. A terminal device for comprehensive processing of radar data, characterized in that: The invention comprises an FPGA processor encapsulated in a metal box, a CPU memory, and a computer program stored in the CPU memory and configured to be executed by the FPGA processor. When the FPGA processor executes the computer program, the method for integrated processing of radar data as described in any one of claims 1 to 4 is implemented.

7. The terminal device for integrated processing of radar data according to claim 6, characterized in that: The FPGA processor is provided with a TVS overvoltage and electrostatic protection circuit.

8. A computer-readable storage medium for integrated processing of radar data, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the radar data integrated processing method according to any one of claims 1 to 4.

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