Memory testing method, memory testing device, storage medium and electronic equipment

Abstract

The invention discloses a memory testing method, a memory testing device, a storage medium and electronic equipment, and the memory testing method comprises the steps: traversing each storage unit of a to-be-tested memory, performing data read-write operation on the traversed target storage unit and an adjacent storage unit adjacent to the target storage unit according to a preset advancing rule; performing logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value; if the actual logic relation value is not consistent with the standard logic relation value, it is determined that the to-be-tested memory has a fault, by adopting the method, the fault condition of the memory can be detected through the actual logic relation value, the reliability of a test algorithm is high, meanwhile, the fault coverage rate and the test complexity are both considered, and the fault test efficiency is high.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory testing method, a memory testing device, a storage medium and an electronic device. Background Art

[0002] In the related art, a built-in self-test is performed on the fault of the memory through a test algorithm, that is, the logic value is compared and analyzed with the expected value to detect the fault of the memory, but the reliability of the test algorithm is poor. At present, the test algorithm is mainly divided into a linear test algorithm and a nonlinear test algorithm. The linear algorithm includes the Check board algorithm, the March algorithm and its derivative algorithms such as the MATS algorithm. The nonlinear algorithm such as the Gallop algorithm basically covers the test of fixed-type faults, jump-type faults and coupled-type faults. However, the test time of the Check board algorithm is short and the fault coverage rate is low. The March algorithm and its derivative algorithms are different for different fault types, coverage rates and test times. Nonlinear algorithms such as the Gallop algorithm can basically cover the test of fixed-type faults, jump-type faults and coupled-type faults. The Gallop algorithm requires I / 0 (input / output) to roam the entire storage cell array during the test process, which leads to low fault test efficiency. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a memory testing method, by which the fault condition of the memory can be detected through the actual logic relationship value, the reliability of the test algorithm is high, the fault coverage and the test complexity are taken into account, and the fault test efficiency is high.

[0004] A second objective of the present invention is to provide a memory testing device.

[0005] A third object of the present invention is to provide a computer storage medium.

[0006] A fourth objective of the present invention is to provide an electronic device.

[0007] In order to solve the above problems, an embodiment of the first aspect of the present invention provides a memory testing method, comprising: traversing each storage unit of the memory to be tested, and during the traversal process, performing data reading and writing operations on the traversed target storage unit and the adjacent storage units adjacent to the target storage unit according to a preset progress rule; performing logical operations on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value; if the actual logical relationship value is inconsistent with the standard logical relationship value, it is determined that the memory to be tested has a fault.

[0008] According to the memory testing method of the embodiment of the present invention, when traversing each memory cell, different logic values ​​are rewritten to the traversed target memory cell and its adjacent memory cells according to the preset progress rule, so that the memory cells in the memory are more prone to failure, and the actual logic relationship value is calculated by reading the read data of the target memory cell and the read data of the adjacent memory cells, and then the actual logic relationship value is compared with the standard logic relationship value to detect the failure of each memory cell. Therefore, compared with the method of comparing the logic value with the expected value in the existing algorithm to obtain the failure condition of the memory to be tested, the actual logic relationship value is used to detect the failure of each memory cell in the present application, which can further improve the reliability of the test algorithm. In addition, compared with the March algorithm, the algorithm in the present application has a lower test complexity, and reads and writes the target memory cell and its adjacent memory cells according to the preset progress rule. This progress method can better sensitize the coupling failure of the memory cell, thereby achieving a higher fault coverage rate.

[0009] In some embodiments, before traversing each storage unit of the memory, the method further includes: writing test data into each storage unit of the memory to be tested.

[0010] In some embodiments, the test data includes a preset logic value and an opposite value of the preset logic value, and writing the test data to each storage unit of the memory under test includes: alternately writing the preset logic value and the opposite value of the preset logic value to each storage unit of the memory under test.

[0011] In some embodiments, each storage unit of the memory to be tested is traversed, and during the traversal process, data reading and writing operations are performed on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule, including: a first traversal of each storage unit along a first order; in the first traversal, data reading and writing operations are performed on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule until all storage units of the memory to be tested are traversed.

[0012] In some embodiments, after the first traversal of each storage unit along the first order, it includes: traversing each storage unit for a second time along the second order; in the second traversal, data reading and writing operations are performed on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule until all storage units of the memory to be tested are traversed.

[0013] In some embodiments, the first sequence is incremented from the storage unit of the lower address bit to the storage unit of the higher address bit; and the second sequence is consistent with the first sequence.

[0014] In some embodiments, the first order is increasing from the storage unit of the lower address bit to the storage unit of the higher address bit; the second order is decreasing from the storage unit of the higher address bit to the storage unit of the lower address bit.

[0015] In some embodiments, the preset proceeding rule includes: performing a read operation on the target storage unit and on storage units adjacent to the target storage unit.

[0016] In some embodiments, the adjacent storage cell includes a subsequent storage cell of the target storage cell; performing a logical operation on the read data of the target storage cell and the read data of the adjacent storage cell to obtain an actual logical relationship value, including: performing a logical AND operation on the first read data and the second read data to obtain an actual logical relationship value, wherein the first read data is obtained by performing a read operation on the target storage cell before flipping, and the second read data is obtained by performing a read operation on the subsequent storage cell before flipping.

[0017] In some embodiments, the adjacent storage unit includes a subsequent storage unit of the target storage unit; performing a logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value, including: performing a logical OR operation on the first read data and the second read data to obtain an actual logical relationship value, wherein the first read data is obtained by performing a read operation on the target storage unit, and the second read data is obtained by performing a read operation on the subsequent storage unit.

[0018] In some embodiments, the adjacent storage unit includes a previous storage unit of the target storage unit; performing a logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value, including: performing a logical XOR operation on the first read data and the third read data to obtain the actual logical relationship value, wherein the first read data is obtained by performing a read operation on the target storage unit, and the third read data is obtained by performing a read operation on the previous storage unit.

[0019] In some embodiments, the preset proceeding rule further includes: performing a data flip operation on the target storage unit.

[0020] In some embodiments, the adjacent storage unit includes a subsequent storage unit of the target storage unit; performing a logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value, including: performing a logical XOR operation on fourth read data and second read data to obtain an actual logical relationship value, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit, and the second read data is obtained by performing a read operation on the subsequent storage unit.

[0021] In some embodiments, the adjacent storage unit includes a previous storage unit of the target storage unit; performing a logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value, including: performing a logical AND operation on fourth read data and third read data to obtain an actual logical relationship value, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit, and the third read data is obtained by performing a read operation on the previous storage unit.

[0022] In some embodiments, the adjacent storage unit includes a previous storage unit of the target storage unit; performing a logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value, including: performing a logical OR operation on fourth read data and third read data to obtain an actual logical relationship value, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit, and the third read data is obtained by performing a read operation on the previous storage unit.

[0023] In some embodiments, the preset progress rule further includes: performing a read operation on the flipped storage unit in units of preset progress units.

[0024] In some embodiments, two adjacent storage units are used as the preset moving units.

[0025] In some embodiments, the memory testing method further includes: performing a logical AND operation on fifth read data and sixth read data to obtain an actual logical relationship value, wherein the fifth read data is obtained by performing a read operation on a storage unit at a low address bit in the preset advancing unit, and the sixth read data is obtained by performing a read operation on a storage unit at a high address bit in the preset advancing unit.

[0026] In some embodiments, the memory testing method further includes: performing a logical OR operation on fifth read data and sixth read data to obtain an actual logical relationship value, wherein the fifth read data is obtained by performing a read operation on a low address bit storage unit in the preset forward unit, and the sixth read data is obtained by performing a read operation on a high address bit storage unit in the preset forward unit.

[0027] In some embodiments, the method further includes: if the actual logic relationship value is consistent with the standard logic relationship value, determining that the memory to be tested is normal.

[0028] In some embodiments, during the traversal process, the test result of the memory to be tested is determined according to the read data of the target storage unit and the expected data corresponding to the target storage unit.

[0029] In some embodiments, the test result of the memory to be tested is determined based on the read data and expected data of the target storage unit, including: determining that the first read data is consistent with the first expected data corresponding to the target storage unit, then determining that the memory to be tested is normal, wherein the first read data is obtained by performing a read operation on the target storage unit before flipping.

[0030] In some embodiments, the test result of the memory to be tested is determined based on the read data and expected data of the target storage unit, including: determining that the first read data is inconsistent with the first expected data corresponding to the target storage unit, then determining that the memory to be tested has a fault, wherein the first read data is obtained by performing a read operation on the target storage unit before flipping.

[0031] In some embodiments, the test result of the memory to be tested is determined based on the read data of the target storage unit and the expected data corresponding to the target storage unit, including: determining that the fourth read data is consistent with the second expected data corresponding to the target storage unit, then determining that the memory to be tested is normal, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit.

[0032] In some embodiments, the test result of the memory to be tested is determined based on the read data of the target storage unit and the expected data corresponding to the target storage unit, including: determining that the fourth read data is inconsistent with the second expected data corresponding to the target storage unit, then determining that the memory to be tested has a fault, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit.

[0033] The second aspect of the present invention provides a memory testing device, including: a traversal module, which is used to traverse each storage unit of the memory to be tested, and during the traversal process, performs data reading and writing operations on the traversed target storage unit and the adjacent storage units adjacent to the target storage unit according to a preset progress rule; an acquisition module, which determines the logical operation of the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value; and a determination module, which determines that the memory to be tested has a fault when the actual logical relationship value is inconsistent with the standard logical relationship value.

[0034] According to the memory testing device of the embodiment of the present invention, the fault condition of the memory can be detected through the actual logic relationship value, the reliability of the test algorithm is high, and both the fault coverage and the test complexity are taken into account, and the fault test efficiency is high.

[0035] A third aspect of the present invention provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the memory testing method described in the above embodiment.

[0036] A fourth aspect of the present invention provides an electronic device, comprising: at least one processor; a memory communicatively connected to at least one of the processors; wherein the memory stores a computer program executable by at least one of the processors, and when at least one of the processors executes the computer program, the memory testing method described in the above embodiment is implemented.

[0037] According to the electronic device of the embodiment of the present invention, the fault condition of the memory can be detected through the actual logic relationship value, the reliability of the test algorithm is high, the fault coverage and the test complexity are taken into account at the same time, and the fault test efficiency is high.

[0038] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0040] Figure 1 is a schematic diagram of a memory according to an embodiment of the present invention;

[0041] Figure 2 is a flow chart of a memory testing method according to an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of memory area division according to an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of a memory cell logic value according to an embodiment of the present invention;

[0044] Figure 5 is a schematic diagram of a memory cell logic value according to another embodiment of the present invention;

[0045] Figure 6 is a flow chart of a memory testing method according to another embodiment of the present invention;

[0046] Figure 7 is a flow chart of a memory testing method according to another embodiment of the present invention;

[0047] Figure 8 is a structural block diagram of a memory testing device according to an embodiment of the present invention;

[0048] Fig. 9 is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0049] Reference numerals:

[0050] Memory testing device 10; electronic device 20;

[0051] Traversal module 2; first determination module 3; second determination module 4; processor 5; memory 6; storage unit 7. DETAILED DESCRIPTION

[0052] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0053] As various types of memories are integrated into embedded processors, embedded processors such as SRAM or DRAM can be widely used in embedded systems due to their flexible and configurable advantages. However, the rapid development of embedded technology and processes has led to higher and higher requirements for memory capacity and integration. The high-density integration of memories makes the storage units in the memories more prone to failure. Therefore, in order to ensure the normal operation of the MCU chip, the logical failure of the memory needs to be tested.

[0054] In the related art, most memories use built-in self-test to complete fault detection, and built-in self-test does not rely on external test equipment, and the test algorithm is the key to complete built-in self-test fault detection. The logic circuit and test circuit of the built-in self-test are integrated inside the chip. The logic circuit is used to generate deterministic test data inside the chip, and then the test data is applied to the memory to be tested. The logic value is returned to the test circuit and compared with the expected value to detect the memory fault. However, the reliability of the test algorithm is poor. At present, the test algorithm is mainly divided into linear test algorithm and nonlinear test algorithm. The linear algorithm includes the Check board algorithm, the March algorithm and its derivative algorithms such as the MATS algorithm. The nonlinear algorithm such as the Gallop algorithm basically covers the test of fixed-type faults, jump-type faults and coupled-type faults. However, the test time of the Check board algorithm is short and the fault coverage is low. The March algorithm and its derivative algorithms are different for different fault types, coverage and test time. Nonlinear algorithms such as the Gallop algorithm can basically cover the test of fixed-type faults, jump-type faults and coupled-type faults. The Gallop algorithm requires 1 / 0 to roam the entire storage cell array during the test process, which leads to low fault test efficiency.

[0055] In order to solve the above problems, an embodiment of the first aspect of the present invention provides a memory testing method, which can detect the fault condition of the memory through the actual logical relationship value. The test algorithm has high reliability, takes into account the fault coverage and test complexity, and has high fault testing efficiency.

[0056] like Figure 1 The schematic diagram of the memory structure of an embodiment of the present invention is that the memory is based on a memory cell, that is, the memory is composed of a plurality of memory cells, wherein one memory cell can store one byte. The memory cells have different logical address arrangement modes and physical address arrangement modes. In the logical address arrangement, the addresses of the memory cells increase linearly, while in the physical address arrangement, the addresses of the memory cells are nonlinear. All memory cells are arranged in the form of an array of N rows × M columns, wherein the rows correspond to the row addresses and the columns correspond to the column addresses. After the address on the address bus is transmitted to the row address buffer and the column address buffer, the address is sent to the row / column decoder through the row / column address line. The row / column decoder decodes the address to generate the row address and the column address to address the target memory cell, and then performs read and write operations on the target memory cell and transmits the data in the target memory cell to the data bus.

[0057] Reference below Figure 2 A memory testing method according to an embodiment of the present invention is described. Figure 2 As shown, the method includes: step S1 to step S3.

[0058] Step S1, traversing each storage unit of the memory to be tested, during the traversal process, performing data reading and writing operations on the traversed target storage unit and the adjacent storage units adjacent to the target storage unit according to a preset progress rule.

[0059] Specifically, each storage cell of the memory to be tested is traversed, and during the traversal process, the data stored in the traversed target storage cell and its adjacent storage cells are read and the logic value is rewritten according to the preset progress rule, that is, the data in the traversed target storage cell and the adjacent storage cells are changed through the write operation, so that the storage cells in the memory are more prone to failure, thereby providing a memory failure test environment, and performing a read operation after or before the write operation on the test data stored in the traversed target storage cell and the adjacent storage cells. Therefore, in the present application, the target storage cell and its adjacent storage cells are read and written according to the preset progress rule. This progress method can better sensitize the coupled failures of the storage cells, thereby achieving a higher fault coverage rate.

[0060] Among them, there is no limit on the number of times each storage unit of the memory to be tested is traversed, and it can be once, twice or more times. It can be understood that the more times the traversal is performed, the more likely the memory to be tested is to have different faults, and the more fault conditions may occur, thereby achieving a higher fault coverage rate and further improving the reliability of the test algorithm.

[0061] Step S2, performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value.

[0062] Specifically, after or before a write operation is performed on the test data stored in the traversed target storage unit, a read operation is performed on the test data in the target storage unit to obtain its read data, and a read operation is performed on the logic value in the adjacent storage unit after or before a write operation to obtain its read data, and a logical operation is performed on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value.

[0063] Step S3: If the actual logic relationship value is inconsistent with the standard logic relationship value, it is determined that the memory to be tested has a fault.

[0064] Specifically, when a fixed-type fault occurs in a storage cell in the memory, the logic value in the storage cell cannot change; when a jump-type fault occurs in a storage cell in the memory, the logic value in the storage cell cannot jump; when a coupling fault occurs in a storage cell in the memory, a change in the logic value in the storage cell will cause a change in the logic value in an adjacent storage cell. Therefore, by judging whether the actual logic relationship value between the read data in the storage cell and the read data in the adjacent storage cell is consistent with the standard logic relationship value, it is possible to detect whether each storage cell in the memory to be tested has a fault.

[0065] Specifically, the standard logical relationship value can be understood as when the target storage unit has no fault, the read data of the target storage unit and the read data of the adjacent storage unit are logically operated to obtain an accurate logical relationship value, the read data of the read target storage unit and the read data of the adjacent storage unit are logically operated to obtain an actual logical relationship value, and then the actual logical relationship value is compared with the standard logical relationship value to detect whether there is a fault in each storage unit in the memory to be tested. If the actual logical relationship value is consistent with the standard logical relationship value, it is determined that the memory to be tested has no fault. If the actual logical relationship value is inconsistent with the standard logical relationship value, it is determined that the memory to be tested has a fault. Fault, thus the test method in the present application is to detect the fault condition of the memory to be tested through the actual logic relationship value, so that it can effectively detect multiple types of coupling faults that affect the adjacent memory cells before and after the target memory cell performs a write operation, and traverse all memory cells according to the preset progress rule, which reduces the addressing test time and has a higher test efficiency. Compared with the March algorithm, the algorithm in the present application has a lower test complexity, thereby reducing the test time and cost. Compared with the existing algorithm that compares the logic value with the expected value to obtain the fault condition of the memory to be tested, the reliability of the test algorithm can be further improved by using the actual logic relationship value in the present application.

[0066] According to the memory testing method of the embodiment of the present invention, when traversing each memory cell, different logic values ​​are rewritten to the traversed target memory cell and its adjacent memory cells according to the preset progress rule, so that the memory cells in the memory are more prone to failure, and the actual logic relationship value is calculated by reading the read data of the target memory cell and the read data of the adjacent memory cells, and then the actual logic relationship value is compared with the standard logic relationship value to detect the failure of each memory cell. Therefore, compared with the method of comparing the logic value with the expected value in the existing algorithm to obtain the failure condition of the memory to be tested, the actual logic relationship value is used to detect the failure of each memory cell in the present application, which can further improve the reliability of the test algorithm. In addition, compared with the March algorithm, the algorithm in the present application has a lower test complexity, and reads and writes the target memory cell and its adjacent memory cells according to the preset progress rule. This progress method can better sensitize the coupling failure of the memory cell, thereby achieving a higher fault coverage rate.

[0067] In some embodiments, before traversing each storage unit of the memory, it also includes: writing test data to each storage unit of the memory to be tested, that is, accessing each storage unit of the memory to be tested through the address transmitted by the address bus, and then writing test data to each storage unit through a write operation.

[0068] In some embodiments, the test data includes a preset logic value and an opposite value of the preset logic value, and the preset logic value and the opposite value of the preset logic value are alternately written to each storage unit of the memory to be tested, thereby achieving a checkerboard distribution of all storage units, improving fault coverage, and enhancing the reliability of the test results. Exemplarily, all storage units of the memory to be tested are array partitioned to facilitate subsequent checkerboard write operations on all storage units, such as Figure 3 As shown, all memory cell arrays are divided into area A and area B, and the divided area A and area B are not continuous in rows and columns of the memory cell array. When a preset logic value is written to a memory cell in area A, the opposite value of the preset logic value is written to the memory cell in area B, so that the preset logic values ​​written in adjacent memory cells are opposite and conform to a specific logical relationship. For example, when the preset logic value written to the memory cell in the first row and the first column is 1, 0 is written to the memory cell in the first row and the second column, and so on, and different logic values ​​are alternately written to all memory cells of the memory to be tested.

[0069] It should be noted that when alternately writing a preset logic value and the opposite value of the preset logic value to each storage cell of the memory to be tested, the writing can be performed in the order from the storage cell with a low address bit to the storage cell with a high address bit, or in the order from the storage cell with a high address bit to the storage cell with a low address bit.

[0070] In some embodiments, each storage cell of the memory to be tested is traversed, and during the traversal process, data reading and writing operations are performed on the traversed target storage cell and the adjacent storage cells adjacent to the target storage cell according to a preset progress rule, including: a first traversal of each storage cell along a first order; in the first traversal, data reading and writing operations are performed on the traversed target storage cell and the storage cells adjacent to the target storage cell according to the preset progress rule until all storage cells of the memory to be tested are traversed, in this way, the coupling faults of the storage cells can be better sensitized, thereby achieving a higher fault coverage rate.

[0071] Furthermore, after each storage cell is traversed for the first time along the first order, each storage cell is traversed for the second time along the second order; in the second traversal, data reading and writing operations are performed on the traversed target storage cell and the storage cells adjacent to the target storage cell according to the preset progress rules until all storage cells of the memory to be tested are traversed.

[0072] Specifically, each storage unit is traversed for the first time along the first order. In the first traversal, the test data stored in the traversed target storage unit and its adjacent storage units are read and the logic values ​​are rewritten according to the preset progress rule. The preset progress rule can be understood as traversing all storage units with one or more storage units as progress units, that is, different read and write operations are performed on the test data stored in the traversed target storage unit and the adjacent storage units according to one or more storage units as units, wherein the adjacent storage units of the target storage unit are the storage units corresponding to the previous address of the address corresponding to the target storage unit and the storage units corresponding to the next address. Corresponding storage cells are traversed until all storage cells of the memory to be tested are traversed, and after each storage cell is traversed for the first time along the first order, the test data of each storage cell is traversed for the second time along the second order, and in the second traversal, the traversed target storage cells and adjacent storage cells are read and the logic values ​​are rewritten according to the preset progress rule until all storage cells of the memory to be tested are traversed. Therefore, in the present application, the preset progress rule is used to perform read and write operations on the target storage cell and its adjacent storage cells, and this progress method can better sensitize the coupling faults of the storage cells, thereby achieving a higher fault coverage rate.

[0073] In an embodiment, each storage unit may be traversed multiple times, and the more traversals there are, the higher the fault coverage rate will be.

[0074] In some embodiments, the first sequence starts from the memory cell with the lower address bit and increases to the memory cell with the higher address bit.

[0075] Specifically, the address pointer is pointed to the storage unit corresponding to the low address bit, and the test data of the storage unit is traversed for the first time. In the first traversal, the storage unit corresponding to the traversed low address bit and its adjacent storage units are read and written according to the preset progress rule, starting from the storage unit of the low address bit, that is, the address pointer is incremented by one to point to the next storage unit corresponding to the storage unit of the low address bit, and the storage unit corresponding to the traversed address pointer incremented by one and its adjacent storage units are read and written according to the preset progress rule, and then it is determined whether the address pointer points to the storage unit corresponding to the highest address bit. If the address pointer does not point to the storage unit corresponding to the highest address bit, it means that all storage units have not been traversed during the first traversal process. If the address pointer points to the storage unit corresponding to the highest address bit, it means that all storage units have been traversed during the first traversal process, and the first traversal ends. Thus, the test data of each storage unit is traversed for the first time starting from the storage unit of the low address bit and incrementing until the first traversal ends at the storage unit of the highest address bit.

[0076] In some embodiments, the second order in the second traversal process is consistent with the first order in the first traversal process. For details, please refer to the description of the first traversal process. In order to reduce redundancy, it will not be repeated here.

[0077] It should be noted that, starting from the storage unit corresponding to the lower address bit and proceeding in sequence, the coupling fault between the highest address bit and the lowest address bit can be tested.

[0078] In some embodiments, the second order is to start from the storage cell with a high address bit and decrease until the storage cell with a low address bit ends, that is, the address pointer is pointed to the storage cell corresponding to the high address bit, and the test data of the storage cell is traversed for the second time, and in the second traversal, the storage cell corresponding to the traversed high address bit and its adjacent storage cells are subjected to data read and write operations according to the preset progress rule, and the traversal is performed from the storage cell with a high address bit, that is, the address pointer is reduced by one to point to the previous storage cell corresponding to the storage cell with a high address bit, and the storage cell corresponding to the traversed address pointer reduced by one and its adjacent storage cells are subjected to data read and write operations according to the preset progress rule, and then it is determined whether the address pointer points to the storage cell corresponding to the lowest address bit. If the address pointer does not point to the storage cell corresponding to the lowest address bit, it means that not all storage cells have been traversed during the second traversal. If the address pointer points to the storage cell corresponding to the lowest address bit, it means that all storage cells have been traversed during the second traversal, and the second traversal ends. Therefore, the test data of each storage cell is traversed for the second time starting from the storage cell with the higher address bit and decreasingly until the second traversal ends at the storage cell with the lowest address bit.

[0079] Therefore, the memory testing method in the present application traverses the test data of all storage cells in the memory to be tested in a linear address increasing or decreasing manner, and after traversing all storage cells, the logic values ​​in all storage cells are flipped.

[0080] In some embodiments, the preset progress rules include: performing a read operation on the target storage cell and the adjacent storage cells of the target storage cell, that is, during the traversal process, performing a read operation on the traversed target storage cell and the storage cells adjacent to the target storage cell. Exemplarily, during the traversal process, when the address pointer points to the storage cell in the first row and the first column, the logical values ​​stored in the storage cell in the first row and the first column and the adjacent storage cells are read first, and the adjacent storage cells of the storage cell in the first row and the first column are the storage cells in the first row and the second column.

[0081] In the embodiments, reference Figure 3 As shown, each storage unit corresponds to an address, and the traversal process is expressed by the following formula:

[0082]

[0083] All storage units are traversed according to the preset progress rule. After writing the test data to each storage unit, each storage unit is first read. The symbol ↑ indicates that all storage units are tested in the positive order of the address, that is, the first order. The symbol ↓ indicates that all storage units are tested in the order opposite to the first order. The symbol Indicates testing all memory cells in positive or reverse order of addresses. A 1 indicates the operation of writing the preset logic value 1 into the storage unit A, W B 0 represents the operation of writing the opposite value 0 of the preset logic value into the storage unit B; W A 0 means that the preset logic value 0 is written to the storage unit A. B 1 indicates the operation of writing the opposite value 1 of the preset logic value into the memory cell B. A Represents the operation of reading the logical values ​​in memory cell A and its adjacent memory cells, R AB Represents the operation of reading memory cell A and memory cell B and their adjacent memory cells, R B Represents the operation of reading the logical values ​​in a storage cell and its adjacent storage cells. Assuming that the number of storage cells to be tested is M, the number of storage cells A is M / 2, and the number of storage cells B is M / 2. From the above formula, it can be obtained that the test complexity for each read and write operation is M / 2, so the complexity of the algorithm in this application is 6M, and the formula of the March algorithm is The complexity of the algorithm is 7M, so the test complexity of the algorithm in this application is lower.

[0084] In the second traversal of the test data of each storage unit along the second sequence, if the second sequence is to increase from the storage unit with the lower address bit, the traversal is performed according to the content of the first traversal, such as Figure 5 As shown, the result of the change of the logic values ​​in all storage cells after the second traversal.

[0085] In an embodiment, when a fixed-type fault occurs in a storage cell in the memory, the logic value in the storage cell cannot change; when a jump-type fault occurs in a storage cell in the memory, the logic value in the storage cell cannot jump; when a coupling fault occurs in a storage cell in the memory, a change in the logic value in the storage cell will cause the logic values ​​in other storage cells to change. Therefore, in order to detect whether each storage cell in the memory to be tested has a fault, the present application uses two adjacent storage cells and storage cells as the moving units to traverse all storage cells, and in the two traversal processes, the logic value in each storage cell in the memory to be tested is flipped twice, and the read data in each storage cell and the adjacent storage cell are read before and after each storage cell is flipped, and by judging whether the actual logic relationship value of the read data in the storage cell and the adjacent storage cell meets the standard logic relationship value, it is detected whether each storage cell in the memory to be tested has a fault.

[0086] In some embodiments, the actual logic relationship value is determined based on the read data of the target storage unit and the read data of the adjacent storage unit, and then the actual logic relationship value is compared with the standard logic relationship value to determine whether the memory to be tested has a fault, as described below.

[0087] In some embodiments, the adjacent storage unit includes a subsequent storage unit of the target storage unit. When the target storage unit has not failed, the logic value in the target storage unit is different from the logic value in the adjacent storage unit. Therefore, the fault test of the memory in the present application can be performed by performing a logical AND operation on the first read data and the first read data to obtain the corresponding actual logic relationship value, and then comparing the actual logic relationship value with the standard logic relationship value to detect whether each storage unit has a fault. That is, a read operation is performed on the target storage unit to obtain the first read data, a read operation is performed on the subsequent storage unit to obtain the second read data, and the first read data is logically ANDed with the second read data to obtain the first read data and the second read data. The actual logical relationship value of the second read data is then compared with the standard logical relationship value to determine whether there is a fault in each storage unit in the memory to be tested, wherein the standard logical relationship value of the logical AND operation of the first read data and the second read data is 0. If the actual logical relationship value is determined to be 0, the actual logical relationship value is consistent with the standard logical relationship value, which means that the logical value in the target storage unit is different from the logical value in the next storage unit, and it is detected that there is no fault in the target storage unit. If the actual logical relationship value is determined to be 1, the actual logical relationship value is inconsistent with the standard logical relationship value, which means that the logical value in the target storage unit is the same as the logical value in the next storage unit, and it is detected that there is a fault in the target storage unit.

[0088] For example, Figure 3 and Figure 4 As shown, assuming that the target storage unit is the storage unit in the first row and first column, that is, the address of the target storage unit is the first row and first column, based on the latter address being the address of the target storage unit plus 1, that is, the latter address is the first row and second column, the latter storage unit is the storage unit in the first row and second column, if the logical value read into the target storage unit, that is, the storage unit in the first row and first column, that is, the first read data, is 1, and the logical value read into the latter storage unit, that is, the storage unit in the first row and second column, that is, the second read data, is 0, the actual logical relationship value obtained by performing a logical AND operation on the first read data and the second read data is 0, and the standard logical relationship value is 0, then it is detected that the target address storage unit, that is, the storage unit in the first row and first column, has no fault; conversely, if the first read data read is 0, and the second read data read is 0, then the actual logical relationship value is 1, which is inconsistent with the standard logical relationship value, then it is detected that the target storage unit, that is, the storage unit in the first row and first column, has a fault.

[0089] In some embodiments, since the logic value in the target storage unit is different from the logic value in the adjacent storage unit when the target storage unit has not failed, the fault test of the memory in the present application can be performed by performing a logical OR operation on the first read data and the second read data to obtain the corresponding actual logic relationship value, and then comparing the actual logic relationship value with the standard logic relationship value to detect whether each storage unit has a fault, that is, performing a logical OR operation on the first read data and the second read data to obtain the actual logic relationship value satisfied by the first read data and the second read data, and then comparing the actual logic relationship value with the standard logic relationship value to determine whether each storage unit in the memory to be tested has a fault, wherein the standard logic relationship value of the logical OR operation of the first read data and the second read data is 1, if the actual logic relationship value is determined to be 1, the actual logic relationship value is consistent with the standard logic relationship value, which means that the logic value in the target storage unit is different from the logic value in the next storage unit, and it is detected that the target storage unit has no fault; if the actual logic relationship value is determined to be 0, the actual logic relationship value is inconsistent with the standard logic relationship value, which means that the logic value in the target storage unit is the same as the logic value in the next storage unit, and it is detected that the target storage unit has no fault.

[0090] For example, Figure 3 and Figure 4 As shown, assuming that the target storage unit is the storage unit in the first row and first column, that is, the address of the target storage unit is the first row and first column, based on the latter address being the address of the target storage unit plus 1, that is, the latter address is the first row and second column, the latter storage unit is the storage unit in the first row and second column, when the address pointer points to the first row and first column, if the logical value read from the target storage unit, that is, the storage unit in the first row and first column, that is, the first read data, is 1, and the logical value read from the latter storage unit, that is, the storage unit in the first row and second column, that is, the second read data, is 0, and the actual logical relationship value obtained by performing a logical OR operation on the first read data and the second read data is 1, then it is detected that the target storage unit, that is, the storage unit in the first row and first column, has no fault; conversely, if the first read data read is 0, and the second read data read is 0, the actual logical relationship value is 0, then it is detected that the target storage unit, that is, the storage unit in the first row and first column, has a fault.

[0091] Therefore, when the first read data and the second read data are subjected to a logical OR operation and / or a logical AND operation, and the first read data and the second read data are subjected to a logical OR operation and a logical AND operation at the same time, the fault test of the memory can be made more accurate and the fault coverage rate can be higher.

[0092] In some embodiments, the adjacent storage unit includes the previous storage unit of the target storage unit. Since when the target storage unit has not failed, the logic value in the target storage unit is the same as the logic value in the adjacent storage unit, i.e., the previous address storage unit. Therefore, the fault test of the memory in the present application can obtain the corresponding actual logic relationship value by performing a logical XOR operation on the first read data and the third read data, and then compare the actual logic relationship value with the standard logic relationship value to detect whether each storage unit has a fault. That is, a read operation is performed on the target storage unit to obtain the first read data, a read operation is performed on the previous storage unit to obtain the third read data in the storage unit, and a logical XOR operation is performed on the first read data and the third read data to obtain The actual logical relationship value satisfied by the first read data and the third read data is then compared with the standard logical relationship value to determine whether there is a fault in each storage unit in the memory to be tested, wherein the standard logical relationship value of the logical XOR operation of the first read data and the third read data is 0. If the actual logical relationship value is determined to be 0, the actual logical relationship value is consistent with the standard logical relationship value, which means that the logical value in the target storage unit is the same as the logical value in the previous storage unit, and it is detected that there is no fault in the target storage unit; if the actual logical relationship value is determined to be 1, the actual logical relationship value is inconsistent with the standard logical relationship value, which means that the logical value in the target storage unit is different from the logical value in the previous storage unit, and it is detected that there is a fault in the target storage unit.

[0093] For example, Figure 3 and Figure 4 As shown, assuming that the target storage unit is the storage unit in the first row and third column, that is, the address of the target storage unit is the first row and third column, based on the previous address being the address of the target storage unit minus 1, that is, the previous address is the first row and second column, then the previous storage unit is the storage unit in the first row and second column, if the logical value read from the target storage unit, i.e., the storage unit in the first row and third column, i.e., the first read data, is 1, and the logical value read from the previous storage unit, i.e., the storage unit in the first row and second column, i.e., the third read data, is 1, and the actual logical relationship value obtained by performing a logical OR operation on the first read data and the third read data is 0, then it is detected that the target storage unit, i.e., the storage unit in the first row and third column, has no fault; conversely, if the first read data read is 0, and the third read data read is 1, the actual logical relationship value is 1, then it is detected that the target storage unit, i.e., the storage unit in the first row and third column, has a fault.

[0094] In some embodiments, the preset progress rules also include: performing a data flip operation on the target storage unit, that is, during the traversal process, performing a data flip operation on the traversed target storage unit. Exemplarily, during the traversal process, when the address pointer points to the storage unit in the first row and the first column, after reading the logic values ​​stored in the storage unit in the first row and the first column and the adjacent storage units, a data flip operation is performed on the storage unit in the first row and the first column. If the logic value in the storage unit in the first row and the first column is 1, then after the data flip operation is performed on the storage unit in the first row and the first column, the logic value in the storage unit in the first row and the first column is 0.

[0095] In some embodiments, the adjacent storage unit includes a subsequent storage unit of the target storage unit. Since when the target storage unit has not failed, the logic value in the flipped target storage unit is the same as the logic value in the adjacent storage unit. Therefore, the fault test of the memory in the present application can be performed by performing a logical XOR operation on the fourth read data and the second read data to obtain the corresponding actual logical relationship value, and then comparing the actual logical relationship value with the standard logical relationship value to detect whether each storage unit has a fault. That is, a read operation is performed on the flipped target storage unit to obtain the flipped logic value in the target storage unit, namely, the fourth read data, a read operation is performed on the subsequent storage unit to obtain the second read data, and a logical XOR operation is performed on the fourth read data and the second read data to obtain the fourth The actual logical relationship value satisfied by the read data and the second read data is then compared with the standard logical relationship value to determine whether there is a fault in each storage unit in the memory to be tested, wherein the standard logical relationship value of the fourth read data and the second read data for the logical XOR operation is 0. If the actual logical relationship value is determined to be 0, the actual logical relationship value is consistent with the standard logical relationship value, which means that the logical value in the target storage unit after the flip is the same as the logical value in the subsequent storage unit, and it is detected that there is no fault in the target storage unit; if the actual logical relationship value is determined to be 1, the actual logical relationship value is inconsistent with the standard logical relationship value, which means that the logical value in the target storage unit after the flip is different from the logical value in the subsequent storage unit, and it is detected that there is a fault in the target storage unit.

[0096] For example, Figures 3 to 5As shown, assuming that the target storage unit is the storage unit in the first row and third column, that is, the address where the target storage unit is located is the first row and third column, based on the fact that the next address is the address where the target storage unit is located plus 1, that is, the next address is the first row and fourth column, the next storage unit is the storage unit in the first row and fourth column, if the logic value in the flipped target storage unit, that is, the storage unit in the first row and third column, that is, the fourth read data, is 0, and the logic value of the next storage unit, that is, the storage unit in the first row and fourth column, that is, the second read data, is 0, a logical exclusive OR operation is performed on the fourth read data and the second read data If the actual logical relationship value obtained is 0, it means that the logical value changes after flipping the target storage unit, i.e. the storage unit in the first row and third column, and the logical value in the next storage unit, i.e. the storage unit in the first row and fourth column, will not change when flipping the target storage unit, i.e. the storage unit in the first row and third column, that is, it is detected that there is no fault in the target storage unit, i.e. the storage unit in the first row and third column; conversely, if the fourth read data read is 1 and the second read data read is 0, the actual logical relationship value is 1, then it is detected that the target storage unit, i.e. the storage unit in the first row and third column, has a jump type fault.

[0097] In some embodiments, the adjacent storage unit includes a previous storage unit of the target storage unit. Since, when the target storage unit has not failed, the logic value in the flipped target storage unit is different from the logic value in the flipped adjacent storage unit, i.e., the previous storage unit, the fault test of the memory in the present application can be performed by performing a logical AND operation on the fourth read data and the third read data to obtain a corresponding actual logic relationship value, and then comparing the actual logic relationship value with the standard logic relationship value to detect whether each storage unit has a fault, that is, a read operation is performed on the flipped target storage unit to obtain the fourth read data, a read operation is performed on the previous storage unit to obtain the third read data, and a logical AND operation is performed on the fourth read data and the third read data to obtain the fourth read data. The actual logical relationship value satisfied by the data and the third read data is then compared with the standard logical relationship value to determine whether there is a fault in each storage unit in the memory to be tested, wherein the standard logical relationship value of the fourth read data and the third read data is 0. If the actual logical relationship value is determined to be 0, the actual logical relationship value is consistent with the standard logical relationship value, which means that the logical value in the target storage unit after the flip is different from the logical value in the previous storage unit after the flip, and it is detected that there is no fault in the target storage unit; if the actual logical relationship value is determined to be 1, the actual logical relationship value is inconsistent with the standard logical relationship value, which means that the logical value in the target storage unit after the flip is the same as the logical value in the previous storage unit after the flip, and it is detected that there is a fault in the target storage unit.

[0098] For example, Figures 3 to 5As shown, the target storage unit is the storage unit in the first row and the third column, that is, the address of the target storage unit is the first row and the third column, based on the previous address being the address of the target storage unit minus 1, that is, the previous address is the first row and the second column, and the previous storage unit is the storage unit in the first row and the second column, if the logic value in the storage unit in the first row and the third column after the flip is read, that is, the fourth read data is 0, if the logic value in the storage unit in the first row and the second column after the flip is read, that is, the third read data is 1, the fourth read data is logically combined with the third read data The actual logical relationship value obtained by the AND operation is 0, which means that the logical value changes after flipping the first row and third column storage unit, and when the target storage unit, i.e., the first row and third column storage unit, is flipped, the logical value in the previous storage unit, i.e., the first row and second column storage unit, does not change. It is detected that the target storage unit, i.e., the first row and third column storage unit, has no fault. On the contrary, if the fourth read data read is 1 and the third read data read is 1, the actual logical relationship value is 1, then it is detected that the target storage unit, i.e., the first row and third column storage unit, has a jump type fault.

[0099] In some embodiments, since when the target storage unit has not failed, the logic value in the flipped target storage unit is different from the logic value in the flipped adjacent storage unit, the fault test of the memory in the present application can be performed by performing a logical XOR operation on the fourth read data and the third read data to obtain the corresponding actual logical relationship value, and then comparing the actual logical relationship value with the standard logical relationship value to detect whether each storage unit has a fault, that is, performing a logical XOR operation on the fourth read data and the third read data to obtain the actual logical relationship value satisfied by the fourth read data and the third read data, and then comparing the actual logical relationship value with the standard logical relationship value. comparison to determine whether there is a fault in each storage unit in the memory to be tested, wherein the standard logical relationship value of the fourth read data and the third read data for logical OR operation is 1, if the actual logical relationship value is determined to be 1, the actual logical relationship value is consistent with the standard logical relationship value, which means that the logical value in the target storage unit after the flip is different from the logical value in the previous storage unit after the flip, and it is detected that there is no fault in the target storage unit; if the actual logical relationship value is determined to be 0, the actual logical relationship value is inconsistent with the standard logical relationship value, which means that the logical value in the target storage unit after the flip is the same as the logical value in the previous storage unit after the flip, and it is detected that there is a fault in the target storage unit.

[0100] For example, Figures 3 to 5As shown, assuming that the target storage unit is the storage unit in the first row and third column, that is, the address of the target storage unit is the first row and third column, based on the previous address being the address of the target storage unit minus 1, that is, the previous address is the first row and second column, the previous storage unit is the storage unit in the first row and second column, if the logic value in the storage unit in the first row and third column after flipping, that is, the fourth read data, is 0, and the logic value of the target storage unit in the first row and second column after flipping, that is, the third read data, is 1, the actual logic relationship value obtained by performing a logical OR operation on the fourth read data and the third read data is 1, then it means that the logic value changes after flipping the target storage unit, that is, the storage unit in the first row and third column, and the logic value in the storage unit in the first row and second column does not change when flipping the target storage unit, that is, the storage unit in the first row and third column, that is, it is detected that there is no fault in the storage unit in the first row and third column. On the contrary, if the fourth read data is 0 and the third read data is 0, the actual logic relationship value is 0, then it is detected that the target storage unit, that is, the storage unit in the first row and third column, has a coupling fault.

[0101] Therefore, when the fourth read data and the third read data are subjected to a logical OR operation and / or a logical AND operation, and the fourth read data and the third read data are subjected to a logical OR operation and a logical AND operation at the same time, the fault test of the memory can be made more accurate and the fault coverage rate can be higher.

[0102] In some embodiments, the preset progress rule also includes: performing a read operation on the flipped storage unit in units of preset progress units, such as traversing the entire memory to be tested using multiple adjacent storage units as progress units, and performing a read operation on the flipped storage unit during the traversal process.

[0103] In some embodiments, two adjacent storage units are used as preset moving units.

[0104] Exemplarily, during the traversal process, the address pointer points to the storage cell of the first row and the first column, and the logic values ​​stored in the storage cell of the first row and the first column and the adjacent storage cells are read. Then, a data flip operation is performed on the logic values ​​in the storage cell of the first row and the first column, so that the logic values ​​stored in the storage cell of the first row and the first column are changed from 1 to 0. Then, the logic values ​​in the storage cell of the first row and the first column and the adjacent storage cells are read. The adjacent storage cells of the storage cell of the first row and the first column are the storage cells of the first row and the second column. After the address pointer is incremented by one, it points to the storage cell of the first row and the second column, and the logic values ​​stored in the storage cell of the first row and the second column and the adjacent storage cells are read. Then, the set logic values ​​in the storage cell of the first row and the second column are flipped, so that the logic values ​​stored in the storage cell of the first row and the second column are changed from 0 to 1. Then, the logic values ​​in the storage cell of the first row and the second column and the adjacent storage cells are read. The adjacent storage cells of the storage cell of the first row and the second column are the storage cells of the first row and the third column. Thus, the above content is passed until all the storage cells of the memory to be tested are traversed.

[0105] In some embodiments, since the logic values ​​of the storage cells at the low address bit and the high address bit in the preset traveling unit are different when there is no fault in the storage cells at the low address bit and the high address bit in the preset traveling unit, the fault test of the memory in the present application can be performed by performing a logical AND operation on the fifth read data and the sixth read data to obtain the corresponding actual logical relationship value, and then comparing the actual logical relationship value with the standard logical relationship value to detect whether each storage unit has a fault, that is, a read operation is performed on the storage cell at the low address bit in the preset traveling unit to obtain the fifth read data, and a read operation is performed on the storage cell at the high address bit in the preset traveling unit to obtain the sixth read data, a logical AND operation is performed on the fifth read data and the sixth read data to obtain the actual logical relationship value satisfied by the fifth read data and the sixth read data, and then the actual logical relationship value is compared with the standard logical relationship value. A comparison is performed to determine whether there is a fault in each storage unit in the memory to be tested, wherein the standard logical relationship value of the fifth read data and the sixth read data is 0. If the actual logical relationship value is determined to be 0, the actual logical relationship value is consistent with the standard logical relationship value, which means that the logical value in the storage unit of the low address bit in the preset traveling unit after flipping is different from the logical value in the storage unit of the high address bit in the preset traveling unit after flipping, and it is detected that the storage unit of the low address bit in the preset traveling unit and the storage unit of the high address bit in the preset traveling unit are not faulty; if the actual logical relationship value is determined to be 1, it means that the logical value in the storage unit of the low address bit in the preset traveling unit after flipping is the same as the logical value in the storage unit of the high address bit in the preset traveling unit after flipping, and it is detected that the storage unit of the low address bit in the preset traveling unit and the storage unit of the high address bit in the preset traveling unit are faulty.

[0106] For example, Figures 3 to 5 As shown, assuming that the storage unit with the low address bit in the preset moving unit is the storage unit in the first row and the first column, and the storage unit with the high address bit in the preset moving unit is the storage unit in the first row and the second column, if the logic value in the storage unit with the low address bit after flipping, that is, the storage unit in the first row and the first column, that is, the fifth read data, is 0, and the logic value in the storage unit with the high address bit after flipping, that is, the storage unit in the first row and the second column, that is, the sixth read data, is 1, and the actual logic relationship value obtained by performing a logic AND operation on the fifth read data and the sixth read data is 0, it means that the flipped low address bit is 0. If the logic value of the storage cell of the address bit, i.e., the storage cell of the first row and the first column, changes, and the logic value of the storage cell of the first row and the second column of the storage cell level of the high address bit changes after flipping, it is detected that the storage cell of the low address bit, i.e., the storage cell of the first row and the first column, and the storage cell of the high address bit, i.e., the storage cell of the first row and the second column, are not faulty; conversely, if the fifth read data read is 1, and the sixth read data read is 1, and the actual logical relationship value is 1, it is detected that the storage cell of the low address bit, i.e., the storage cell of the first row and the first column, has a jump type fault.

[0107] In some embodiments, since when the storage unit at the low address bit and the storage unit at the high address bit in the preset advancing unit do not have a fault, the logic value in the storage unit at the low address bit in the preset advancing unit after flipping is different from the logic value in the storage unit at the high address bit after flipping, the fault test of the memory in the present application can determine the actual logic relationship value of the fifth read data and the sixth read data through a logical OR operation, and then compare the actual logic relationship value with the standard logic relationship value to detect whether each storage unit has a fault, that is, perform a logical OR operation on the fifth read data and the sixth read data to obtain the actual logic relationship value of the fifth read data and the sixth read data, and then compare the actual logic relationship value with the standard logic relationship value to determine whether the memory to be tested has a fault. Whether there is a fault in each storage unit, wherein the standard logical relationship value of the logical OR operation of the fifth read data and the sixth read data is 1, if the actual logical relationship value is determined to be 1, it means that the logical value in the storage unit of the low address bit in the preset traveling unit after the flip is different from the logical value in the storage unit of the high address bit in the preset traveling unit after the flip, then it is detected that the storage unit of the low address bit and the storage unit of the high address bit in the preset traveling unit have no fault; if the actual logical relationship value is determined to be 0, it means that the logical value in the storage unit of the low address bit in the preset traveling unit after the flip is the same as the logical value in the storage unit of the high address bit in the preset traveling unit after the flip, then it is detected that the storage unit of the low address bit or the storage unit of the high address bit in the preset traveling unit has a fault.

[0108] For example, Figure 4 and Figure 5 As shown, the storage unit with the low address bit in the preset moving unit is the storage unit in the first row and the first column, and the storage unit with the high address bit in the preset moving unit is the storage unit in the first row and the second column. If the logic value in the storage unit with the low address bit, i.e., the storage unit in the first row and the first column, i.e., the fifth read data, is read as 0, and if the logic value in the storage unit with the high address bit, i.e., the storage unit in the first row and the second column, i.e., the sixth read data, is read as 1, the actual logic relationship value obtained by performing a logic OR operation on the fifth read data and the sixth read data is 1, then it is explained that the logic value of the storage unit with the low address bit, i.e., the storage unit in the first row and the first column, changes after flipping, and the logic value of the storage unit with the high address bit, i.e., the storage unit in the first row and the second column, changes after flipping, that is, it is detected that the storage unit with the low address bit, i.e., the storage unit in the first row and the first column, and the storage unit with the high address bit, i.e., the storage unit in the first row and the second column, do not have a fault. On the contrary, if the fifth read data read is 0, and the third read data read is 0, the actual logic relationship value is 0, then it is detected that the storage unit with the high address bit, i.e., the storage unit in the first row and the second column, has a jump type fault.

[0109] Therefore, when the fifth read data and the sixth read data are subjected to a logical OR operation and / or a logical AND operation, and the fifth read data and the sixth read data are subjected to a logical OR operation and a logical AND operation at the same time, the fault test of the memory can be made more accurate and the fault coverage rate can be higher.

[0110] Based on this, the test method in the present application compares the actual logic relationship value with the standard logic relationship value to obtain the fault condition of the memory to be tested, which can effectively detect multiple types of coupling faults that affect adjacent memory cells before and after the target memory cell performs a write operation.

[0111] In some embodiments, during the traversal process, the present application compares the read data of the target storage unit with the expected data corresponding to the target storage unit to obtain the fault condition of the memory to be tested.

[0112] In some embodiments, the first expected data can be understood as the logical value stored when the storage unit is not flipped when no fault occurs. Therefore, the first read data is compared with the first expected data corresponding to the target storage unit. If it is determined that the first read data is consistent with the first expected data corresponding to the target storage unit, the test result is that there is no fault in the target storage unit of the memory to be tested; if it is determined that the first read data is inconsistent with the first expected data corresponding to the target storage unit, the test result is that there is a fault in the target storage unit of the memory to be tested. Therefore, in this application, the first read data of each storage unit before flipping is compared with the first expected data to detect the fault of each storage unit in the memory to be tested.

[0113] Exemplarily, if the first expected data is 0, and the logic value in the unflipped target storage unit, that is, the first read data, is 1, it is detected that the target storage unit has a fault. Otherwise, if the first read data is 0, it is detected that the target storage unit does not have a fault.

[0114] In some embodiments, the second expected data can be understood as the logic value stored after the storage unit is flipped when no failure occurs. Therefore, the fourth read data is compared with the second expected data corresponding to the target storage unit. If it is determined that the fourth read data is consistent with the second expected data corresponding to the target storage unit, the test result is that there is no failure in the target storage unit of the memory to be tested; if it is determined that the fourth read data is inconsistent with the second expected data corresponding to the target storage unit, the test result is that there is a failure in the target storage unit of the memory to be tested. Therefore, in this application, the fourth read data of each storage unit after flipping is compared with the second expected data to detect the failure of each storage unit of the memory to be tested.

[0115] Exemplarily, if the second expected data is 0, and the logic value in the target storage unit after reading the flip, that is, the second read data is 0, it is detected that the target storage unit has no fault; otherwise, if the second read data is 1, it is detected that the target storage unit has a fault.

[0116] Reference below Figure 6 The memory testing method according to the embodiment of the present invention is illustrated by way of example, and the specific contents are as follows.

[0117] Step S5, start.

[0118] Step S6, partitioning all storage units into arrays.

[0119] Step S7, alternately writing a preset logic value and an opposite value of the preset logic value into each storage unit of the memory to be tested.

[0120] Step S8: the address pointer points to the storage unit corresponding to the low address bit.

[0121] Step S9, performing a read operation on the storage cell at the low address bit and its adjacent storage cells, that is, reading the test data stored in the storage cell at the low address bit and the storage cells corresponding to the previous address bit and the next address bit of the storage cell at the low address bit, and flipping the preset logic value in the storage cell at the low address bit so that the logic value in the storage cell at the low address bit is changed from 1 to 0.

[0122] Step S10, the address pointer is incremented by one.

[0123] Step S11, performing a read operation on the storage cell at the low address bit, the storage cell at the high address bit and their adjacent storage cells, that is, reading the test data stored in the storage cell at the low address bit, the storage cell at the high address bit and the storage cells corresponding to the previous and next address bits of the storage cell at the high address bit, and then flipping the opposite value of the preset logic value in the storage cell at the high address bit, so that the logic value in the storage cell at the high address bit is changed from 0 to 1, and then performing a read operation on the storage cell at the high address bit and its adjacent storage cells.

[0124] Step S12, determine whether the address pointer points to the storage unit corresponding to the highest address bit, if so, execute step S16, otherwise execute the step.

[0125] Step S13, determine whether the actual logical relationship value of the read data of the storage unit and the read data of the adjacent storage unit meets the standard logical relationship value, and determine whether the read data of the storage unit is equal to the expected data. If so, execute step S14, otherwise execute step S15.

[0126] Step S14, the address pointer is incremented by one, and the process returns to step S9.

[0127] Step S15: the target storage unit has a fault.

[0128] Step S16, performing a read operation on the storage unit at the lower address and its adjacent storage units, and flipping the preset logic value in the storage unit at the lower address, so as to change the logic value in the storage unit at the lower address from 0 to 1.

[0129] Step S17, the address pointer is reduced by one.

[0130] Step S18, performing a read operation on the storage cell at the low address bit, the storage cell at the high address bit and its adjacent storage cells, and then flipping the opposite value of the preset logic value in the storage cell at the high address bit so that the logic value in the storage cell at the high address bit changes from 1 to 0, and then performing a read operation on the storage cell at the high address bit and its adjacent storage cells.

[0131] Step S19, determining whether the address pointer points to the lowest address bit.

[0132] Step S20, determine whether the actual logical relationship value of the read data of the storage unit and the read data of the adjacent storage unit meets the standard logical relationship value, or determine whether the read data of the storage unit is equal to the expected data. If so, execute step S21, otherwise execute step S22.

[0133] Step S21, the address pointer is reduced by one.

[0134] Step S22: the target storage unit has a fault.

[0135] Step S23, end.

[0136] Reference below Figure 7 The memory testing method according to the embodiment of the present invention is illustrated by way of example, and the specific contents are as follows.

[0137] Step S24, start.

[0138] Step S25, partitioning all storage units into arrays.

[0139] Step S26, alternately writing a preset logic value and an opposite value of the preset logic value into each memory cell of the memory to be tested.

[0140] Step S27, the address pointer points to the storage unit corresponding to the lowest address bit.

[0141] Step S28, performing a read operation on the storage cell at the low address bit and its adjacent storage cells, i.e., reading the test data stored in the storage cell at the low address bit and the storage cells corresponding to the previous and next address bits of the storage cell at the low address bit, and flipping the preset logic value in the storage cell at the low address bit so that the logic value in the storage cell at the high address bit is changed from 1 to 0.

[0142] Step S29, the address pointer is incremented by one.

[0143] Step S30, performing a read operation on the storage cell at the low address bit, the storage cell at the high address bit and its adjacent storage cells, then flipping the opposite value of the preset logic value in the storage cell at the high address bit, so that the logic value in the storage cell at the high address bit changes from 0 to 1, and then performing a read operation on the storage cell at the high address bit and its adjacent storage cells.

[0144] Step S31, determining whether the address pointer points to the storage unit corresponding to the highest address bit, if yes, execute step S35, otherwise execute step S32.

[0145] Step S32, determine whether the actual logical relationship value of the read data of the storage unit and the read data of the adjacent storage unit meets the standard logical relationship value, or determine whether the read data of the storage unit is equal to the expected data. If so, execute step S33, otherwise execute step S34.

[0146] Step S33, the address pointer is incremented by one, and the process returns to step S28.

[0147] Step S34: the target storage unit has a fault.

[0148] Step S35: the address pointer points to the storage unit corresponding to the lowest address bit.

[0149] Step S36, performing a read operation on the storage unit at the lower address and its adjacent storage units, and flipping the preset logic value in the storage unit at the lower address, so that the logic value in the storage unit at the lower address is written as 1.

[0150] Step S37, the address pointer is incremented by one.

[0151] Step S38, performing a read operation on the storage unit at the low address bit, the storage unit at the high address bit and its adjacent storage units, writing the logic value in the storage unit at the high address bit to 0, and then performing a read operation on the storage unit at the high address bit and its adjacent storage units.

[0152] Step S39, determine whether the address pointer points to the highest address bit, if so, execute step S43, otherwise execute step S40.

[0153] Step S40, determine whether the actual logical relationship value of the read data of the storage unit and the read data of the adjacent storage unit meets the standard logical relationship value, or determine whether the read data of the storage unit is equal to the expected data. If so, execute step S41, otherwise execute step S42.

[0154] Step S41, the address pointer is incremented by one.

[0155] Step S42: the target storage unit has a fault.

[0156] Step S43, end.

[0157] A second aspect of the present invention provides a memory testing device 10, such as Figure 8 As shown, the memory testing device 10 includes: a traversal module 2 , an acquisition module 3 and a determination module 4 .

[0158] Among them, the traversal module 2 is used to traverse each storage unit of the memory to be tested. During the traversal process, data read and write operations are performed on the traversed target storage unit and the adjacent storage units adjacent to the target storage unit according to the preset progress rules; the acquisition module 3 is used to perform logical operations on the read data of the target storage unit and the read data of the adjacent storage unit to obtain the actual logical relationship value; the determination module 4 is used to determine that the memory to be tested has a fault when the actual logical relationship value is inconsistent with the standard logical relationship value.

[0159] According to the memory testing device 10 of the embodiment of the present invention, the fault condition of the memory can be detected through the actual logic relationship value, the reliability of the test algorithm is high, the fault coverage and test complexity are taken into account at the same time, and the fault test efficiency is high.

[0160] A third aspect of the present invention provides a computer storage medium having a computer program stored thereon, wherein the computer program implements the memory testing method in the above embodiment when executed by a processor.

[0161] A fourth aspect of the present invention provides an electronic device 20, such as Fig. 9 As shown, the electronic device includes: at least one processor 5 and a memory 6 communicatively connected to the at least one processor 5 .

[0162] The memory 6 stores a computer program that can be executed by at least one processor 5 , and the memory testing method in the above embodiment is implemented when the at least one processor 5 executes the computer program.

[0163] According to the electronic device 20 of the embodiment of the present invention, the fault condition of the memory can be detected through the actual logic relationship value, the reliability of the test algorithm is high, the fault coverage and test complexity are taken into account at the same time, and the fault test efficiency is high.

[0164] In the description of this specification, any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code including one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

[0165] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0166] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0167] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0168] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0169] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0170] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0171] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A memory testing method, characterized in that: include: Traversing each storage unit of the memory to be tested, and in the traversal process, performing data reading and writing operations on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value; If the actual logic relationship value is inconsistent with the standard logic relationship value, it is determined that the memory to be tested has a fault.

2. The memory testing method according to claim 1, characterized in that: Before traversing each storage unit of the memory, the method further includes: Writing test data into each storage unit of the memory to be tested.

3. The memory testing method according to claim 2, characterized in that: The test data includes a preset logic value and an opposite value of the preset logic value, and writing the test data into each storage unit of the memory to be tested includes: The preset logic value and the opposite value of the preset logic value are alternately written into each storage unit of the memory to be tested.

4. The memory testing method according to claim 3, characterized in that: The traversing of each storage unit of the memory to be tested, during the traversing process, performing data reading and writing operations on the traversed target storage unit and the adjacent storage units adjacent to the target storage unit according to a preset progress rule, includes: Perform a first traversal of each storage unit along the first sequence; In the first traversal, data reading and writing operations are performed on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule until all storage units of the memory to be tested are traversed.

5. The memory testing method according to claim 4, characterized in that: After the first traversal of each storage unit along the first order, the method includes: Perform a second traversal of each storage unit along the second sequence; In the second traversal, data reading and writing operations are performed on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule until all storage units of the memory to be tested are traversed.

6. The memory testing method according to claim 5, characterized in that: The first sequence is to increase from the storage unit of the lower address bit to the storage unit of the higher address bit; The second order is consistent with the first order.

7. The memory testing method according to claim 5, characterized in that: The first sequence is to increase from the storage unit of the lower address bit to the storage unit of the higher address bit; The second sequence is to start from the storage unit with a higher address and decrease to the storage unit with a lower address.

8. The memory testing method according to claim 4, characterized in that: The preset travel rules include: A read operation is performed on the target storage unit and on storage units adjacent to the target storage unit.

9. The memory testing method according to claim 8, characterized in that: The adjacent storage unit includes a storage unit after the target storage unit; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value, including: A logical AND operation is performed on the first read data and the second read data to obtain an actual logical relationship value, wherein the first read data is obtained by performing a read operation on the target storage unit, and the second read data is obtained by performing a read operation on the subsequent storage unit.

10. The memory testing method according to claim 8 or 9, characterized in that: The adjacent storage unit includes a storage unit after the target storage unit; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value, including: A logical OR operation is performed on the first read data and the second read data to obtain an actual logical relationship value, wherein the first read data is obtained by performing a read operation on the target storage unit, and the second read data is obtained by performing a read operation on the subsequent storage unit.

11. The memory testing method according to claim 8, characterized in that: The adjacent storage unit includes a previous storage unit of the target storage unit; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value, including: A logical exclusive OR operation is performed on the first read data and the third read data to obtain an actual logical relationship value, wherein the first read data is obtained by performing a read operation on the target storage unit, and the third read data is obtained by performing a read operation on the previous storage unit.

12. The memory testing method according to claim 8, characterized in that: The preset travel rules also include: A data flip operation is performed on the target storage unit.

13. The memory testing method according to claim 12, characterized in that: The adjacent storage unit includes a storage unit after the target storage unit; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value, including: A logical XOR operation is performed on the fourth read data and the second read data to obtain an actual logical relationship value, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit, and the second read data is obtained by performing a read operation on the subsequent storage unit.

14. The memory testing method according to claim 12, characterized in that: The adjacent storage unit includes a previous storage unit of the target storage unit; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value, including: A logical AND operation is performed on the fourth read data and the third read data to obtain an actual logical relationship value, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit, and the third read data is obtained by performing a read operation on the previous storage unit.

15. The memory testing method according to claim 12 or 14, characterized in that: The adjacent storage unit includes a previous storage unit of the target storage unit; Performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value, including: A logical OR operation is performed on the fourth read data and the third read data to obtain an actual logical relationship value, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit, and the third read data is obtained by performing a read operation on the previous storage unit.

16. The memory testing method according to claim 12, characterized in that: The preset travel rules also include: The flipped storage unit is read in units of preset moving units.

17. The memory testing method according to claim 16, characterized in that: Two adjacent storage units are used as the preset moving units.

18. The memory testing method according to claim 17, characterized in that: The memory testing method further includes: A logical AND operation is performed on the fifth read data and the sixth read data to obtain an actual logical relationship value, wherein the fifth read data is obtained by performing a read operation on a storage unit at a low address bit in the preset forward unit, and the sixth read data is obtained by performing a read operation on a storage unit at a high address bit in the preset forward unit.

19. The memory testing method according to claim 17 or 18, characterized in that: The memory testing method further includes: A logical OR operation is performed on the fifth read data and the sixth read data to obtain an actual logical relationship value, wherein the fifth read data is obtained by performing a read operation on a storage unit at a low address bit in the preset forward unit, and the sixth read data is obtained by performing a read operation on a storage unit at a high address bit in the preset forward unit.

20. The memory testing method according to claim 1, characterized in that: Also includes: If the actual logic relationship value is consistent with the standard logic relationship value, it is determined that the memory to be tested is normal.

21. The memory testing method according to claim 1, characterized in that: The memory testing method further includes: During the traversal process, the test result of the memory to be tested is determined according to the read data of the target storage unit and the expected data corresponding to the target storage unit.

22. The memory testing method according to claim 21, characterized in that: Determining a test result of the memory to be tested according to the read data of the target storage unit and the expected data corresponding to the target storage unit, comprising: If it is determined that the first read data is consistent with the first expected data corresponding to the target storage unit, then it is determined that the memory to be tested is normal, wherein the first read data is obtained by performing a read operation on the target storage unit before flipping.

23. The memory testing method according to claim 21, characterized in that: Determining a test result of the memory to be tested according to the read data of the target storage unit and the expected data corresponding to the target storage unit, comprising: If it is determined that the first read data is inconsistent with the first expected data corresponding to the target storage unit, it is determined that the memory under test has a fault, wherein the first read data is obtained by performing a read operation on the target storage unit before flipping.

24. The memory testing method according to claim 21, characterized in that: Determining a test result of the memory to be tested according to the read data of the target storage unit and the expected data corresponding to the target storage unit, comprising: If it is determined that the fourth read data is consistent with the second expected data corresponding to the target storage unit, it is determined that the memory to be tested is normal, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit.

25. The memory testing method according to claim 21, characterized in that: Determining a test result of the memory to be tested according to the read data of the target storage unit and the expected data corresponding to the target storage unit, comprising: If it is determined that the fourth read data is inconsistent with the second expected data corresponding to the target storage unit, it is determined that the memory under test has a fault, wherein the fourth read data is obtained by performing a read operation on the flipped target storage unit.

26. A memory testing device, characterized in that: include: A traversal module, used for traversing each storage unit of the memory to be tested, and during the traversal process, performing data read and write operations on the traversed target storage unit and adjacent storage units adjacent to the target storage unit according to a preset progress rule; An obtaining module, used for performing a logic operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logic relationship value; The determination module is used to determine that the memory to be tested has a fault when the actual logic relationship value is inconsistent with the standard logic relationship value.

27. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the memory testing method according to any one of claims 1 to 26 is implemented.

28. An electronic device, characterized in that: include: at least one processor; a memory communicatively coupled to at least one of the processors; The memory stores a computer program executable by at least one of the processors, and when at least one of the processors executes the computer program, the memory testing method according to any one of claims 1 to 26 is implemented.

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