DRAM testing method, device, readable storage medium and electronic device
By conducting two rounds of testing on DRAM, using alternate row access and inverse data writing, combined with refresh operations, the problem of difficulty in detecting bridge faults and coupling faults in the prior art is solved, and the fault coverage and test reliability are improved.
Patent Information
- Application Number
- CN202011456909.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-11
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2040-12-11
AI Technical Summary
The prior art is difficult to effectively detect bridge faults and coupling faults in DRAM, especially in the case of specific potential differences, resulting in low test coverage and difficult to detect chip defects.
Using two rounds of testing methods, alternate row access to the DRAM to be tested, write preset test data and its inverse number, and perform refresh operations in the storage array to compare the data of the target row and its adjacent rows to improve the failure. Coverage.
Through the comparison results of two rounds of tests, the previous test blind spots can be covered, multiple memory units can be stimulated, fault coverage and reliability of test results can be improved, and product benignity can be enhanced.
Smart Images
Figure CN112599178B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of DRAM chip testing, and in particular to a DRAM testing method, device, readable storage medium and electronic equipment. Background Art
[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems. Different platforms include Double Data Rate (DDR) modules for personal computers or servers and Low Power Double Data Rate (LPDDR) chips for embedded ARM architecture.
[0003] The basic storage unit of LPDDR is cell. Computers and embedded systems store and read data by writing high or low levels in cells.
[0004] In addition, the current DRAM uses a burst read and write mode for efficient access rate, that is, the read and write operations in a storage array are performed in units of burst length (Burst Length, BL), and the read and write of multiple bits (such as 8 or 16 bits) of column addresses are operated at a time, and the data composed of 0 and 1 is accessed in each burst length. For example, if the address is located at row 0 and the burst length is 8 bits, then 1 bit of data is written to each bit in the space from row 0, column 0 to row 0, column 7, for a total of 8 bits. The second burst length is from row 0, column 8 to column 15, and so on. When all the storage locations of a row are written, the memory controller (Memory Controller, MC) locates the address of the next row and continues the same operation.
[0005] Due to the characteristics of DRAM's internal structure, the storage cells used to store information will continue to leak electricity. When the leakage reaches a certain level, the data in the cells will be lost. Therefore, it is necessary to rewrite the current data to the storage cells before the data is lost, i.e. refresh (REF). If the DRAM works normally, the data will remain unchanged after the refresh. If there are defects or it is under extreme conditions, the data will change after the refresh.
[0006] At the same time, the influence of the process technology makes it possible for the storage unit to cause data storage failure when reading and writing. Storage failures are divided into single-cell and multi-cell failures. Single-cell failures mainly include fixed failures (Stuck at Fault, SF) and transition failures (Transition Fault, TF). The detection of these two types of failures is generally carried out by writing 1 to the unit to be tested, then writing 0 and then reading 0. Correspondingly, it is necessary to write 0, then write 1 and then read 1 for detection. Typical multi-cell failures include: Bridging Fault (BF) and Coupling Fault (CF). For these two failures, the traditional detection method is to write and read the storage cells in the address space in ascending order, and then write and read in descending order to detect whether there are data errors.
[0007] Coupling faults are more likely to be triggered under special circumstances. One of the circumstances is that a cell is at a high level, but the cells around it are all at a low level, or vice versa, a cell is at a low level, but the cells around it are all at a high level. This large potential difference can easily trigger a storage error in the faulty cell. Currently, there is no test method for this fault situation. Summary of the invention
[0008] The technical problem to be solved by the present invention is to provide a DRAM testing method, device, readable storage medium and electronic device, which can improve the coverage of faults when testing DRAM.
[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0010] A DRAM testing method comprises the following steps:
[0011] Perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively;
[0012] The tests include:
[0013] Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data;
[0014] Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed;
[0015] For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested;
[0016] Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data;
[0017] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0018] A test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.
[0019] In order to solve the above technical problems, another technical solution adopted by the present invention is:
[0020] A DRAM testing device, comprising:
[0021] A data reading and writing module is used to perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively;
[0022] The tests include:
[0023] Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data;
[0024] Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed;
[0025] For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested;
[0026] Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data;
[0027] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0028] A testing module is used to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0029] In order to solve the above technical problems, another technical solution adopted by the present invention is:
[0030] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, each step in the above DRAM testing method is implemented.
[0031] In order to solve the above technical problems, another technical solution adopted by the present invention is:
[0032] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned DRAM testing method when executing the computer program.
[0033] The beneficial effects of the present invention are:
[0034] The present invention performs two rounds of tests on the DRAM to be tested, performs row-alternating access to all storage cells that have been written with preset test data, obtains comparison results in the process of row-alternating access, and obtains final test results through comparison results of the two rounds of tests. The present invention can cover previous test blind areas and detect chip defects that are difficult to detect in existing technologies, so that multiple storage unit faults such as bridging faults and coupling faults are stimulated, thereby improving fault coverage, enhancing the reliability of test results, and thus improving product quality. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 A flowchart of a DRAM testing method according to an embodiment of the present invention;
[0036] Figure 2 A schematic diagram of the structure of a DRAM testing device according to an embodiment of the present invention;
[0037] Figure 3 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention;
[0038] Figure 4 A schematic diagram of preset test data and the inverse of the preset test data in the DRAM test method according to an embodiment of the present invention;
[0039] Figure 5 A schematic diagram of a storage array of a DRAM to be tested into which data is written in a DRAM testing method according to an embodiment of the present invention;
[0040] Figure 6 A schematic diagram of writing the inverse of preset test data to adjacent rows of a target row in a DRAM test method according to an embodiment of the present invention;
[0041] Figure 7 A schematic diagram of refreshing the entire memory array of a DRAM to be tested in a DRAM testing method according to an embodiment of the present invention;
[0042] Figure 8 A schematic diagram of reading data of a target row and its adjacent rows in a DRAM testing method according to an embodiment of the present invention;
[0043] Fig. 9 It is a schematic diagram of writing preset test data into adjacent rows after comparison in the DRAM test method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0044] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.
[0045] like Figure 1 As shown, an embodiment of the present invention provides a DRAM testing method, comprising the steps of:
[0046] Perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively;
[0047] The tests include:
[0048] Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data;
[0049] Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed;
[0050] For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested;
[0051] Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data;
[0052] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0053] A test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.
[0054] From the above description, it can be seen that the beneficial effects of the present invention are: by performing two rounds of tests on the DRAM to be tested, all storage cells that have been written with preset test data are accessed alternately in rows, and comparison results are obtained during the row alternating access process. The final test results are obtained by comparing the results of the two rounds of tests. This can cover the previous test blind areas and detect chip defects that are difficult to detect in existing technologies, so that multiple storage unit faults such as bridging faults and coupling faults are stimulated, thereby improving fault coverage, enhancing the reliability of test results, and thus improving product quality.
[0055] Furthermore, writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data includes:
[0056] The preset test data is written starting from the low-order address of each first preset read / write unit of the DRAM to be tested in units of a preset burst length until all storage units of the DRAM to be tested are written with data.
[0057] It can be seen from the above description that by writing preset test data to the DRAM to be tested in units of burst length, the data writing speed can be improved, and the time complexity is low, which is suitable for mass production testing.
[0058] Furthermore, writing the inverse of the preset test data into a row adjacent to the target row comprises:
[0059] The inverse of the preset test data is written to the previous row and the next row of the target row in a preset order in units of a preset burst length. If the previous row or the next row of the target row does not exist, the data writing of the previous row or the next row is omitted.
[0060] From the above description, it can be seen that writing the inverse of the preset test data to the previous row and the next row of the target row causes a large potential difference between the target row and the adjacent row, which can cover the previous test blind area and make it easier to stimulate multiple storage unit faults, thereby improving the fault coverage.
[0061] Furthermore, the reading of the data of the target row and its adjacent rows and comparing the read data with the corresponding written data includes:
[0062] Reading the data of the target row in units of a preset burst length, and comparing the read data with the corresponding written data;
[0063] The data of the adjacent rows of the target row are read in a preset order with a preset burst length as a unit, and the read data are compared with the corresponding written data.
[0064] From the above description, it can be seen that after refreshing the storage array, the data of the target row and the adjacent row are read and compared with the written data. If the DRAM to be tested works normally, the data before and after the refresh are consistent. If there is a defect or it is under extreme conditions, the data before and after the refresh are inconsistent. This can detect whether the DRAM to be tested is fault-free and improve the fault coverage during testing.
[0065] Furthermore, the step of comparing the read data with the corresponding written data includes the following steps:
[0066] The preset test data is written into adjacent rows of the compared target row in a preset order in units of a preset burst length.
[0067] From the above description, it can be seen that by first writing the preset test data to adjacent rows, then writing the inverse of the preset test data, then reading the inverse of the preset test data, and finally writing the preset test data, a single storage unit can be stimulated, thereby improving fault coverage and ensuring the reliability and accuracy of the test.
[0068] Furthermore, the preset sequence includes:
[0069] Firstly, read and write the row before the target row, and then read and write the row after the target row;
[0070] Or, the read and write operations are performed on the row following the target row first, and then the read and write operations are performed on the row preceding the target row.
[0071] From the above description, it can be seen that when performing read and write operations on adjacent rows, the previous row can be read and written first, and then the next row can be read and written, or the next row can be read and written first, and then the previous row can be read and written. This allows the tester to choose the order of alternating row access by himself, which is highly flexible.
[0072] Further, obtaining the test result of the DRAM to be tested according to the first comparison result and the second comparison result includes:
[0073] If the first comparison result and the second comparison result are both consistent, the test result is success; otherwise, the test result is failure.
[0074] It can be seen from the above description that by obtaining the first comparison result and the second comparison result respectively through two rounds of testing, it is possible to detect chip defects that are difficult to find, improve the fault coverage during testing, and ensure the reliability of the test.
[0075] like Figure 2 As shown, another embodiment of the present invention provides a DRAM testing device, comprising:
[0076] A data reading and writing module is used to perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively;
[0077] The tests include:
[0078] Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data;
[0079] Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed;
[0080] For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested;
[0081] Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data;
[0082] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0083] A testing module is used to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0084] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements each step of the above DRAM testing method.
[0085] like Figure 3 As shown, another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned DRAM testing method when executing the computer program.
[0086] The DRAM testing method, device, computer-readable storage medium and electronic device of the present invention can be applied to the testing of any type of DRAM, such as DDR and LPDDR products of various generations, and are described below through specific implementation methods:
[0087] Embodiment 1
[0088] Please refer to Figure 1 , a DRAM testing method, comprising the steps of:
[0089] S1, performing two rounds of testing on the DRAM to be tested, and obtaining a first comparison result and a second comparison result respectively;
[0090] The tests include:
[0091] S11, writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data;
[0092] Specifically, the preset test data is written starting from the low-order address of each first preset read / write unit of the DRAM to be tested in units of a preset burst length until all storage units of the DRAM to be tested are written with data;
[0093] Wherein, the first preset read-write unit can be flexibly set according to actual needs, for example, it can be set to a column or a row;
[0094] The burst length (BL) is determined by the JEDEC standard and can also be set freely, that is, multiple bits (such as 8 bits or 16 bits) are operated at one time for corresponding reading and writing. For example, when writing data based on rows, if the address is row 0 and the burst length is 8 bits, the first 8 bits of the data to be written are written at the same time starting from the position of row 0 and column 0, and then the second burst length is used to write the 9-16 bits of the data to be written. The writing continues until all the storage locations of row 0 are written, and then the address of the next row is relocated, and the operation of the previous row is continued until the data is written to the entire disk. The reading of data is similar.
[0095] In this embodiment, the first preset unit is a row, such as Figure 5 As shown;
[0096] For example, the preset test data is written starting from the first column of the first row. After the first row is written, the preset test data is written starting from the first column of the second row, and so on, until data is written to each row of the DRAM to be tested;
[0097] S12, traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed;
[0098] For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested;
[0099] Specifically, writing the inverse of the preset test data into a row adjacent to the target row includes:
[0100] Writing the inverse of the preset test data to the row before and after the target row in a preset order in units of a preset burst length, and omitting the writing of data of the row before or after if there is no row before or after the target row;
[0101] The preset sequence includes:
[0102] Firstly, read and write the row before the target row, and then read and write the row after the target row;
[0103] Or, first perform the read and write operations on the row after the target row, and then perform the read and write operations on the row before the target row;
[0104] In this embodiment, the preset order is to first perform the read and write operations on the row before the target row, and then perform the read and write operations on the row after the target row;
[0105] For example, for a target row traversed, assuming that the target row has a previous row and a next row, the inverse of the preset test data is first written to the previous row of the target row, and then the inverse of the preset test data is written to the next row of the target row in units of the preset burst length;
[0106] For example, if the target row is the first row, then there is only one row after it, data writing of the row before the target row is omitted, the inverse of the preset test data is written to the row after it, and a refresh operation is performed on the entire storage array of the DRAM to be tested; if the target row is the last row, then there is only one row before it, data writing of the row after the target row is omitted, the inverse of the preset test data is written to the row before it, and a refresh operation is performed on the entire storage array of the DRAM to be tested; if the target row is a row other than the first row and the last row, then there is a row before it and a row after it, first the inverse of the predicted test data is written to the row before it, then the inverse of the preset test data is written to the row after it, and a refresh operation is performed on the entire storage array of the DRAM to be tested;
[0107] S13, reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data;
[0108] Specifically, reading the data of the target row and its adjacent rows and comparing the read data with the corresponding written data includes:
[0109] S131, reading the data of the target row in units of a preset burst length, and comparing the read data with the corresponding written data;
[0110] S132, reading data of adjacent rows of the target row in a preset order in units of a preset burst length, and comparing the read data with the corresponding written data;
[0111] For example, the data of the previous row of the target row is first read in units of a preset burst length, and the read data is compared with the corresponding written data, and then the data of the next row of the target row is read, and the read data is compared with the corresponding written data;
[0112] S14, writing the preset test data to adjacent rows of the compared target row in a preset order in units of a preset burst length;
[0113] For example, the preset test data is first written to the previous row of the compared target row in units of the preset burst length, and then the preset test data is written to the next row of the compared target row;
[0114] After the first round of testing is completed, the second round of testing is performed, and the preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0115] S2. Obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result;
[0116] If the first comparison result and the second comparison result are both consistent, the test result is success; otherwise, the test result is failure.
[0117] In this embodiment, the specific reference Figure 4-9 First, the first round of testing is performed on the DRAM to be tested:
[0118] like Figure 4 As shown, the test data to be written is defined as D=01010101...0101, and its inverse is / D=10101010...1010. Assuming that the preset burst length is BL=8 bits, then D=01010101, / D=10101010;
[0119] First, the address located is row 0, column 0, and the test data D is written from the storage unit corresponding to row 0, column 0 according to BL. After writing row 0, the test data D is written from row 1, column 0, and so on, until the entire storage array is written with data, such as Figure 5 As shown;
[0120] Secondly, the storage array is traversed starting from row 0 until all rows of the entire storage array are traversed. For the target row (i.e. Figure 6 Base Line in the target line), press BL to go to the line before the target line (i.e. Figure 6 Front Line in the target line) write / D, and then write to the line after the target line (i.e. Figure 6 Rear Line) in write / D, such as Figure 6 As shown;
[0121] Next, a REF (refresh) operation is performed on the entire storage array, such as Figure 7 As shown;
[0122] If there is no previous row or next row of the target row, the data writing of the previous row or next row is omitted. For example, if row 0 is the target row, and there is no previous row but only next row of the target row, the data writing of the previous row is omitted and the data is written to the next row.
[0123] Then press BL to read the data of the target row, and compare the read data with D to check whether there is any error; press BL to read the data of the row before the target row, and compare the read data with / D to check whether there is any error, and then read the data of the row after the target row, and compare the read data with / D to check whether there is any error, such as Figure 8 As shown;
[0124] Then, press BL to write D to the row before the target row, and then write D to the row after the target row, such as Fig. 9 As shown;
[0125] Obtaining a first comparison result;
[0126] In the second round of testing, the test data written is defined as / D = 10101010, and its inverse D = 01010101:
[0127] First, the address located is row 0, column 0, and the test data / D is written from the storage cell corresponding to row 0, column 0 according to BL. After writing row 0, the test data / D is written from row 1, column 0, and so on, until the entire storage array is written with data;
[0128] Secondly, the storage array is traversed starting from row 0 until all rows of the entire storage array are traversed. For the target row traversed, D is first written to the row before the target row according to BL, and then D is written to the row after the target row.
[0129] Next, a REF operation is performed on the entire storage array;
[0130] Then press BL to read the data of the target row, and compare the read data with / D to check whether there is any error; press BL to first read the data of the row before the target row, and compare the read data with D to check whether there is any error, and then read the data of the row after the target row, and compare the read data with D to check whether there is any error;
[0131] Then, press BL to write / D to the row before the target row, and then write / D to the row after the target row;
[0132] obtaining a second comparison result;
[0133] If the first comparison result and the second comparison result are both consistent, the test result is successful; otherwise, the test result is failed.
[0134] Embodiment 2
[0135] The difference between the second embodiment and the first embodiment is that the first preset unit is a column, and the preset order is to first perform a read and write operation on a row after the target row, and then perform a read and write operation on a row before the target row;
[0136] Specifically, the located address is the 0th column and the 0th row, and the test data D is written from the storage unit corresponding to the 0th column and the 0th row according to BL, that is, the test data D is written from the 0th column and the 0th row to the 7th column and the 0th row. After writing, the test data D is written from the 0th column and the 1st row. After writing all the rows from the 0th column to the 7th column, all the rows from the 8th column to the 15th column are written in the order of the rows, and so on, until the entire storage array is written with data;
[0137] Secondly, the storage array is traversed starting from row 0 until all rows of the entire storage array are traversed. For the target row traversed, / D is first written to the row after the target row according to BL, and then / D is written to the row before the target row;
[0138] Next, a REF (refresh) operation is performed on the entire storage array;
[0139] Then press BL to read the data of the target row, and compare the read data with D to check whether there is any error; press BL to first read the data of the row after the target row, and compare the read data with / D to check whether there is any error, and then read the data of the row before the target row, and compare the read data with / D to check whether there is any error;
[0140] Then, press BL to write D to the row after the target row, and then write D to the row before the target row;
[0141] Obtaining a first comparison result;
[0142] In the second round of testing, the test data written is defined as / D = 10101010, and its inverse D = 01010101:
[0143] First, the address located is row 0, column 0, and the test data / D is written from the storage cell corresponding to row 0, column 0 according to BL. After writing row 0, the test data / D is written from row 1, column 0, and so on, until the entire storage array is written with data;
[0144] Secondly, the storage array is traversed starting from row 0 until all rows of the entire storage array are traversed. For the target row traversed, D is first written to the row after the target row according to BL, and then D is written to the row before the target row.
[0145] Next, a REF operation is performed on the entire storage array;
[0146] Then press BL to read the data of the target row, and compare the read data with / D to check whether there is any error; press BL to first read the data of the row after the target row, and compare the read data with D to check whether there is any error, and then read the data of the row before the target row, and compare the read data with D to check whether there is any error;
[0147] Then, press BL to write / D to the row after the target row, and then write / D to the row before the target row;
[0148] obtaining a second comparison result;
[0149] If the first comparison result and the second comparison result are both consistent, the test result is successful; otherwise, the test result is failed.
[0150] Embodiment 3
[0151] Please refer to Figure 2 , a DRAM testing device, comprising:
[0152] A data reading and writing module is used to perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively;
[0153] The tests include:
[0154] Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data;
[0155] Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed;
[0156] For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested;
[0157] Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data;
[0158] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0159] A testing module is used to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0160] Embodiment 4
[0161] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, each step of the DRAM testing method in the first embodiment or the second embodiment can be implemented.
[0162] Embodiment 5
[0163] Please refer to Figure 3 , an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the DRAM testing method in Embodiment 1 or Embodiment 2 when executing the computer program.
[0164] In summary, the DRAM detection method, device, readable storage medium and electronic device provided by the present invention perform two rounds of tests on the DRAM to be tested. In the process of writing preset test data to the DRAM to be tested and writing data to the target row and adjacent rows, the writing is performed in units of preset burst length, which can improve the data writing speed and has low time complexity, which is convenient for mass production testing. The reverse of the preset test data is written to the previous row and the next row of the target row, resulting in a large span of potential difference between the target row and the adjacent rows, making it easier to stimulate multiple storage unit faults. In the process of reading and writing data to the target row and its adjacent rows, Read and write operations are performed on adjacent rows in a preset order. The preset order includes first performing read and write operations on the previous row and then performing read and write operations on the next row, or first performing read and write operations on the next row and then performing read and write operations on the previous row. This improves the flexibility of the test, and writes preset test data to the compared adjacent rows to stimulate a single storage unit. By alternately accessing the rows of the DRAM to be tested, the previous test blind areas are covered and chip defects that are difficult to be found in existing technologies are detected, so that multiple storage unit faults such as bridging faults and coupling faults are stimulated, thereby improving fault coverage and enhancing the reliability of test results, thereby improving product quality.
[0165] In the above embodiments provided in the present application, it should be understood that the disclosed methods, devices, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple components or modules can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or components or modules, which can be electrical, mechanical or other forms.
[0166] The components described as separate components may or may not be physically separated, and the components shown as components may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0167] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each component may exist physically separately, or two or more modules may be integrated into one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.
[0168] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.
[0169] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.
[0170] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0171] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A DRAM testing method, characterized in that: Includes steps: Perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively; The tests include: Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data; Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed; For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested; Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data; The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing; Obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result; Writing the inverse of the preset test data into a row adjacent to the target row comprises: Writing the inverse of the preset test data to the row before and after the target row in a preset order in units of a preset burst length, and omitting the writing of data of the row before or after if there is no row before or after the target row; The step of reading the data of the target row and its adjacent rows and comparing the read data with the corresponding written data comprises: Reading the data of the target row in units of a preset burst length, and comparing the read data with the corresponding written data; The data of the adjacent rows of the target row are read in a preset order with a preset burst length as a unit, and the read data are compared with the corresponding written data.
2. A DRAM testing method according to claim 1, characterized in that: Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data includes: The preset test data is written starting from the low-order address of each first preset read / write unit of the DRAM to be tested in units of a preset burst length until all storage units of the DRAM to be tested are written with data.
3. A DRAM testing method according to claim 1, characterized in that: The step of comparing the read data with the corresponding written data includes: The preset test data is written into adjacent rows of the compared target row in a preset order in units of a preset burst length.
4. A DRAM testing method according to claim 1 or 3, characterized in that: The preset sequence includes: Firstly, read and write the row before the target row, and then read and write the row after the target row; Or, the read and write operations are performed on the row following the target row first, and then the read and write operations are performed on the row preceding the target row.
5. A DRAM testing method according to any one of claims 1 to 3, characterized in that: The step of obtaining the test result of the DRAM to be tested according to the first comparison result and the second comparison result includes: If the first comparison result and the second comparison result are both consistent, the test result is success; otherwise, the test result is failure.
6. A DRAM testing device, characterized in that: include: A data reading and writing module is used to perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively; The tests include: Writing preset test data to the DRAM to be tested until all storage cells of the DRAM to be tested are written with data; Traversing the DRAM to be tested in units of rows until all rows of the DRAM to be tested are traversed; For the traversed target row, write the inverse of the preset test data to the row adjacent to the target row, and perform a refresh operation on the entire storage array of the DRAM to be tested; Reading data of the target row and its adjacent rows, and comparing the read data with the corresponding written data; The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing; A testing module, configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result; Writing the inverse of the preset test data into a row adjacent to the target row comprises: Writing the inverse of the preset test data to the row before and after the target row in a preset order in units of a preset burst length, and omitting the writing of data of the row before or after if there is no row before or after the target row; The step of reading the data of the target row and its adjacent rows and comparing the read data with the corresponding written data comprises: Reading the data of the target row in units of a preset burst length, and comparing the read data with the corresponding written data; The data of the adjacent rows of the target row are read in a preset order with a preset burst length as a unit, and the read data are compared with the corresponding written data.
7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step in a DRAM testing method as claimed in any one of claims 1 to 5 is implemented.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, each step in the DRAM testing method according to any one of claims 1 to 5 is implemented.