SiC MOSFET drive circuit and control method thereof

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving circuit and a control method thereof, the SiC MOSFET driving circuit comprises an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source inter-electrode voltage overshoot detection circuit, an analog-to-digital conversion module and an FPGA (Field Programmable Gate Array) module, and a self-adaptive adjustment algorithm is built in the FPGA module. The load current detection circuit and the drain-source inter-electrode voltage overshoot detection circuit have low requirements for real-time performance, use of high-speed simulation devices is avoided, hardware design cost is reduced, a self-adaptive adjustment algorithm can adjust SiC MOSFET gate drive parameters in real time according to output of the load current detection circuit and the drain-source inter-electrode voltage overshoot detection circuit, and the self-adaptive adjustment algorithm can adjust the gate drive parameters of the SiC MOSFET in real time according to the output of the drain-source inter-electrode voltage overshoot detection circuit. Therefore, overshoot and switching loss are self-adaptively balanced, and safe operation of the SiC MOSFET is ensured. The technical problems that a SiC MOSFET driving circuit driven by an active grid is high in hardware cost and is difficult to balance voltage and current overshoot and switching loss are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor switch circuits, and in particular to a SiC MOSFET drive circuit and a control method thereof. Background Art

[0002] As a substitute for traditional silicon-based devices, silicon carbide metal oxide semiconductor field effect transistor (SiCMOSFET) has the advantages of faster switching speed, lower conduction loss and higher blocking voltage, and is expected to significantly improve the efficiency and power density of power conversion devices. Gate drive directly affects the operating state of switching devices. Good gate drive can not only provide strong guarantee for the safe operation of switching devices, but also effectively reduce the switching loss and electromagnetic interference generated by the devices, and effectively improve the performance of power conversion devices. The typical gate drive working principle is: using the voltage source and gate resistance to the input capacitance of SiC MOSFET The SiC MOSFET is charged and discharged to realize the on and off control of the switching device. Due to the presence of parasitic capacitance and stray inductance, SiC MOSFET will have obvious current overshoot and overvoltage during the on and off process. Once the overshoot current and overshoot voltage exceed the safe operating area (SOA) of SiC MOSFET, that is, the current threshold and voltage threshold, SiC MOSFET will age, and in severe cases, it will cause irreversible damage to the switching device, thus posing a serious threat to the entire circuit system.

[0003] Conventional gate drivers (CGD) use fixed gate resistors to drive switching devices. Therefore, to suppress voltage and current overshoot, CGD can only replace smaller gate resistors with larger resistors. This method will lead to longer switching delays, slower switching speeds, and larger switching losses. In order to better balance overshoot and loss, active gate drivers (AGD) came into being. The current source driver composed of an inductor requires more than two control switches and multiple control signals to accurately control the inductor pre-charging process. Although the current source driver composed of a current mirror has a simpler control process, it requires more control switches and a more complex circuit structure. In order to achieve accurate closed-loop control in a very short switching phase, the switch state detection circuit and feedback circuit need to use high-bandwidth analog devices and analog-to-digital conversion chips, which greatly increases the manufacturing cost of active gate drivers. In applications where the DC bus voltage or load current varies greatly over time, such as wind power generation, the voltage and current overshoot of the switching device will be different in each switching cycle. If the overshoot of both is far below the threshold of SOA at lower voltage or current, the fixed control parameters of AGD used to suppress voltage or current overshoot will cause unnecessary switching loss. Therefore, for SiCMOSFET drive circuits with active gate drive, how to avoid using high-speed analog devices, reduce hardware costs, and balance voltage and current overshoot and switching loss are technical problems that need to be solved urgently by technicians in this field. Summary of the invention

[0004] The present invention provides a SiC MOSFET drive circuit and a control method thereof, which are used to solve the technical problems of high hardware cost and difficulty in balancing voltage and current overshoot and switching loss in an active gate driven SiC MOSFET drive circuit.

[0005] In view of this, a first aspect of the present invention provides a SiC MOSFET drive circuit, comprising an active current source drive circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-to-digital conversion module, and an FPGA module;

[0006] The output of the active current source drive circuit is connected to the gate of the SiC MOSFET;

[0007] The load current detection circuit is connected to the SiC MOSFET, and is used to detect the drain-source current flowing through the SiC MOSFET, and output a voltage signal corresponding to the drain-source current of the SiC MOSFET;

[0008] The drain-source voltage overshoot detection circuit is connected to the SiC MOSFET and is used to detect the drain-source overshoot voltage of the SiC MOSFET;

[0009] The input end of the analog-to-digital conversion module is connected to the output end of the load current detection circuit and the drain-source voltage overshoot detection circuit respectively, and the output end of the analog-to-digital conversion module is connected to the input end of the FPGA module;

[0010] The FPGA module has a built-in PWM unit and a digital controller, the output end of the PWM unit is connected to the PWM signal input end of the active current source drive circuit, the PWM unit is used to generate a PWM signal for controlling the active current source drive circuit to be turned on or off and to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal, and the digital controller has a built-in adaptive adjustment algorithm, and the adaptive adjustment algorithm is used to control the gate current output of the active current source drive circuit to the SiC MOSFET according to the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit.

[0011] Optionally, the active current source driving circuit includes a voltage source, a PNP transistor, an NPN transistor, an adjustable on-resistance and an adjustable off-resistance;

[0012] The emitter of the PNP transistor is connected in parallel with the emitter of the NPN transistor, and the collector of the PNP transistor is connected in parallel with the collector of the NPN transistor;

[0013] The positive electrode of the voltage source is connected to the emitter connection terminals of the PNP transistor and the NPN transistor, and the negative electrode of the voltage source is connected to the Kelvin source of the SiC MOSFET;

[0014] The collector connection ends of the PNP transistor and the NPN transistor are connected to the gate of the SiC MOSFET;

[0015] The base of the PNP transistor is connected to one end of the adjustable on-resistance, the base of the NPN transistor is connected to one end of the adjustable off-resistance, and the other end of the adjustable on-resistance and the other end of the adjustable off-resistance are connected and commonly connected to the Kelvin source of the SiC MOSFET.

[0016] Optionally, the adjustable on-resistance includes a plurality of on-resistors with different resistance values ​​connected in parallel, each of the on-resistors is connected in series with a first analog switch, one end of all the on-resistors is connected in common, and one end of all the first analog switches is connected in common.

[0017] Optionally, the adjustable off-resistance includes a plurality of off-resistances with different resistances connected in parallel, each of the off-resistances is connected in series with a second analog switch, one end of all the off-resistances is connected in common, and one end of all the second analog switches is connected in common.

[0018] Optionally, the adaptive adjustment algorithm is specifically used for:

[0019] Comparing the output of the drain-source voltage overshoot detection circuit with the overshoot voltage lower limit, if the output of the drain-source voltage overshoot detection circuit is less than the overshoot voltage lower limit, adjusting the gate current of the SiC MOSFET by reducing the adjustable turn-off resistor, if the output of the drain-source voltage overshoot detection circuit is greater than the overshoot voltage lower limit but less than the overshoot voltage upper limit, not adjusting the adjustable turn-off resistor, if the output of the drain-source voltage overshoot detection circuit is greater than the overshoot voltage upper limit, adjusting the gate current of the SiC MOSFET by increasing the adjustable turn-off resistor;

[0020] The load current output by the load current detection circuit is divided into a plurality of current intervals, each current interval corresponds to a resistance value, and according to the current interval into which the load current output by the load current detection circuit falls, the resistance value of the adjustable on-resistance is adjusted to the resistance value corresponding to the current interval into which the load current output by the load current detection circuit falls.

[0021] Optionally, the drain-source voltage overshoot detection circuit includes an overshoot detection circuit and a subtraction circuit;

[0022] The overshoot detection circuit includes a diode, a capacitor, a reset switch and a current limiting resistor, wherein the anode of the diode is connected to the drain of the SiC MOSFET, the cathode of the diode is connected to one end of the capacitor, the other end of the capacitor is connected to the source of the SiC MOSFET, one end of the reset switch is connected to the cathode of the diode, the other end of the reset switch is connected to one end of the current limiting resistor, and the other end of the current limiting resistor is connected to the DC bus;

[0023] The subtraction circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor and an operational amplifier, one end of the first resistor is connected to the cathode of the diode, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier, one end of the second resistor is connected to the non-inverting input terminal of the operational amplifier, the other end of the second resistor is grounded, one end of the third resistor is connected to the anode of the diode, the other end of the third resistor is connected to the inverting input terminal of the operational amplifier, one end of the fourth resistor is connected to the inverting input terminal of the operational amplifier, and the other end of the fourth resistor is connected to the output terminal of the operational amplifier.

[0024] Optionally, the load current detection circuit is a Hall current sensor.

[0025] Optionally, the PWM unit generates a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit when the PWM signal is converted from a low level to a high level;

[0026] Optionally, the analog-to-digital conversion module includes a first ADC chip and a second ADC chip;

[0027] The input end of the first ADC chip is connected to the output end of the drain-source voltage overshoot detection circuit, and the output end of the first ADC chip is connected to the first input end of the digital controller;

[0028] The input end of the second ADC chip is connected to the output end of the load current detection circuit, and the output end of the second ADC chip is connected to the second input end of the digital controller.

[0029] Optionally, when the PNP transistor is turned on, the current output by the active current source driving circuit is:

[0030]

[0031] in, is the output current of the active current source driving circuit, is the current gain of the PNP transistor, is the output voltage of the voltage source, is the voltage drop between the base and emitter of the PNP transistor, is the adjustable on-resistance.

[0032] Optionally, when the NPN transistor is turned on, the current output by the active current source driving circuit is:

[0033]

[0034] in, is the output current of the active current source driving circuit, is the current gain of the NPN transistor, is the output voltage of the voltage source, is the voltage drop between the base and emitter of the NPN transistor, is the adjustable off resistance.

[0035] A second aspect of the present invention provides a control method for a SiC MOSFET drive circuit according to any one of the first aspects of the present invention, comprising:

[0036] The FPGA module generates a PWM signal for controlling the active current source drive circuit to be turned on or off;

[0037] The FPGA module obtains the output of the load current detection circuit or the output of the drain-source voltage overshoot detection circuit;

[0038] The FPGA module controls the gate current output by the active current source driving circuit to the SiC MOSFET according to the load current output by the load current detection circuit or the overshoot voltage output by the drain-source voltage overshoot detection circuit;

[0039] The FPGA module determines whether to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit based on the PWM signal. If so, it generates a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit and sends the reset signal to the drain-source voltage overshoot detection circuit.

[0040] It can be seen from the above technical solutions that the SiC MOSFET driving circuit provided by the present invention has the following advantages:

[0041] The SiC MOSFET driving circuit provided by the present invention comprises an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-to-digital conversion module and an FPGA module, wherein the FPGA module has a built-in adaptive adjustment algorithm. The load current detection circuit and the drain-source voltage overshoot detection circuit have low real-time requirements, avoid the use of high-speed analog devices, and reduce the hardware design cost. The adaptive adjustment algorithm can adjust the SiC MOSFET gate drive parameters in real time according to the output of the load current detection circuit and the drain-source voltage overshoot detection circuit, thereby adaptively balancing overshoot and switching loss, and ensuring the safe operation of the SiC MOSFET. The technical problems of high hardware cost and difficulty in balancing voltage and current overshoot and switching loss of the SiC MOSFET driving circuit with active gate drive are solved.

[0042] At the same time, the SiC MOSFET driving circuit provided by the present invention utilizes a voltage source and a current source driving composed of a parallel transistor formed by connecting a PNP transistor and an NPN transistor in parallel. The structure and control method are relatively simple, and the generated gate current is more constant. The SiC MOSFET can be quickly turned on and off, and the overshoot and switching loss can be better balanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic diagram of the structure of a SiC MOSFET driving circuit provided in an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of an active current source driving circuit provided in an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a drain-source voltage overshoot detection circuit provided in an embodiment of the present invention;

[0047] Figure 4 It is a working waveform diagram of the drain-source voltage overshoot detection circuit provided in an embodiment of the present invention;

[0048] Figure 5 The voltage and current waveform diagram of the SiC MOSFET under the control of the quasi-closed-loop active gate drive circuit provided in the embodiment of the present invention;

[0049] Figure 6 The current waveform diagram of the SiC MOSFET at the turn-on stage under different on-resistance values ​​provided in the embodiment of the present invention;

[0050] Figure 7 The voltage waveform diagram of the SiC MOSFET turn-off stage under different turn-off resistance values ​​provided in the embodiment of the present invention;

[0051] Figure 8 The present invention provides a flow chart of a control method of a SiC MOSFET driving circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] For easier understanding, see Figure 1, the present invention provides an embodiment of a SiC MOSFET driving circuit, comprising an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-to-digital conversion module, and an FPGA module;

[0054] The output of the active current source driving circuit is connected to the gate of the SiC MOSFET;

[0055] The load current detection circuit is connected to the SiC MOSFET, and is used to detect the drain-source current flowing through the SiC MOSFET, and output a voltage signal corresponding to the drain-source current of the SiC MOSFET;

[0056] The input end of the analog-to-digital conversion module is connected to the output end of the load current detection circuit and the drain-source voltage overshoot detection circuit respectively, and the output end of the analog-to-digital conversion module is connected to the input end of the FPGA module;

[0057] The FPGA module has a built-in PWM unit and a digital controller. The output end of the PWM unit is connected to the PWM signal input end of the active current source drive circuit. The PWM unit is used to generate a PWM signal for controlling the active current source drive circuit to be turned on or off and to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal. The digital controller has a built-in adaptive adjustment algorithm. The adaptive adjustment algorithm is used to control the output of the active current source drive circuit to the gate current size of the SiC MOSFET according to the output of the load current detection circuit and the drain-source voltage overshoot detection circuit.

[0058] It should be noted that Figure 1 In the figure, G is the gate of MOSFET, D is the drain of MOSFET, and S is the source of MOSFET. is the parasitic capacitance between the gate G and drain D of the MOSFET, is the parasitic capacitance between the drain D and source S of the MOSFET, is the parasitic capacitance between the gate G and source S of the MOSFET, s is the Kelvin source of the MOSFET, The output of the active current source drive circuit is connected to the gate G of the SiC MOSFET, and the output of the active current source drive circuit provides a gate current for the SiC MOSFET. . Drain-source voltage ( ) The overshoot detection circuit detects the overshoot voltage between the drain D and source S of the switching device MOSFET And output to the field programmable gate array (FPGA) module, the load current ( ) The detection circuit detects the load current of the SiC MOSFET, that is, the current flowing through the drain and source of the SiC MOSFET, and converts it into a voltage signal for output. Before the output of the drain-source voltage overshoot detection circuit and the load current detection circuit enters the FPGA module, it is first converted into an analog-to-digital conversion module, and then input into the digital controller of the FPGA module. Specifically, the analog-to-digital conversion module includes a first ADC chip and a second ADC chip, the input end of the first ADC chip is connected to the output end of the drain-source voltage overshoot detection circuit, the output end of the first ADC chip is connected to the first input end of the digital controller, the input end of the second ADC chip is connected to the output end of the load current detection circuit, and the output end of the second ADC chip is connected to the second input end of the digital controller. The digital controller has a built-in adaptive adjustment algorithm for controlling the gate current of the MOSFET. The adaptive adjustment algorithm controls the output of the active current source drive circuit to the gate current of the SiC MOSFET according to the output of the load current detection circuit and the drain-source voltage overshoot detection circuit. The PWM unit inside the FPGA module controls the active current source drive circuit to turn on or off by outputting a PWM signal to the active current source drive circuit, and generates a reset signal to reset the drain-source voltage overshoot detection circuit according to the PWM signal. The adaptive adjustment algorithm can adjust the gate current in real time according to different working conditions. When the SiC MOSFET operates in the safe operating area (SOA), the gate current can be appropriately increased to reduce switching losses. When the SiC MOSFET operates at the SOA boundary, the gate drive current is reduced to reduce overshoot and ensure the safe operation of the SiC MOSFET.

[0059] In one embodiment, Figure 2 As shown, the active current source driving circuit includes a voltage source 、PNP transistor 、NPN transistor and base resistors, which include adjustable on-resistance and adjustable off resistance , PNP Transistor emitter and NPN transistor The emitters of the PNP transistor are connected in parallel. The collector and NPN transistor The collectors are connected in parallel, the voltage source The positive electrode of the PNP transistor and NPN transistor The emitter connection terminal is connected to a voltage source The cathode of the PNP transistor is connected to the Kelvin source of the SiC MOSFET. and NPN transistor The collector connection terminal is connected to the gate of SiC MOSFET, and the PNP transistor The base and adjustable on-resistance The base of the NPN transistor is connected to the adjustable off resistor One end is connected to the adjustable on-resistance The other end and the adjustable off resistor The other end of the voltage source is connected and connected together to the Kelvin source s of the SiC MOSFET. Receives the PWM signal output by the FPGA module and outputs a positive level (+15V) or a negative level (-5V) according to the PWM signal. When the output is positive (+15V), the PNP transistor When it is turned on, the output current is:

[0060]

[0061] in, is the output current of the active current source driving circuit, is the current gain of the PNP transistor, is the output voltage of the voltage source, is the voltage drop between the base and emitter of the PNP transistor, is the adjustable on-resistance.

[0062] Similar to the turn-on process, when the voltage source When the output is negative (-5V), the NPN transistor is turned on and the output current is:

[0063]

[0064] in, is the output current of the active current source driving circuit, is the current gain of the NPN transistor, is the output voltage of the voltage source, is the voltage drop between the base and emitter of the NPN transistor, is the adjustable turn-off resistance. It should be noted that if all parameters remain constant during the switching process, the gate current is clamped to a constant value.

[0065] To achieve active control of gate current, the on-resistance can be adjusted Includes several on-resistors of different resistance values ​​connected in parallel ( ), each on-resistor is connected in series with a first analog switch, and all on-resistors ( ) are connected together, all first analog switches ( ) are connected together. The first analog switch ( ) are controlled by the analog switch control voltage output by the FPGA module ( ) control, when the analog switch control voltage is high, the analog switch is turned on, and the resistor connected to this path will be connected in parallel to the base of the transistor; when the signal of this path is low, the analog switch is turned off, and the resistor connected to this path will be disconnected from the base of the transistor. Adjustable off resistance Includes several off resistors with different resistance values ​​connected in parallel ( ), each turn-off resistor is connected in series with a second analog switch, and all turn-off resistors ( ) are connected together, all second analog switches ( ) are connected together. The second analog switch ( ) are controlled by the analog switch control voltage output by the FPGA module ( ), when the analog switch control voltage is high, the analog switch is turned on, and the resistor connected to the analog switch will be connected in parallel to the base of the transistor; when the signal is low, the analog switch is turned off, and the resistor connected to the analog switch will be disconnected from the base of the transistor. The calculation formula shows that the current amplitude of the transistor output will change. Therefore, the FPGA module is used to adjust the on-resistance and adjustable off resistance Active adjustment can be made to the gate current Active control.

[0066] In one embodiment, to achieve quasi-closed-loop control, the load current Detection circuit and drain-source voltage ( ) The overshoot detection circuit detects the working condition of SiC MOSFET in real time. The current overshoot peak value generated in the turn-on stage is directly related to the amplitude of the load current, that is, the greater the current flowing through the SiC MOSFET, the greater the corresponding current overshoot. Therefore, the current detection circuit used in the present invention detects the load current after the SiC MOSFET is fully turned on. Rather than the high-frequency current in the switching phase. Since only the low-frequency load current needs to be detected , the Hall current sensor can complete its detection. The Hall current sensor is connected to the drain D of the SiC MOSFET; when the load current The Hall current sensor detects the current signal Generating voltage signals , the voltage signal Sent to the FPGA module.

[0067] In one embodiment, Figure 3As shown, in the present invention, the drain-source voltage overshoot detection circuit includes an overshoot detection circuit and a subtraction circuit, and the overshoot detection circuit includes a diode ,capacitance , reset switch and current limiting resistor ,diode The anode of the diode is connected to the drain D of the SiC MOSFET. The cathode and capacitor One end of the capacitor is connected The other end of the reset switch is connected to the source S of the SiC MOSFET. One end of the diode Cathode connection of the reset switch The other end of the current limiting resistor Connect one end of the current limiting resistor The other end of the DC bus connected, the subtraction circuit includes a first resistor , the second resistor , the third resistor , the fourth resistor and operational amplifiers , the first resistor One end of the diode The cathode connection of the first resistor The other end of the operational amplifier The non-inverting input terminal is connected to the second resistor One end of the operational amplifier The non-inverting input terminal is connected to the second resistor The other end of the third resistor is grounded. One end of the diode The anode connection of the third resistor The other end of the operational amplifier The inverting input terminal is connected to the fourth resistor One end of the operational amplifier The inverting input terminal is connected to the fourth resistor The other end of the operational amplifier The output of the operational amplifier is connected to Output The signal is sent to the digital controller of the FPGA through the analog-to-digital conversion circuit of the FPGA. To ensure that the overshoot detection circuit can operate normally, the reset switch needs to be turned on. On, DC bus voltage Through the current limiting resistor Capacitance Charge until the capacitor The voltage at both ends reaches the DC bus voltage After that, reset the switch Shut down. Figure 4 As shown in Figure 1, when the PWM signal changes from high level to low level, the SiC MOSFET is turned off. Rapid rise and overshoot. Exceed When the diode On-state capacitance Charging, Capacitor Voltage across both ends Rising until the overshoot peak Since the diode Only one-way conduction, diode will be clamped to After the overshoot and oscillation completely disappear, will be clamped to It is worth noting that in the subtraction circuit, the first resistor , the second resistor , the third resistor and the fourth resistor When the oscillation disappears, and After the subtraction circuit, the output of the subtraction circuit is Subsequently, the result is converted into a digital signal and transmitted to the digital controller of the FPGA. Figure 4 As shown, when the PWM signal is converted from a low level to a high level, the PWM unit generates a reset signal for resetting the drain-source voltage overshoot detection circuit. Sent to the drain-source voltage overshoot detection circuit, reset switch Upon receiving a reset signal After that, reset the switch Turn on and set the capacitor Voltage across both ends Reset to . Operational Amplifier Output for:

[0068]

[0069] The adaptive adjustment algorithm is executed in the FPGA module, and the execution result is output to the adjustable on-resistance and adjustable off resistance , change the adjustable on-resistance and adjustable off resistance The impedance of the current source is adjusted to drive the output current , to achieve active control of SiC MOSFET switching behavior. Figure 5As shown, for the shutdown process, the FPGA module obtains the detected overshoot signal After that, first with the overshoot voltage lower limit Compare, if it is less than the lower voltage limit (i.e. ), the adaptive adjustment algorithm will actively reduce the adjustable off resistance , the FPGA module generates an adjustable off resistance to reduce PWM signal, speed up the shutdown speed; if the detection signal is greater than the lower voltage limit, but less than the upper voltage limit (i.e. ), the adaptive adjustment algorithm will not generate a PWM signal and will not adjust the adjustable off resistance ; If the detection signal is greater than the upper voltage limit (i.e. ), the adaptive adjustment algorithm will generate an increase in the adjustable off resistance PWM signal, increase the adjustable off resistance , reducing overshoot. For the turn-on process, the adaptive adjustment algorithm divides the load current into several current intervals ( ), each interval has a corresponding resistance value; after the FPGA obtains the load current signal, it adjusts the adjustable on-resistance according to the current interval To verify the ability of active gate drive to suppress voltage and current overshoot, the present invention performs simulation verification in LTspice, and the results are as follows: Figure 6 and Figure 7 As shown, with adjustable on-resistance As the resistance value increases, the current overshoot and oscillation are significantly suppressed, and the switching speed is correspondingly reduced; similarly, with the adjustable off resistance With the increase of resistance value, voltage overshoot and oscillation are also significantly suppressed.

[0070] The SiC MOSFET driving circuit provided by the present invention comprises an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit and an FPGA module, wherein the FPGA module has a built-in adaptive adjustment algorithm. The load current detection circuit and the drain-source voltage overshoot detection circuit have low real-time requirements, avoid the use of high-speed analog devices, and reduce the hardware design cost. The adaptive adjustment algorithm can generate corresponding PWM control signals according to the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit, and adjust the SiC MOSFET gate drive parameters in real time, thereby adaptively balancing overshoot and switching loss, and ensuring the safe operation of the SiC MOSFET. The invention solves the technical problems of high hardware cost and difficulty in balancing voltage and current overshoot and switching loss of the SiC MOSFET driving circuit driven by active gate.

[0071] At the same time, the SiC MOSFET driving circuit provided by the present invention utilizes a voltage source and a current source driving composed of a parallel transistor formed by connecting a PNP transistor and an NPN transistor in parallel. The structure and control method are relatively simple, and the generated gate current is more constant. The SiC MOSFET can be quickly turned on and off, and the overshoot and switching loss can be better balanced.

[0072] For easier understanding, see Figure 8 The present invention provides an embodiment of a control method for a SiC MOSFET driving circuit provided in the present invention, comprising:

[0073] Step 101: The FPGA module generates a PWM signal for controlling the active current source driving circuit to be turned on or off.

[0074] It should be noted that the active current source driving circuit is turned on or off by the PWM signal sent by the FPGA module for control.

[0075] Step 102: The FPGA module obtains the output of the load current detection circuit or the output of the drain-source voltage overshoot detection circuit.

[0076] It should be noted that when the SiC MOSFET is turned on, the FPGA module obtains the output of the load current detection circuit. When the SiC MOSFET is turned off, the FPGA module obtains the output of the drain-source voltage overshoot detection circuit.

[0077] Step 103 , the FPGA module controls the gate current output by the active current source driving circuit to the SiC MOSFET according to the load current output by the load current detection circuit or the overshoot voltage output by the drain-source voltage overshoot detection circuit.

[0078] It should be noted that the control process of this step has been described in the SiC MOSFET driving circuit embodiment provided in the present invention, and will not be repeated here.

[0079] Step 104, the FPGA module determines whether to generate a reset signal for resetting the drain-source voltage overshoot detection circuit based on the PWM signal, and if so, generates a reset signal for resetting the drain-source voltage overshoot detection circuit and sends the reset signal to the drain-source voltage overshoot detection circuit.

[0080] It should be noted that step 104 can be performed directly after step 101. In this step, when the PWM signal is converted from a low level to a high level, a reset signal for resetting the drain-source voltage overshoot detection circuit is generated to reset the drain-source voltage overshoot detection circuit.

[0081] The control method of the SiC MOSFET driving circuit provided in the embodiment of the present invention is applied to the SiC MOSFET driving circuit provided in the present invention. The control principle has been described in the embodiment of the SiC MOSFET driving circuit provided in the present invention and will not be repeated here.

[0082] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A SiC MOSFET driving circuit, characterized in that: It includes an active current source drive circuit, SiC MOSFET, load current detection circuit, drain-source voltage overshoot detection circuit, analog-to-digital conversion module and FPGA module; The output of the active current source drive circuit is connected to the gate of the SiC MOSFET; The load current detection circuit is connected to the SiC MOSFET, and is used to detect the drain-source current flowing through the SiC MOSFET, and output a voltage signal corresponding to the drain-source current of the SiC MOSFET; The drain-source voltage overshoot detection circuit is connected to the SiC MOSFET and is used to detect the drain-source overshoot voltage of the SiC MOSFET; The input end of the analog-to-digital conversion module is connected to the output end of the load current detection circuit and the drain-source voltage overshoot detection circuit respectively, and the output end of the analog-to-digital conversion module is connected to the input end of the FPGA module; The FPGA module has a built-in PWM unit and a digital controller, the output end of the PWM unit is connected to the PWM signal input end of the active current source drive circuit, the PWM unit is used to generate a PWM signal for controlling the active current source drive circuit to be turned on or off and to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal, and the digital controller has a built-in adaptive adjustment algorithm, and the adaptive adjustment algorithm is used to control the gate current output of the active current source drive circuit to the SiC MOSFET according to the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit.

2. The SiC MOSFET driving circuit according to claim 1, characterized in that: The active current source driving circuit includes a voltage source, a PNP transistor, an NPN transistor, an adjustable on-resistance and an adjustable off-resistance; The emitter of the PNP transistor is connected in parallel with the emitter of the NPN transistor, and the collector of the PNP transistor is connected in parallel with the collector of the NPN transistor; The positive electrode of the voltage source is connected to the emitter connection terminals of the PNP transistor and the NPN transistor, and the negative electrode of the voltage source is connected to the Kelvin source of the SiC MOSFET; The collector connection ends of the PNP transistor and the NPN transistor are connected to the gate of the SiC MOSFET; The base of the PNP transistor is connected to one end of the adjustable on-resistance, the base of the NPN transistor is connected to one end of the adjustable off-resistance, and the other end of the adjustable on-resistance and the other end of the adjustable off-resistance are connected and commonly connected to the Kelvin source of the SiC MOSFET.

3. The SiC MOSFET driving circuit according to claim 2, characterized in that: The adjustable on-resistance includes a plurality of on-resistances with different resistances connected in parallel, each of the on-resistances is connected in series with a first analog switch, one end of all the on-resistances is connected in common, and one end of all the first analog switches is connected in common.

4. The SiC MOSFET driving circuit according to claim 3, characterized in that: The adjustable turn-off resistor includes a plurality of turn-off resistors with different resistance values ​​connected in parallel, each of the turn-off resistors is connected in series with a second analog switch, one end of all the turn-off resistors is connected in common, and one end of all the second analog switches is connected in common.

5. The SiC MOSFET driving circuit according to claim 4, characterized in that: The adaptive adjustment algorithm is specifically used for: Comparing the output of the drain-source voltage overshoot detection circuit with the overshoot voltage lower limit, if the output of the drain-source voltage overshoot detection circuit is less than the overshoot voltage lower limit, adjusting the gate current of the SiC MOSFET by reducing the adjustable turn-off resistor, if the output of the drain-source voltage overshoot detection circuit is greater than the overshoot voltage lower limit but less than the overshoot voltage upper limit, not adjusting the adjustable turn-off resistor, if the output of the drain-source voltage overshoot detection circuit is greater than the overshoot voltage upper limit, adjusting the gate current of the SiC MOSFET by increasing the adjustable turn-off resistor; The load current output by the load current detection circuit is divided into a plurality of current intervals, each current interval corresponds to a resistance value, and according to the current interval into which the load current output by the load current detection circuit falls, the resistance value of the adjustable on-resistance is adjusted to the resistance value corresponding to the current interval into which the load current output by the load current detection circuit falls.

6. The SiC MOSFET driving circuit according to claim 1, characterized in that: The drain-source voltage overshoot detection circuit comprises an overshoot detection circuit and a subtraction circuit; The overshoot detection circuit includes a diode, a capacitor, a reset switch and a current limiting resistor, wherein the anode of the diode is connected to the drain of the SiC MOSFET, the cathode of the diode is connected to one end of the capacitor, the other end of the capacitor is connected to the source of the SiC MOSFET, one end of the reset switch is connected to the cathode of the diode, the other end of the reset switch is connected to one end of the current limiting resistor, and the other end of the current limiting resistor is connected to the DC bus; The subtraction circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor and an operational amplifier, one end of the first resistor is connected to the cathode of the diode, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier, one end of the second resistor is connected to the non-inverting input terminal of the operational amplifier, the other end of the second resistor is grounded, one end of the third resistor is connected to the anode of the diode, the other end of the third resistor is connected to the inverting input terminal of the operational amplifier, one end of the fourth resistor is connected to the inverting input terminal of the operational amplifier, and the other end of the fourth resistor is connected to the output terminal of the operational amplifier.

7. The SiC MOSFET driving circuit according to claim 1, characterized in that: The load current detection circuit is a Hall current sensor.

8. The SiC MOSFET driving circuit according to claim 1, characterized in that: The PWM unit generates a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit when the PWM signal is converted from a low level to a high level.

9. The SiC MOSFET driving circuit according to claim 1, characterized in that: The analog-to-digital conversion module includes a first ADC chip and a second ADC chip; The input end of the first ADC chip is connected to the output end of the drain-source voltage overshoot detection circuit, and the output end of the first ADC chip is connected to the first input end of the digital controller; The input end of the second ADC chip is connected to the output end of the load current detection circuit, and the output end of the second ADC chip is connected to the second input end of the digital controller.

10. A control method for a SiC MOSFET drive circuit according to any one of claims 1 to 9, characterized in that: include: The FPGA module generates a PWM signal for controlling the active current source drive circuit to be turned on or off; The FPGA module obtains the output of the load current detection circuit or the output of the drain-source voltage overshoot detection circuit; The FPGA module controls the gate current output by the active current source driving circuit to the SiC MOSFET according to the load current output by the load current detection circuit or the overshoot voltage output by the drain-source voltage overshoot detection circuit; The FPGA module determines whether to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit based on the PWM signal. If so, it generates a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit and sends the reset signal to the drain-source voltage overshoot detection circuit.

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