Data weight averaging method based on double-capacitor array and related device

Abstract

The invention discloses a data weight averaging method based on a double-capacitor array and a related device, and belongs to the technical field of modulators, and the method comprises the steps: obtaining an input digital signal of a digital-to-analog converter; splitting an input digital signal into two split digital signals, wherein the absolute value of the difference value of the two split digital signals is not more than 1; and respectively carrying out first-order dynamic element matching on the two split digital signals on the two independent capacitor arrays to obtain two matched capacitor arrays, and completing data weight averaging based on the double capacitor arrays. The method is simple in implementation logic, and meanwhile, the random depth of dynamic element matching can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of modulators, and relates to a data weight averaging method for a Sigma-Delta ADC, and in particular to a data weight averaging method based on a dual capacitor array and a related device. Background Art

[0002] Analog-to-digital converters (ADCs) can convert analog signals into digital signals. They are considered to be the foundation and core components of power Internet of Things, body area networks, etc., and have always been an important research direction. Sigma-delta modulators are an important analog-to-digital converter that samples and quantizes analog signals through sampling and noise shaping techniques.

[0003] Sigma-delta usually uses a first-order dynamic element matching algorithm to reduce the nonlinear output problem caused by capacitor element mismatch. This is because the first-order dynamic element matching technology is simple to implement and has low hardware overhead. However, the first-order dynamic element matching has a small random depth and cannot meet the requirements of high-precision and low-distortion ADCs.

[0004] In order to overcome the limitations of first-order dynamic element matching, researchers have proposed many improvement schemes, such as second-order dynamic element matching methods. However, these methods often bring about a significant increase in circuit complexity while improving the random depth. Therefore, how to use simpler methods to improve the random depth of dynamic element matching methods has become an urgent problem to be solved. Summary of the invention

[0005] The purpose of the present invention is to provide a data weight averaging method and related devices based on a dual capacitor array to overcome the defects of the prior art. The present invention has simple implementation logic and can effectively improve the random depth of dynamic element matching.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme:

[0007] The data weight averaging method based on the dual capacitor array includes the following steps:

[0008] obtaining an input digital signal of a digital-to-analog converter;

[0009] Splitting the input digital signal into two split digital signals, wherein the absolute value of the difference between the two split digital signals does not exceed 1;

[0010] First-order dynamic element matching is performed on two split digital signals on two independent capacitor arrays to obtain two matched capacitor arrays, thereby completing data weight averaging based on dual capacitor arrays.

[0011] Further, the step of obtaining the input digital signal of the digital-to-analog converter is specifically as follows:

[0012] The digital signal D[n] outputted by the quantizer in the nth round is obtained, and the digital signal D[n] is used as the input digital signal of the digital-to-analog converter.

[0013] Further, the input digital signal is split into two split digital signals, and the absolute value of the difference between the two split digital signals does not exceed 1, specifically:

[0014] The input digital signal D[n] is 5 bits, and the input digital signal D[n] is split into two digital signals S1[n] and S2[n], and S1[n] and S2[n] satisfy |S1[n]-S2[n]|<=1. The splitting method includes:

[0015] The input digital signal D[n] is represented as {D[n][4], D[n][3], D[n][2], D[n][1], D[n][0]}, where D[n][x] represents the bit value of the x-th bit of D[n], x∈{0,1,2,3,4};

[0016] Split D[n] into two equal 5-bit digital signals M1[n] and M2[n], represented as {0, D[n][3], D[n][2], D[n][1], D[n][0]};

[0017] Perform a majority vote on the 4 high-order bit values ​​of D[n] {D[n][4], D[n][3], D[n][2], D[n][1]} and output the vote value v[n];

[0018] The final split digital signals S1[n] and S2[n] are generated using the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n].

[0019] Furthermore, the output voting value v[n] is specifically:

[0020] If the number of 1s in the 4 high-order bit values ​​of D[n] exceeds 2, the voting value v[n] = 0;

[0021] If the number of 1s in the 4 high-order bit values ​​of D[n] is less than 2, the voting value v[n] = 1;

[0022] If the number of 1s in the 4 high-order bit values ​​of D[n] is equal to 2, the voting value v[n]=1 or the voting value v[n]=1 is output with equal probability.

[0023] Furthermore, the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n], are used to generate the final split digital signals S1[n] and S2[n], specifically:

[0024] If v[n]=0, then S1[n]=M1[n]+D[n][0], S2[n]=M2[n]+0;

[0025] If v[n]=1, then S1[n]=M1[n]+0, S2[n]=M2[n]+D[n][0].

[0026] Furthermore, the first-order dynamic element matching is performed on the two split digital signals respectively, specifically:

[0027] Convert S1[n] and S2[n] to thermometer codes T1[n] and T2[n];

[0028] Based on the thermometer codes T1[n] and T2[n], and the pointer positions P1[n] and P2[n], the thermometer codes are cyclically shifted to obtain the final output T {shift,1} [n] and T {shift,2} [n], completing first-order dynamic component matching.

[0029] Furthermore, the pointer position is calculated as follows:

[0030] P1[n]=S2[n]+P1[n-1]+16*O {overflow,1} [n];

[0031] P2[n]=S1[n]+P2[n-1]+16*O {overflow,2 [n];

[0032] Among them, O {overflow,1} [n] and O {overflow,2} [n] are all overflow items. When S2[n]+P1[n-1]>=16, O {overflow,1} [n] = -1, otherwise, O {overflow,1} [n]=0; when S1[n]+P2[n-1]>=16, O {overflow,2} [n] = -1, otherwise O {overflow,2} [n]=0.

[0033] The data weight averaging system based on dual capacitor array includes:

[0034] Signal acquisition module: used to obtain the input digital signal of the digital-to-analog converter;

[0035] A signal splitting module: used for splitting an input digital signal into two split digital signals, wherein the absolute value of the difference between the two split digital signals does not exceed 1;

[0036] First-order dynamic element matching module: used to perform first-order dynamic element matching on two split digital signals on two independent capacitor arrays respectively, to obtain two matched capacitor arrays, and to complete data weight averaging based on dual capacitor arrays.

[0037] Further, the step of obtaining the input digital signal of the digital-to-analog converter is specifically as follows:

[0038] The digital signal D[n] outputted by the quantizer in the nth round is obtained, and the digital signal D[n] is used as the input digital signal of the digital-to-analog converter.

[0039] Further, the input digital signal is split into two split digital signals, and the absolute value of the difference between the two split digital signals does not exceed 1, specifically:

[0040] The input digital signal D[n] is 5 bits, and the input digital signal D[n] is split into two digital signals S1[n] and S2[n], and S1[n] and S2[n] satisfy |S1[n]-S2[n]|<=1. The splitting method includes:

[0041] The input digital signal D[n] is represented as {D[n][4], D[n][3], D[n][2], D[n][1], D[n][0]}, where D[n][x] represents the bit value of the x-th bit of D[n], x∈{0,1,2,3,4};

[0042] Split D[n] into two equal 5-bit digital signals M1[n] and M2[n], represented as {0, D[n][3], D[n][2], D[n][1], D[n][0]};

[0043] Perform a majority vote on the 4 high-order bit values ​​of D[n] {D[n][4], D[n][3], D[n][2], D[n][1]} and output the vote value v[n];

[0044] The final split digital signals S1[n] and S2[n] are generated using the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n].

[0045] Furthermore, the output voting value v[n] is specifically:

[0046] If the number of 1s in the 4 high-order bit values ​​of D[n] exceeds 2, the voting value v[n] = 0;

[0047] If the number of 1s in the 4 high-order bit values ​​of D[n] is less than 2, the voting value v[n] = 1;

[0048] If the number of 1s in the 4 high-order bit values ​​of D[n] is equal to 2, the voting value v[n]=1 or the voting value v[n]=1 is output with equal probability.

[0049] Furthermore, the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n], are used to generate the final split digital signals S1[n] and S2[n], specifically:

[0050] If v[n]=0, then S1[n]=M1[n]+D[n][0], S2[n]=M2[n]+0;

[0051] If v[n]=1, then S1[n]=M1[n]+0, S2[n]=M2[n]+D[n][0].

[0052] Furthermore, the first-order dynamic element matching is performed on the two split digital signals respectively, specifically:

[0053] Convert S1[n] and S2[n] to thermometer codes T1[n] and T2[n];

[0054] Based on the thermometer codes T1[n] and T2[n], and the pointer positions P1[n] and P2[n], the thermometer codes are cyclically shifted to obtain the final output T {shift,1} [n] and T {shift,2} [n], completing first-order dynamic component matching.

[0055] Furthermore, the pointer position is calculated as follows:

[0056] P1[n]=S2[n]+P1[n-1]+16*O {overflow,1} [n];

[0057] P2[n]=S1[n]+P2[n-1]+16*O {overflow,2 [n];

[0058] Among them, O {overflow,1} [n] and O {overflow,2} [n] are all overflow items. When S2[n]+P1[n-1]>=16, O {overflow,1} [n] = -1, otherwise, O {overflow,1} [n]=0; when S1[n]+P2[n-1]>=16, O {overflow,2} [n] = -1, otherwise O {overflow,2} [n]=0.

[0059] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the data weight averaging method based on a dual capacitor array when executing the computer program.

[0060] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data weight averaging method based on a dual capacitor array are implemented.

[0061] Compared with the prior art, the present invention has the following beneficial technical effects:

[0062] The present invention splits the input digital signal of the Sigma-delta ADC to obtain two smaller split digital signals, and the absolute value of the difference between the two split digital signals does not exceed 1. Then, the two smaller split digital signals are respectively subjected to first-order dynamic element matching, and when the two digital signals are respectively subjected to first-order dynamic element matching, the position of the pointer is calculated based on another digital signal. The method is simple to implement, and can effectively improve the random depth of dynamic element matching and the conversion performance of the Sigma-delta ADC.

[0063] Furthermore, the present invention realizes logic simplicity by designing a split implementation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0065] Figure 1 It is a schematic diagram of the splitting of the input digital signal;

[0066] Figure 2 The invention relates to a majority voting circuit;

[0067] Figure 3 The invention relates to a split value lowest bit selection signal generating circuit;

[0068] Figure 4 It is a flow chart of a data weight averaging method based on a dual capacitor array of the present invention;

[0069] Figure 5 It is a structural schematic diagram of a data weight averaging system based on a dual capacitor array of the present invention. DETAILED DESCRIPTION

[0070] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0071] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0072] Embodiment 1

[0073] like Figure 4 As shown, the present invention provides a data weight averaging method based on a dual capacitor array, comprising the following steps:

[0074] obtaining an input digital signal of a digital-to-analog converter;

[0075] Splitting the input digital signal into two split digital signals, wherein the absolute value of the difference between the two split digital signals does not exceed 1;

[0076] First-order dynamic element matching is performed on two separate capacitor arrays for the two split digital signals to obtain two matched capacitor arrays, thereby completing the data weight averaging based on the dual capacitor arrays.

[0077] The present invention splits the input digital signal of the Sigma-delta ADC to obtain two smaller split digital signals, and performs first-order dynamic element matching on the two smaller split digital signals respectively. The method is simple to implement and can effectively improve the random depth of dynamic element matching and the conversion performance of the Sigma-delta ADC.

[0078] Embodiment 2

[0079] The present invention provides a data weight averaging method based on a dual capacitor array, which splits an input digital signal D[n] of a Sigma-delta ADC into two smaller split digital signals S1[n] and S2[n], the absolute value of the difference between which does not exceed 1; further, first-order dynamic element matching is performed on the two smaller split digital signals respectively.

[0080] Specifically:

[0081] 1. Obtain the digital signal D[n] output by the quantizer in the nth round, and use the digital signal D[n] as the input digital signal of the digital-to-analog converter;

[0082] 2. Split the input digital signal D[n] into two split digital signals S1[n] and S2[n], and S1[n] and S2[n] satisfy |S1[n]-S2[n]|<=1. The splitting process of D[n] is as follows: Figure 1 As shown in FIG. 1 , the splitting method is specifically as follows:

[0083] (1) The 5-bit digital signal D[n] is represented as {D[n][4], D[n][3], D[n][2], D[n][1], D[n][0]}, where D[n][x] (x∈{0,1,2,3,4}) represents the bit value of the x-th bit of D[n]. D[n] is first split into two equal 5-bit digital signals M1[n] and M2[n], represented as {0, D[n][3], D[n][2], D[n][1], D[n][0]}.

[0084] (2) Based on the majority voting concept, a majority vote is performed on the four high-order bit values ​​of D[n] {D[n][4], D[n][3], D[n][2], D[n][1]}, as follows: Figure 2 As shown, the voting value v[n] is output so that if the number of 1s in the 4 high-order bit values ​​of D[n] exceeds 2, 1 is output, if it is less than 2, 0 is output, and if it is equal to 2, 1 and 0 are output with equal probability. The specific output logic is v[n] = (D[n][2]D[n][1])'+(D[n][4]D[n][3])'+(D[n][4]D[n][2])', where ()' represents the negation operation in the logical operation, and + represents the or operation in the logical operation.

[0085] (3) Using the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n], the final split digital signals S1[n] and S2[n] are generated. The specific implementation process is: if v[n] = 0, then S1[n] = M1[n] + D[n][0], S2[n] = M2[n] + 0; if v[n] = 1, then S1[n] = M1[n] + 0, S2[n] = M2[n] + D[n][0]. That is to say, let the split value lowest bit select signal R1[n] and R2[n], satisfy R1[n]=(v[n])'∪D[n][0], R2[n]=v[n]∪D[n][0], then S1[n]=M1[n]+R1[n], S2[n]=M2[n]+R2[n], that is, satisfy Figure 3 The logic shown.

[0086] 3. Convert S1[n] and S2[n] to thermometer codes T1[n] and T2[n];

[0087] 4 Based on the thermometer codes T1[n] and T2[n], and the pointer positions P1[n] and P2[n], the thermometer codes are cyclically shifted to obtain the final output T {shift,1} [n] and T {shift,2} [n].

[0088] The pointer position is calculated as P1[n]=S2[n]+P1[n-1]+16*O {overflow,1} [n];P2[n]=S1[n]+P2[n-1]+16*O {overflow,2 [n] where O {overflow,1} [n] and O {overflow,2} [n] are all overflow items. When S2[n]+P1[n-1]>=16, O {overflow,1} [n] = -1, otherwise, O {overflow,1} [n]=0; when S1[n]+P2[n-1]>=16, O {overflow,2} [n] = -1, otherwise O {overflow,2} [n] = 0. P1[n-1] and P2[n-1] represent the pointer positions of the previous round.

[0089] Based on two capacitor arrays, through two cyclic shifted T {shift,1} [n] and T {shift,2} [n] controls the capacitor gating. Finally, the two capacitor arrays are treated as a whole capacitor array for data weight averaging of the sigma-delta modulator, increasing the random depth with lower complexity.

[0090] Embodiment 3

[0091] like Figure 5 As shown, the present invention provides a data weight averaging system based on a dual capacitor array, comprising:

[0092] Signal acquisition module: used to acquire the input digital signal of the digital-to-analog converter, specifically, to acquire the digital signal D[n] output by the nth round of the quantizer, and use the digital signal D[n] as the input digital signal of the digital-to-analog converter;

[0093] The signal splitting module is used to split the input digital signal into two split digital signals, and the absolute value of the difference between the two split digital signals does not exceed 1. Specifically, the input digital signal D[n] is 5 bits, and the input digital signal D[n] is split into two digital signals S1[n] and S2[n], and S1[n] and S2[n] satisfy |S1[n]-S2[n]|<=1. The splitting method includes:

[0094] The input digital signal D[n] is represented as {D[n][4], D[n][3], D[n][2], D[n][1], D[n][0]}, where D[n][x] represents the bit value of the x-th bit of D[n], x∈{0,1,2,3,4};

[0095] Split D[n] into two equal 5-bit digital signals M1[n] and M2[n], represented as {0, D[n][3], D[n][2], D[n][1], D[n][0]};

[0096] Perform a majority vote on the 4 high-order bit values ​​of D[n] {D[n][4], D[n][3], D[n][2], D[n][1]} and output the voting value v[n]; if the number of 1s in the 4 high-order bit values ​​of D[n] exceeds 2, the voting value v[n] = 0; if the number of 1s in the 4 high-order bit values ​​of D[n] is less than 2, the voting value v[n] = 1; if the number of 1s in the 4 high-order bit values ​​of D[n] is equal to 2, the voting value v[n] = 1 or the voting value v[n] = 1 is output with equal probability;

[0097] The final split digital signals S1[n] and S2[n] are generated using the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n]. Specifically, if v[n]=0, then S1[n]=M1[n]+D[n][0], S2[n]=M2[n]+0; if v[n]=1, then S1[n]=M1[n]+0, S2[n]=M2[n]+D[n][0].

[0098] First-order dynamic element matching module: used to perform first-order dynamic element matching on two split digital signals on two independent capacitor arrays, obtain two matched capacitor arrays, and complete data weight averaging based on dual capacitor arrays, wherein first-order dynamic element matching is performed on two split digital signals respectively, specifically:

[0099] Convert S1[n] and S2[n] to thermometer codes T1[n] and T2[n];

[0100] Based on the thermometer codes T1[n] and T2[n], and the pointer positions P1[n] and P2[n], the thermometer codes are cyclically shifted to obtain the final output T {shift,1} [n] and T {shift,2} [n], complete the first-order dynamic element matching, the pointer position is calculated as:

[0101] P1[n]=S2[n]+P1[n-1]+16*O {overflow,1} [n];

[0102] P2[n]=S1[n]+P2[n-1]+16*O {overflow,2 [n];

[0103] Among them, O {overflow,1} [n] and O {overflow,2} [n] are all overflow items. When S2[n]+P1[n-1]>=16, O {overflow,1} [n] = -1, otherwise, O {overflow,1} [n]=0; when S1[n]+P2[n-1]>=16, O {overflow,2} [n] = -1, otherwise O {overflow,2} [n]=0.

[0104] The system of the present invention splits the input digital signal of the Sigma-delta ADC by setting a signal splitting module to obtain two smaller split digital signals, and the absolute value of the difference between the two split digital signals does not exceed 1. Then, by setting a first-order dynamic element matching module, the first-order dynamic element matching is performed on the two smaller split digital signals on two independent capacitor arrays, and when the two digital signals are respectively subjected to the first-order dynamic element matching, the position of the pointer is calculated based on another digital signal. The method is simple to implement and can effectively improve the random depth of the dynamic element matching and the conversion performance of the Sigma-delta ADC.

[0105] Embodiment 4

[0106] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the data weight averaging method based on a dual capacitor array when executing the computer program.

[0107] Embodiment 5

[0108] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data weight averaging method based on a dual capacitor array are implemented.

[0109] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0111] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0113] Finally, it should be noted that the above-listed embodiments exist only as one or more specific forms of expression of the technical solution of the present invention. Their purpose is to clearly explain the concept, principle and application of the present invention through specific examples, and it is by no means intended to limit the protection scope of the present invention to these specific embodiments. In fact, the real value of the present invention lies in the technical ideas and innovations it proposes, rather than its form of expression or means of implementation.

[0114] For ordinary technicians in the relevant technical field, after in-depth reading and understanding of the technical solution of the present invention, they are fully capable of making various forms of changes, modifications or equivalent substitutions to the specific implementation methods of the invention based on their own professional knowledge and skills. These changes may include but are not limited to: adjusting the value range of technical parameters, optimizing algorithm processes to improve efficiency, replacing some technical components to achieve better compatibility or reduce costs, etc. As long as these changed technical solutions still substantially maintain the technical features claimed for protection by the original invention, that is, they can still achieve the core functions and effects of the present invention, then these changes should be deemed to fall within the scope of protection of the pending claims of the present invention.

Claims

1. A data weight averaging method based on a dual capacitor array, characterized in that: The steps include: obtaining an input digital signal of a digital-to-analog converter; Splitting the input digital signal into two split digital signals, wherein the absolute value of the difference between the two split digital signals does not exceed 1; First-order dynamic element matching is performed on two split digital signals on two independent capacitor arrays to obtain two matched capacitor arrays, thereby completing data weight averaging based on dual capacitor arrays.

2. The data weight averaging method based on dual capacitor array according to claim 1, characterized in that: The step of obtaining the input digital signal of the digital-to-analog converter is specifically as follows: The digital signal D[n] outputted by the quantizer in the nth round is obtained, and the digital signal D[n] is used as the input digital signal of the digital-to-analog converter.

3. The data weight averaging method based on dual capacitor array according to claim 2, characterized in that: The step of splitting the input digital signal into two split digital signals, wherein the absolute value of the difference between the two split digital signals does not exceed 1, is specifically: The input digital signal D[n] is 5 bits, and the input digital signal D[n] is split into two digital signals S1[n] and S2[n], and S1[n] and S2[n] satisfy |S1[n]-S2[n]|<=1. The splitting method includes: The input digital signal D[n] is represented as {D[n][4], D[n][3], D[n][2], D[n][1], D[n][0]}, where D[n][x] represents the bit value of the x-th bit of D[n], x∈{0,1,2,3,4}; Split D[n] into two equal 5-bit digital signals M1[n] and M2[n], represented as {0, D[n][3], D[n][2], D[n][1], D[n][0]}; Perform a majority vote on the 4 high-order bit values ​​of D[n] {D[n][4], D[n][3], D[n][2], D[n][1]} and output the vote value v[n]; The final split digital signals S1[n] and S2[n] are generated using the voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n].

4. The data weight averaging method based on dual capacitor array according to claim 3, characterized in that: The output voting value v[n] is specifically: If the number of 1s in the 4 high-order bit values ​​of D[n] exceeds 2, the voting value v[n] = 0; If the number of 1s in the 4 high-order bit values ​​of D[n] is less than 2, the voting value v[n] = 1; If the number of 1s in the 4 high-order bit values ​​of D[n] is equal to 2, the voting value v[n]=1 or the voting value v[n]=1 is output with equal probability.

5. The data weight averaging method based on dual capacitor array according to claim 4, characterized in that: The voting value v[n] and the lowest bit of the input digital signal D[n], as well as M1[n] and M2[n], are used to generate the final split digital signals S1[n] and S2[n], specifically: If v[n]=0, then S1[n]=M1[n]+D[n][0], S2[n]=M2[n]+0; If v[n]=1, then S1[n]=M1[n]+0, S2[n]=M2[n]+D[n][0].

6. The data weight averaging method based on dual capacitor array according to claim 3, characterized in that: The first-order dynamic element matching is performed on the two split digital signals respectively, specifically: Convert S1[n] and S2[n] to thermometer codes T1[n] and T2[n]; Based on the thermometer codes T1[n] and T2[n], and the pointer positions P1[n] and P2[n], the thermometer codes are cyclically shifted to obtain the final output T {shift,1} [n] and T {shift,2} [n], completing first-order dynamic component matching.

7. The data weight averaging method based on dual capacitor array according to claim 6, characterized in that: The calculation method of the pointer position is: P1[n]=S2[n]+P1[n-1]+16*O {overflow,1} [n]; P2[n]=S1[n]+P2[n-1]+16*O {overflow,2 [n]; Among them, O {overflow,1} [n] and O {overflow,2} [n] are all overflow items. When S2[n]+P1[n-1]>=16, O {overflow,1} [n] = -1, otherwise, O {overflow,1} [n]=0; when S1[n]+P2[n-1]>=16, O {overflow,2} [n] = -1, otherwise O {overflow,2} [n]=0.

8. A data weight averaging system based on a dual capacitor array, characterized in that: include: Signal acquisition module: used to obtain the input digital signal of the digital-to-analog converter; A signal splitting module: used for splitting an input digital signal into two split digital signals, wherein the absolute value of the difference between the two split digital signals does not exceed 1; First-order dynamic element matching module: used to perform first-order dynamic element matching on two split digital signals on two independent capacitor arrays respectively, to obtain two matched capacitor arrays, and to complete data weight averaging based on dual capacitor arrays.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the data weight averaging method based on the dual capacitor array as claimed in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the data weight averaging method based on a dual capacitor array are implemented as claimed in any one of claims 1 to 7.

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