Data processing method and device based on low-power multi-core processor

Abstract

The present application relates to a data processing method and device based on a low-power multi-core processor. The method includes: the multi-core processor data is configured through a network configuration register group, and the register group sends an enable instruction to a data selector to start data transmission. After receiving the enable instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor to obtain storage information. The control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and sends the multi-core data processing result to a shared memory after being processed by an operation unit. The use of this method can reduce the memory access power consumption and delay in the reduction operation without changing the instruction set.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data processing method and device based on a low-power multi-core processor. Background Art

[0002] In modern computing systems, data access from processor cores to memory has become an increasingly critical bottleneck. As the speed gap between processors and memory has been growing steadily over the past few decades, a problem called the "memory wall" has emerged. In addition, due to the emergence of a large number of applications that access memory, such as the training process of deep neural networks in the field of artificial intelligence, a large amount of constant access to memory will be required, resulting in a "power wall" problem. With the recent trend of multi-core development, the cost of moving data from different memory levels to the core has increased, further exacerbating the problem of the memory wall. This problem will become more serious as technology scales up, because more transistors are squeezed into larger chips, increasing the relative cost of moving data to the computing core.

[0003] During data processing, data movement will increase request latency, increase data movement power consumption, and reduce system performance, and this impact will increase as the data size increases. Data movement is a necessary step in many big data applications (such as data analysis, data cleaning, and data aggregation). Data needs to be transferred from storage devices to computing units for further processing, and will be written back to storage devices after data processing is completed. Data movement takes up more than half of the execution time of data processing applications such as data analysis, data cleaning, and data aggregation. At the same time, the development of big data has increased the total amount of data processing in big data applications. Therefore, the data movement overhead between storage nodes and computing nodes has become an important factor affecting the performance of many big data applications.

[0004] In order to reduce the overhead caused by data movement during data processing, researchers proposed a reduction operation, also known as a folding operation, which is a process of aggregating all elements into a summary result through a certain connection action. Summing elements, finding the maximum or minimum value, finding the total number of elements, and converting all elements into a list or set are all reduction operations. This type of algorithm can generally perform a large number of parallel calculations, and after the parallel calculations are completed, it will be combined with a reduction operation, such as summing or comparing sizes. The usual calculation process is to transfer the intermediate results of other cores to the computing core for calculation. Because in this process, the data will first be transferred to the last level cache (Last Level Cache, LLC) and then to the computing core, so there will be a large number of memory access operations, resulting in greater memory access power consumption and delay. Summary of the invention

[0005] Based on this, it is necessary to provide a data processing method and device based on a low-power multi-core processor that can reduce memory access power consumption and delay in order to address the above technical problems.

[0006] A data processing method based on a low-power multi-core processor is applied to a reduction algorithm near-memory acceleration processing unit. The reduction algorithm near-memory acceleration processing unit includes: a register group, a data selector, a FIFO register group, a control unit and an operation unit.

[0007] The method comprises:

[0008] The multi-core processor data is configured through a network configuration register group, and the register group sends an open instruction to the data selector to start data transmission.

[0009] After receiving the start instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor to obtain storage information.

[0010] The control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and sends the multi-core data processing result to the shared memory after being processed by the operation unit.

[0011] In one embodiment, the register group includes: a setting register, a switch register and a result register, and also includes: after the multi-core processor data is configured through the configuration network setting register, the configuration parameters are obtained, the switch register is configured according to the configuration parameters, and the switch register sends an enable instruction to the data selector to start the data transmission of the reduction algorithm near memory acceleration processing unit.

[0012] In one embodiment, the method further includes: after receiving the start instruction, the data selector obtains the multi-core processor data through the data network, and screens the multi-core processor data to confirm the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor. If the value of the first FIFO memory of the FIFO register group is not empty, the storage information of the first data is obtained. Otherwise, the FIFO register group remains in a waiting state.

[0013] In one embodiment, the method further includes: after receiving the start instruction, the data selector obtains the multi-core processor data through the data network, and screens the multi-core processor data. If the address of the multi-core processor data is within the preset address range, and the current processor core model is within the preset core number range, the switch register of the reduction algorithm near storage acceleration processing unit is checked. If the switch register is in the on state, the first data participating in the reduction is obtained. Otherwise, the data selector removes the multi-core processor data that has been obtained.

[0014] In one embodiment, the control unit further includes: after the operation unit receives the first data, the control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and stores the multi-core data processing result in a result register through the operation unit. The result register sends the multi-core data processing result to the shared memory through the axi interface.

[0015] In one embodiment, the method further includes: the shared memory sends a shutdown instruction to the switch register, and the switch register receives the shutdown instruction and determines the counter value. If the counter value is equal to the register operation times of the operation unit, the FIFO register group automatically shuts down the reduction algorithm near memory acceleration processing unit. Otherwise, the reduction algorithm near memory acceleration processing unit is shut down by writing the shutdown instruction to the switch register through an external program.

[0016] A data processing device based on a low-power multi-core processor, the device comprising:

[0017] The data transmission startup module is used for multi-core processor data to configure the network configuration register group, and the register group sends an enable instruction to the data selector to start data transmission.

[0018] The process information storage module is used to obtain the multi-core processor data and determine the first data involved in the reduction after the data selector receives the start instruction. The first data is stored in the FIFO register group according to the address of the multi-core processor to obtain storage information.

[0019] The reduction processing module is used to control the control unit to perform a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and send the multi-core data processing result to the shared memory after being processed by the operation unit.

[0020] In one embodiment, the process information storage module is also used for obtaining multi-core processor data through a data network after the data selector receives the start instruction, and screening the multi-core processor data to confirm the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor. If the value of the first FIFO memory of the FIFO register group is not empty, the storage information of the first data is obtained. Otherwise, the FIFO register group remains in a waiting state for receiving.

[0021] In one embodiment, the process information storage module is also used for the data selector to obtain the multi-core processor data through the data network after receiving the start instruction, and to screen the multi-core processor data. If the address of the multi-core processor data is within the preset address range, and the current processor core model is within the preset core number range, then the switch register of the reduction algorithm near storage acceleration processing unit is checked. If the switch register is in the on state, the first data participating in the reduction is obtained. Otherwise, the data selector removes the multi-core processor data that has been obtained.

[0022] In one embodiment, the reduction processing module is further used to control the control unit to perform a reduction operation on the first data according to the storage information after the operation unit receives the first data, obtain a multi-core data processing result, and store the multi-core data processing result in a result register through the operation unit. The result register sends the multi-core data processing result to the shared memory through the axi interface.

[0023] The above-mentioned data processing method and device based on a low-power multi-core processor, the multi-core processor data is configured by configuring the network configuration register group, and the register group sends an enable instruction to the data selector to start data transmission. The register group can be flexibly configured to achieve efficient data selection. Furthermore, after the data selector receives the enable instruction, it obtains the multi-core processor data and determines the first data involved in the reduction, and temporarily stores the first data in the FIFO register group, thereby reducing the number of core memory accesses, reducing the number of network data transmission times, and reducing data network pressure, thereby reducing overall power consumption. After adding the NDP unit in the last level shared memory, the data flow of the reduction algorithm is changed, and the multi-core data processing results are sent to the shared memory after being processed by the operation unit. Without changing the instruction set, the inter-core reduction operation in the multi-core processor can be unloaded to the last level cache memory, with less hardware changes and relatively flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is an application scenario diagram of a data processing method based on a low-power multi-core processor in an embodiment;

[0025] Figure 2 A flowchart of a multi-core data processing method with near-memory acceleration of a reduction algorithm in one embodiment;

[0026] Figure 3 It is a structural block diagram of a reduction algorithm near-memory acceleration processing unit in one embodiment;

[0027] Figure 4 is a schematic diagram of a process of reducing a data flow in one embodiment;

[0028] Figure 5The structure block diagram of a data processing device based on a low-power multi-core processor in one embodiment. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0030] The multi-core data processing method with near-memory acceleration of reduction algorithm provided in this application can be applied to Figure 1 In the application environment shown. Among them, CORE0, CORE1, CORE2, CORE3...COREN are multi-core processors, 1×2 switch is a one-to-two splitter, LLC is the last level cache (LLC), DDR is a double data rate synchronous dynamic random access memory (Double Data Rate), result FIFO is a result buffer memory (First Input First Output), NDP is a reduction algorithm near storage acceleration processing unit, and BANK is a memory bank. In addition, the configuration network can be but not limited to various packet switching networks, ATM networks, Internet, IP networks, local area networks, metropolitan area networks, wide area networks, etc., and the data network can be but not limited to various packet switching networks, ATM networks, Internet, IP networks, local area networks, metropolitan area networks, wide area networks, etc. The configuration network and the data network are in the same network environment, respectively, with the processor core, one-to-two splitter, LLC, result FIFO, NDP, double data rate synchronous dynamic random access memory, configuration registers and BANK for data transmission and interconnection.

[0031] In one embodiment, Figure 2 As shown, a data processing method based on a low-power multi-core processor is provided, and the method is applied to Figure 1 The low-power multi-core processor with near-memory acceleration of the reduction algorithm in FIG. 1 is used as an example to illustrate the method, which includes the following steps:

[0032] Step 202, the multi-core processor data is configured through a network configuration register group, and the register group sends an open instruction to a data selector to start data transmission.

[0033] The register group includes setting registers, switch registers, and result registers.

[0034] Specifically, the programmer packages the configuration function into a library through software programming, and uses the configuration code to transmit the configuration information to the corresponding register through the configuration network, that is, the multi-core processor data configures each configuration register in the register group through the configuration network. Usually, the configuration information is transmitted to a fixed address for writing. The register group can be configured in batches, or each register can be configured individually. For example, the code NDP_Op_type (unint_32t) indicates that the data calculated this time is a 32-bit unsigned number, and the code NDP_Op_type (unint_64t) indicates that the data calculated this time is a 64-bit unsigned number. Other configurable registers are shown in Table 1:

[0035] Table 1 Configurable register information

[0036]

[0037] Furthermore, first configure the Data_From register to configure whether to offload single-core instructions or perform multi-core reduction, and then configure the NDP_Group_Choose register to decide which group of reduction operations to configure, such as Figure 3 As shown, each time a group of reduction operations is configured, each group of reduction operations has a corresponding group of configuration registers, each group of reduction operations corresponds to an operation unit, and each group of operation units corresponds to a result FIFO register. There are two computing units in the figure, and correspondingly there are two result FIFO registers.

[0038] Furthermore, when the preset number of registers are configured, multiple configuration parameters are obtained, and the configuration parameters are sent to the switch register for switch register configuration. After the configuration is completed, the reduction algorithm near memory acceleration processing unit (hereinafter referred to as NDP) is started, and the start instruction is sent to the data selector. At this time, the programmer reads the NDP_DSP_Ready register, reads out the corresponding processor core that needs to participate in this operation, and performs data transmission.

[0039] Step 204, after receiving the start instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction, and stores the first data in the FIFO register group according to the address of the multi-core processor to obtain storage information.

[0040] Specifically, after receiving the start command, the data selector (i.e., the splitter divided into two) obtains the multi-core processor data from the data network, and then makes a judgment in the splitter. The data of processor core 0 (i.e., CORE0) is transmitted to the 1x2switch module. According to the preset configuration information, the host ID (AWHOSTID) of the axi interface is used to check whether the data comes from the processor core participating in this reduction operation, and further check whether the data address (AWADDR) is within a specific address range. The address division is shown in Table 2:

[0041] Table 2 Address identification division table

[0042]

[0043] The reserved data addresses in different processor systems are different and can be changed by yourself. Finally, check whether the NDP unit is turned on. The preset configuration information includes the data address range, processor core number range and register configuration parameters.

[0044] Furthermore, if the address of the multi-core processor data is within a preset address range, and the current processor core model is within a preset core number range, the switch register of the NDP unit is checked; if the switch register is in an on state, the first data participating in the reduction is obtained; otherwise, the data selector (i.e., a splitter that divides into two) eliminates the acquired multi-core processor data.

[0045] Furthermore, the first data selected is stored in the FIFO register group according to the address of the multi-core processor. The data of processor core 0 (CORE0) enters the FIFO0 memory, the data of processor core 1 (CORE1) enters the FIFO1 memory, and so on, that is, the data of processor core N (COREN) enters the FIFON memory. If the data value of the first FIFO memory (i.e., FIFO0) is not empty, the FIFO register group is ready, the multi-core processor data is temporarily stored, and the storage information from the FIFO0 memory to the FIFON memory is generated at the same time. The FIFO register group returns the storage information to the control unit one by one.

[0046] Step 206: The control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and sends the multi-core data processing result to the shared memory after being processed by the operation unit.

[0047] Specifically, the Fifo_Ready_Info register collects the storage information of all FIFO register groups that are ready, and compares it with the NDP_DSP_Ready register, that is, the data readiness information in the current FIFO register group is compared with the data information required for this reduction operation. If it meets the requirements of NDP_DSP_Ready, the control unit transfers the multi-core processor data to the operation unit according to the storage information. If the data is not completely ready, the FIFO register group and the control unit remain in the waiting to receive state and the waiting to send state.

[0048] Furthermore, when the data participating in the reduction enters the operation unit, the reduction operation is performed according to the storage information of the control unit, and the result is temporarily stored in the result register, waiting for the right time. The result register sends the multi-core data processing result to the shared memory (i.e., the last level memory LLC) through the axi interface.

[0049] Furthermore, there is a counter in the operation unit. Each time a reduction operation is completed, the counter is incremented. If the counter value is equal to the number of register operations of the operation unit, the FIFO register group automatically turns off the reduction algorithm near-memory acceleration processing unit. On the contrary, if there is still data in the FIFO register group, an error is reported. At this time, the programmer needs to write a shutdown instruction to the switch register through software programming, manually turn off the NDP unit, and perform debugging.

[0050] In the above-mentioned data processing method based on low-power multi-core processor, the multi-core processor data is configured by configuring the network configuration register group, and the register group sends an enable instruction to the data selector to start data transmission. The register group can be flexibly configured to achieve efficient data selection. Furthermore, after receiving the enable instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction, and temporarily stores the first data in the FIFO register group, thereby reducing the number of memory accesses of the core to the memory, reducing the number of network data transmissions, and reducing the pressure on the data network, thereby reducing the overall power consumption. After adding the NDP unit in the last level shared memory, the data flow of the reduction algorithm is changed, and the multi-core data processing results are sent to the shared memory after being processed by the operation unit. Without changing the instruction set, the inter-core reduction operation in the multi-core processor can be unloaded to the last level cache memory for execution, with less hardware changes and relatively flexible.

[0051] In one embodiment, the register group includes: a setting register, a switch register and a result register.

[0052] After the multi-core processor data passes through the configuration network configuration setting register, the configuration parameters are obtained, and the switch register is configured according to the configuration parameters. The switch register sends an opening instruction to the data selector to start the data transmission of the reduction algorithm near memory acceleration processing unit.

[0053] In one embodiment, after receiving the start instruction, the data selector obtains the multi-core processor data through the data network, and screens the multi-core processor data to confirm the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor. If the value of the first FIFO memory of the FIFO register group is not empty, the storage information of the first data is obtained. Otherwise, the FIFO register group remains in a waiting state.

[0054] It is worth mentioning that the FIFO register group is a high-speed cache memory group. From the RTL level (register conversion level), it almost does not involve changes to the architecture source code. The registers used are reserved registers in the LLC, which do not require additional resources and have excellent debuggability.

[0055] In one embodiment, after receiving the start instruction, the data selector obtains the multi-core processor data through the data network and screens the multi-core processor data. If the address of the multi-core processor data is within a preset address range and the current processor core model is within a preset core number range, the switch register of the reduction algorithm near storage acceleration processing unit is checked. If the switch register is in the on state, the first data participating in the reduction is obtained. Otherwise, the data selector removes the multi-core processor data that has been obtained.

[0056] It can be seen that it has a high degree of parallelism, and different cores can be specified to perform multiple types of reductions at the same time, and multi-core reduction and single-core simple instruction offloading can also be performed at the same time. In addition, not only can inter-core reduction be completed, but also simple instructions of a single core can be offloaded to LLC, which is more functional.

[0057] In one embodiment, after the operation unit receives the first data, the control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and stores the multi-core data processing result in a result register through the operation unit. The result register sends the multi-core data processing result to the shared memory through the axi interface.

[0058] It is worth noting that the process of unloading simple instructions for a single core is the same as above. You only need to configure the Data_From register in advance, select the direction of data flow, and enter the NDP unit from the DDR to unload simple instructions and complete the operation in the LLC. It can be seen that there is no need to add a new instruction set. For systems with a high degree of completion, the NDP unit has the characteristics of being easy to add and has a wider range of adaptation environments.

[0059] In one embodiment, the shared memory sends a shutdown instruction to the switch register, and the switch register receives the shutdown instruction to determine the counter value. If the counter value is equal to the register operation times of the operation unit, the FIFO register group automatically shuts down the reduction algorithm near memory acceleration processing unit. Otherwise, the reduction algorithm near memory acceleration processing unit is shut down by writing the shutdown instruction to the switch register through an external program.

[0060] It is worth mentioning that the NDP unit is divided into three modules: operation module, control module and intermediate result data storage module. Control module: contains various registers for data flow control and process control. Programmers need to actively configure registers, so the register group is set to readable. To ensure that programmers can debug, all registers are set to writable. Intermediate result data storage module: mainly contains four groups of intermediate data FIFO cache memories and receives control signals from the control unit. When the conditions are met, the data is transferred to the operation unit. The FIFO cache memory receives the intermediate results from the four processor cores and transfers the corresponding data to the corresponding FIFO according to the conditions. For example, the data participating in the reduction from core 0 is transferred to FIFO0, and the other three FIFOs are analogous. Operation module: This module is used to store the results of the reduction operation and is sent to the shared storage (i.e., the last level memory LLC) through the axi interface under the control of the control module. Therefore, by moving the calculation closer to the data location in the main memory or cache memory (FIFO register group), the delay and energy overhead caused by data movement can be greatly reduced.

[0061] In one embodiment, NDP_Addr_L and NDP_Addr_H are used to store the result address. In this architecture, the address bit size is 36 bits. Since the register size is only 32 bits, two registers are required to store the high bit and the low bit respectively, as shown in Table 3 and Table 4 respectively:

[0062] Table 3 NDP_Addr_H

[0063]

[0064] Table 4 NDP_Addr_L

[0065]

[0066] If the array a[n] is the reduction result, the programmer can use the line of code NDP_Addr_L(&a[0]); in the library function to configure the first address of the reduction result.

[0067] In one embodiment, the NDP_Op_Info register can be used for overall configuration, with a large amount of information and each bit having a specific meaning, as shown in Table 5:

[0068] Table 5 NDP_Op_Info

[0069]

[0070] In one embodiment, the NDP unit can be configured with multiple operations, and multiple different reduction operations are performed in parallel. The NDP_Group_Choose register indicates which group of reduction operations is configured this time, as shown in Table 6:

[0071] Table 6 NDP_Group_Choose

[0072]

[0073] If a single register is configured separately, this register is configured first, indicating which group it is. NDP_Group_Choose(0); indicates that this group is the 0th group reduction operation, and then other registers are configured later.

[0074] In one embodiment, the NDP_Op_Typ register is the type of the current operation. For example, if this operation is addition or comparison, NDP_Op_Type(1); indicates that this operation is addition, as shown in Table 7:

[0075] Table 7 NDP_Op_Typ

[0076]

[0077] In one embodiment, the NDP_DSP_Ready register indicates which processor cores participate in the current round of reduction operations. NDP_DSP_Ready (1110); indicates that the numbers required for this group of reduction operations come from cores 0, 1, and 2 respectively; NDP_DSP_Ready (1101); indicates that the numbers required for this group of reduction operations come from cores 0, 1, and 3 respectively. As shown in Table 8:

[0078] Table 8 NDP_DSP_Ready

[0079]

[0080] In one embodiment, the NDP_Op_Numb register indicates the total number of calculations for this group of reductions, NDP_Op_Numb(i); there are i times in this round of loops, and a total of i calculations are performed. As shown in Table 9:

[0081] Table 9 NDP_Op_Numb

[0082]

[0083] In one embodiment, the NDP_OP_Ready register indicates the overall switch status of the NDP unit, NDP_OP_Ready (1); the NDP unit is turned on. As shown in Table 10:

[0084] Table 10 NDP_OP_Ready

[0085]

[0086] In one embodiment, the NDP_Op_Arg_Type register is the data type of the operation of this group and the data type of the calculation result, which can be used to configure the AWSIZE interface in the axi interface and used as an offset to calculate the address of the subsequent reduction result. As shown in Table 11:

[0087] Table 11 NDP_Op_Arg_Type

[0088]

[0089] In one embodiment, Data_From is used to determine whether to accept data from the core or the DDR. Data_From(1); indicates that multi-core reduction is performed this time; Data_From(0); indicates that only related operations of a single core can be configured this time. As shown in Table 12:

[0090] Table 12 Data_From

[0091]

[0092] In one embodiment, the Fifo_Ready_Info register is read-only and is used to indicate the ready state of the data FIFO, as shown in Table 13:

[0093] Table 13 Fifo_Ready_Info

[0094]

[0095] In one embodiment, if Figure 4As shown, for the data storage of the reduction algorithm of the multi-core processor during the loading process, there is no NDP unit: C0, C1, C2, C3 are the data in cores 0, 1, 2, and 3 respectively. At this time, DSP core 0 is used as the main core to perform the operation C=C0+C1+C2+C3. When there is no NDP, the first step is for each core to transfer its own data to LLC through the data network, that is, steps ①② in the figure; the second step is for DSP0 to take the data from LLC and transfer it to DSP0 for calculation, that is, steps ④⑤ in the figure; the third step is for DSP0 to obtain the calculation result C, and write the data back to LLC through the data network, that is, steps ①② in the figure. The complete process of this process is ①②④⑤①②, and there are three memory accesses during the period.

[0096] Add NDP unit: When performing the inter-core operation of C=C0+C1+C2+C3, the DSP0 core sends the operation command to the NDP through the configuration network. Each core directly transmits the data to the NDP through the data network, which is steps ①③ in the figure. After the NDP unit completes the calculation, it directly writes the result to the LLC, which is step ⑥ in the figure. The complete process of this process is ①③⑥, during which there is a total of one memory access. The number of memory accesses is significantly reduced after adding the NDP unit.

[0097] In one embodiment, if Figure 4 As shown, for a single-core processor, the data storage of the reduction algorithm is in the loading process, simple instruction unloading, and no NDP unit: the data is transferred from the LLC to the core for calculation, and then the result is transferred back to the LLC. The complete process is ④⑤①②, during which there are two memory access operations.

[0098] Add NDP unit: data directly enters the NDP module from DDR, and after the calculation is completed, the result is written to the corresponding LLC address for use. That is, after the data is written from DDR to LLC, the calculation reduces two memory accesses.

[0099] It should be understood that although Figure 1-Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-Figure 4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0100] In one embodiment, Figure 5As shown, a multi-core data processing device with near-memory acceleration of reduction algorithm is provided, including: a data transmission starting module 502, a process information storage module 504 and a reduction processing module 506, wherein:

[0101] The data transmission start module 502 is used for multi-core processor data to configure the network configuration register group, and the register group sends an open instruction to the data selector to start data transmission.

[0102] The process information storage module 504 is used to obtain the multi-core processor data and determine the first data involved in the reduction after the data selector receives the start instruction. The first data is stored in the FIFO register group according to the address of the multi-core processor to obtain storage information.

[0103] The reduction processing module 506 is used to control the control unit to perform a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and send the multi-core data processing result to the shared memory after being processed by the operation unit.

[0104] In one embodiment, the process information storage module 504 is also used for obtaining multi-core processor data through a data network after the data selector receives the start instruction, and screening the multi-core processor data to confirm the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor. If the value of the first FIFO memory of the FIFO register group is not empty, the storage information of the first data is obtained. Otherwise, the FIFO register group remains in a waiting state.

[0105] In one embodiment, the process information storage module 504 is also used for the data selector to obtain the multi-core processor data through the data network after receiving the start instruction, and to screen the multi-core processor data. If the address of the multi-core processor data is within the preset address range, and the current processor core model is within the preset core number range, then the switch register of the reduction algorithm near storage acceleration processing unit is checked. If the switch register is in the on state, the first data participating in the reduction is obtained. Otherwise, the data selector removes the multi-core processor data that has been obtained.

[0106] In one embodiment, the reduction processing module 506 is further used to control the control unit to perform a reduction operation on the first data according to the storage information after the operation unit receives the first data, obtain a multi-core data processing result, and store the multi-core data processing result in a result register through the operation unit. The result register sends the multi-core data processing result to the shared memory through the axi interface.

[0107] For the specific definition of the data processing device based on the low-power multi-core processor, please refer to the definition of the data processing method based on the low-power multi-core processor above, which will not be repeated here. Each module in the above-mentioned data processing device based on the low-power multi-core processor can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0108] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0109] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0110] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data processing method based on a low-power multi-core processor, characterized in that: Applied to a reduction algorithm near-memory acceleration processing unit, the reduction algorithm near-memory acceleration processing unit comprises: a register group, a data selector, a FIFO register group, a control unit and an operation unit; The method comprises: The multi-core processor data configures the register group through a configuration network, and the register group sends an enable instruction to the data selector to start data transmission; After receiving the start instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction, and stores the first data in the FIFO register group according to the address of the multi-core processor to obtain storage information; The control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and sends the multi-core data processing result to the shared memory after being processed by the operation unit.

2. The method according to claim 1, characterized in that The register group includes: a setting register, a switch register and a result register; The multi-core processor data configures the register group through the configuration network, and the register group sends an opening instruction to the data selector to start data transmission, including: After the multi-core processor data configures the setting register through the configuration network, the configuration parameters are obtained, and the switch register is configured according to the configuration parameters. The switch register sends an enable instruction to the data selector to start the data transmission of the reduction algorithm near memory acceleration processing unit.

3. The method according to claim 1, characterized in that After receiving the start instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction, and stores the first data in the FIFO register group according to the address of the multi-core processor to obtain storage information, including: After receiving the start instruction, the data selector obtains the multi-core processor data through the data network, and screens the multi-core processor data to confirm the first data involved in the reduction; The first data is stored in the FIFO register group according to the address of the multi-core processor. If the value of the first FIFO memory of the FIFO register group is not empty, the storage information of the first data is obtained; otherwise, the FIFO register group remains in a waiting state for reception.

4. The method according to claim 3, characterized in that After receiving the start instruction, the data selector obtains the multi-core processor data through the data network, and screens the multi-core processor data to confirm the first data involved in the reduction, including: After receiving the start instruction, the data selector obtains the multi-core processor data through the data network and filters the multi-core processor data. If the address of the multi-core processor data is within a preset address range and the current processor core model is within a preset core number range, the switch register of the reduction algorithm near memory acceleration processing unit is checked; if the switch register is in the on state, the first data participating in the reduction is obtained; otherwise, the data selector discards the multi-core processor data that has been obtained.

5. The method according to claim 2, characterized in that: The control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and sends the multi-core data processing result to a shared memory after being processed by the operation unit, including: After the operation unit receives the first data, the control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and stores the multi-core data processing result into the result register through the operation unit; the result register sends the multi-core data processing result to the shared memory through the axi interface.

6. The method according to claim 5, characterized in that After the step of sending the multi-core data processing result to the shared memory after being processed by the operation unit, the method further includes: The counter in the operation unit counts after each reduction operation. If the value of the counter is equal to the number of register operations of the operation unit, the FIFO register group automatically turns off the reduction algorithm near-memory acceleration processing unit; otherwise, a closing instruction is written to the switch register through an external program to turn off the reduction algorithm near-memory acceleration processing unit.

7. A data processing device based on a low-power multi-core processor, characterized in that: The device comprises: A data transmission start module, used for multi-core processor data to configure a network configuration register group, and the register group sends an opening instruction to the data selector to start data transmission; A process information storage module, used for the data selector to obtain the multi-core processor data and determine the first data involved in the reduction after receiving the start instruction, and the first data is stored in the FIFO register group according to the address of the multi-core processor to obtain storage information; The reduction processing module is used to control the control unit to perform a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and send the multi-core data processing result to the shared memory after being processed by the operation unit.

8. The device according to claim 7, characterized in that The process information storage module is further used for the data selector to obtain the multi-core processor data through the data network after receiving the start instruction, and to screen the multi-core processor data to confirm the first data involved in the reduction; The first data is stored in the FIFO register group according to the address of the multi-core processor. If the value of the first FIFO memory of the FIFO register group is not empty, the storage information of the first data is obtained; otherwise, the FIFO register group remains in a waiting state for reception.

9. The device according to claim 7, characterized in that The process information storage module is also used for the data selector to obtain the multi-core processor data through the data network after receiving the start instruction, and to filter the multi-core processor data. If the address of the multi-core processor data is within a preset address range and the current processor core model is within a preset core number range, the switch register of the reduction algorithm near storage acceleration processing unit is checked; if the switch register is in the on state, the first data participating in the reduction is obtained; otherwise, the data selector discards the multi-core processor data that has been obtained.

10. The device according to claim 7, characterized in that The reduction processing module is further used for the control unit to perform a reduction operation on the first data according to the storage information after the operation unit receives the first data, to obtain a multi-core data processing result, and to store the multi-core data processing result into a result register through the operation unit; The result register sends the multi-core data processing result to the shared memory through the axi interface.

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