Configurable network on chip

Abstract

The embodiment of the invention provides a configurable network-on-chip, the network-on-chip can comprise at least one sub-network with k-element n-dimensional nodes, the nodes of the network-on-chip are connected through network links, and a selector is arranged between adjacent nodes. And controlling the on-off of all network links in the sub-networks and all network links among the sub-networks through a selector so as to configure the topological structure of the network on chip. The topological structure of the network-on-chip can be flexibly configured according to task requirements, so that the network-on-chip has good expandability, and the problems that an existing topological structure of the network-on-chip is large in transmission delay and single in transmission path in a complex task scene are solved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular, to a configurable network on chip. Background Art

[0002] Neural network processing unit (NPU) is the most representative multi-core architecture at present, with broad application prospects and great potential in the future. However, the traditional communication method limits the communication bandwidth, number of cores and scalability of NPU. Introducing the network on chip (NoC) as a bus interconnection architecture into NPU will greatly alleviate the limitation of communication bandwidth and facilitate the increase and expansion of NPU cores.

[0003] However, with the increase in the number of NPU cores, the existing on-chip network topology has problems such as a single transmission path and large transmission delay in complex task scenarios. Summary of the invention

[0004] The embodiment of the present invention provides a configurable on-chip network to at least solve the problems of a single transmission path and large transmission delay in the existing on-chip network topology structure in complex task scenarios in the related art.

[0005] According to an embodiment of the present invention, a configurable on-chip network is provided, the on-chip network comprising at least one sub-network of k-ary and n-dimensional nodes; the nodes of the on-chip network are connected via network links; a selector is connected between two adjacent nodes;

[0006] The selector is used to configure the topology of the on-chip network by controlling the on-off of all network links of the on-chip network.

[0007] In an exemplary embodiment, the sub-network includes bridge nodes, and the bridge nodes of different sub-networks are connected via the network links.

[0008] In an exemplary embodiment, the network on chip further includes a bridge node, and the bridge node is located between sub-networks; wherein each of the pier nodes is connected to one of the bridge nodes, and a plurality of adjacent pier nodes are connected to the same bridge node.

[0009] In an exemplary embodiment, a plurality of the bridge nodes are connected via the network link; and the selector is connected between adjacent bridge nodes.

[0010] In an exemplary embodiment, the network link includes at least one of the following types: a mesh link, a ring link, and a configurable link.

[0011] In an exemplary embodiment, two ends of the configurable link are respectively connected to different selectors; wherein the configurable link is a cross-node link, and the two ends of the configurable link are configured to cross one or more nodes.

[0012] In an exemplary embodiment, the selector is further configured to select one of the network links to be connected when a plurality of the network links are connected.

[0013] In an exemplary embodiment, the bridge nodes in the same row or column are connected via the ring links.

[0014] In an exemplary embodiment, the topology of the on-chip network includes an intra-subnetwork topology and an inter-subnetwork topology, and the intra-subnetwork topology and the inter-subnetwork topology are configured with different routing algorithms; wherein the inter-subnetwork topology is a topology formed by connecting multiple bridge nodes through the network links.

[0015] In an exemplary embodiment, the bridge node is configured with an inter-sub-network routing algorithm according to the inter-sub-network topology structure.

[0016] In an exemplary embodiment, the sub-network further includes non-pier nodes, and the non-pier nodes in the topological structure within the sub-network and the pier nodes in the topological structure within the sub-network are configured with different routing algorithms.

[0017] In an exemplary embodiment, the non-bridge node is configured with a label relabeling algorithm, and the bridge node is configured with a fusion routing algorithm of the inter-subnetwork routing algorithm and the relabeling algorithm.

[0018] In this embodiment, the configurable on-chip network of the present application may include one or more sub-networks of k-ary and n-dimensional nodes, the nodes of the on-chip network are connected by network links, and selectors are provided between adjacent nodes, and the on-off of all network links within the sub-network and all network links between sub-networks is controlled by the selector to configure the topological structure of the on-chip network. The topological structure of the on-chip network can be flexibly configured according to task requirements, so that the on-chip network has good scalability, thereby solving the problems of large transmission delay and single transmission path in the existing on-chip network topological structure in complex task scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a diagram of a configurable on-chip network structure according to an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a configurable heterogeneous sub-network structure according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a ring-type topology structure configured as a sub-network according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of a mesh topology structure configured as a sub-network according to an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of a cmesh topology structure in which a sub-network is configured according to an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of a torus-type topology structure in which a sub-network is configured according to an embodiment of the present invention;

[0025] Figure 7 is a schematic diagram of a tree-type topology structure configured as a sub-network according to an embodiment of the present invention;

[0026] Figure 8 is a schematic diagram of a hypercube topology structure in which a sub-network is configured according to an embodiment of the present invention;

[0027] Fig. 9 is a schematic diagram of a global integration of 2x2 heterogeneous sub-networks according to an embodiment of the present invention;

[0028] Fig.10 is a schematic diagram of a global integration of 2x4 heterogeneous sub-networks according to an embodiment of the present invention;

[0029] Fig.11 is a schematic diagram of a global integration of 4x4 heterogeneous sub-networks according to an embodiment of the present invention;

[0030] Fig.12 It is a schematic diagram of routing numbers within a network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0033] The Network on Chip (NoC) borrows the communication mode of distributed computing system and adopts routing and packet switching technology to replace the traditional bus. It is a new method to solve the complex on-chip communication problem. NoC technology solves the three major problems inherent in the bus structure from the perspective of architecture: scalability problems caused by limited address space, communication efficiency problems caused by time-sharing communication, and power consumption and area problems caused by global synchronization.

[0034] The key technologies of on-chip network are:

[0035] Topology: The topology of a NoC is the arrangement of communicating node elements. The ability of a NoC to communicate effectively depends largely on the underlying topology.

[0036] Routing algorithm: The routing algorithm establishes the path that each message or packet will execute, and searches for a path on the on-chip network structure that satisfies certain restrictions on data transmission.

[0037] At present, there are three main topological structures of on-chip networks: mesh, torus and tree. The routing algorithm mainly adopts XY dimensional order routing algorithm. The topological structure proposed in the prior art is designed for a certain type of specific application and does not have the configurable characteristics according to the application task. At the same time, the corresponding routing algorithm is designed for a specific topology and does not have the ability to route for multiple topologies.

[0038] The Network on Chip (NoC) is mainly used to solve the communication problem in multi-core / many-core architecture. The topology structure and routing algorithm are the key points of NoC technology. A suitable topology structure and routing algorithm will greatly improve the communication capability between multi-core / many-core. After NoC is introduced into NPU as a bus interconnection architecture, the limitation of communication bandwidth will be greatly alleviated, which will facilitate the increase and expansion of NPU cores.

[0039] However, as the number of NPU cores increases, the existing topology has problems such as large transmission delay and single transmission path. In addition, the diversity of NPU network connections and the huge amount of data make single topology structures such as mesh and torus connections prone to certain communication problems.

[0040] The technical concept of the present application is to select a k-element n-dimensional network unit as a subnetwork of the on-chip network. The on-chip network can be composed of one or more subnetworks. The nodes of the on-chip network are connected through network links, and selectors are set between nodes in each subnetwork, and selectors are set between nodes between subnetworks. The selectors are used to control the on-off of all network links in the subnetwork and all network links between subnetworks, and configure the topological structure of the on-chip network. The topological structure of the on-chip network can be flexibly configured according to task requirements, so that the on-chip network has good scalability, thereby solving the problems of large transmission delay and single transmission path in the existing on-chip network topological structure in complex task scenarios.

[0041] The embodiments of the present invention support communication tasks of multi-core / many-core systems and are suitable for artificial intelligence (AI) acceleration application environments such as services and communications, including but not limited to scenarios such as data centers, autonomous driving, virtual currency, and terminal AI.

[0042] Figure 1 : is a structural diagram of a configurable on-chip network according to an embodiment of the present invention, wherein the on-chip network includes at least one sub-network 10 with k-ary and n-dimensional nodes, such as Figure 1 As shown, taking the on-chip network including a 4-element 2-dimensional (i.e., 4×4) sub-network 10 as an example, the nodes 101 of the on-chip network are connected by network links 102; a selector 103 is connected between two adjacent nodes; the selector is used to configure the topology of the on-chip network by controlling the on-off of all network links of the on-chip network.

[0043] The on-chip network technology is a process of converting data transmission between IP cores into data forwarding between routers. The nodes on the on-chip network may include a processing unit node and a router node, and a router may be connected to a processing unit. In the embodiment of the present invention, the routing node is used as a node on the sub-network for explanation.

[0044] Here, K is the number of nodes on the edge of each subnetwork. For example, a 4x4 mesh subnetwork and a 4-element 2-dimensional torus subnetwork both have a total of 16 nodes.

[0045] Exemplarily, a 4x4 sub-network 10 may be built first, and the nodes 101 in the sub-network 10 are connected via a network link 102 . On this basis, a selector 103 may be added, and the selector 103 is set between each adjacent node 101 . The selector 103 is connected to the adjacent node 101 via the network link 102 .

[0046] Exemplarily, the selector 103 may control the network link 102 , thereby controlling the input and output of the node.

[0047] The selector 103 of this embodiment can switch all links in the sub-network in real time according to application requirements to achieve heterogeneity of the sub-network.

[0048] It should be noted that the above selection of a sub-network of size 4x4 is only an example, and sub-networks of other sizes may also be selected in the heterogeneous method, such as 3x3, 5x5, etc., and the embodiment of the present invention is not limited thereto.

[0049] In an exemplary embodiment, the network link includes at least one of the following types: a mesh link, a ring link, and a configurable link.

[0050] For example, Figure 2 is a schematic diagram of a configurable heterogeneous sub-network structure according to an embodiment of the present invention, referring to Figure 2The subnetwork includes a network link 201, a router 202, a processing unit 203, a network interface (NI) (not shown in the figure), and a selector 204. The network link 201 may include at least the following three link structures: a mesh link 2011, a ring link 2012, and a configurable link 2013.

[0051] As an example, the mesh structure link 2011 is the link in the horizontal and vertical directions of the router, the ring link 2012 is the link between the sub-network edge nodes, and the configurable link 2013 is a link added to increase the variability of the topology and is a cross-node link.

[0052] In an exemplary embodiment, two ends of the configurable link 2013 are respectively connected to different selectors; wherein the configurable link 2013 is a cross-node link, and the two ends of the configurable link 2013 are configured to cross one or more nodes.

[0053] Exemplarily, the two ends of the configurable link 2013 can be connected to different selectors respectively, and the configurable link 2013 can span one or more nodes according to the size of the sub-network. The configurable link 2013 can be connected to the same selector as the mesh structure link 2011 and the ring link 2012 in the same direction of some nodes.

[0054] In an exemplary embodiment, the selector 204 is further configured to select one of the network links 202 for connection when multiple network links 202 are connected.

[0055] For example, when multiple network links are connected, the selector can select a suitable network link to connect according to the actual application scenario to reduce the technical problem of large transmission delay. Figure 2 As shown, one end of the selector 204 is connected to the router 202 via a network link 201, and the other end is connected to different routers via two network links 201. One of the two network links 201 connected to the selector 204 may be a configurable link 2013, and the configurable link 2013 may be connected to another selector across a node. When the selector chooses to connect to the configurable link 2013, the subnetwork may achieve cross-node communication.

[0056] As an example, a subnetwork can control the on and off of network links between nodes in the subnetwork through a selector to achieve heterogeneity of the subnetwork. For example, the topology structure in the subnetwork can be configured as a ring structure, a mesh structure, a concentrated mesh structure (cmesh), a torus structure, a tree structure, a hypercube structure, and other irregular topology structures through a selector.

[0057] The following is a further explanation of the heterogeneity of sub-networks through some examples:

[0058] Example 1:

[0059] Figure 3 is a schematic diagram of a ring-type topology structure configured as a sub-network according to an embodiment of the present invention, such as Figure 3 As shown in the figure, the gray links are disabled links and the black links are enabled links. The selector only needs to control some mesh links to be enabled to configure a ring topology.

[0060] Example 2:

[0061] Figure 4 is a schematic diagram of a mesh topology structure configured as a sub-network according to an embodiment of the present invention, such as Figure 4 As shown in the figure, the gray links are disabled links, and the black links are enabled links. The selector only needs to control some mesh links to be enabled to configure a mesh topology.

[0062] Example 3:

[0063] Figure 5 is a schematic diagram of a cmesh topology structure configured as a sub-network according to an embodiment of the present invention, such as Figure 5 As shown, the gray links are disabled links, and the black links are enabled links. To facilitate the expansion of the topology, the corner nodes of the subnetwork can be selected as the centralized nodes of the cmesh topology. The selector only needs to control the opening of some mesh links and ring links to configure the cmesh topology.

[0064] Example 4:

[0065] Figure 6 is a schematic diagram of a torus-type topology structure configured as a sub-network according to an embodiment of the present invention, such as Figure 6 As shown, the gray links are disabled links, and the black links are enabled links. The selector only needs to control the mesh link and ring link to be enabled to configure the torus topology.

[0066] Example 5:

[0067] Figure 7 Schematic diagram of a tree-type topology structure of a sub-network configuration according to an embodiment of the present invention, such as Figure 7 As shown in the figure, the gray links are disabled links, and the black links are enabled links. To facilitate the expansion of the topology, the corner nodes of the subnetwork can be selected as the root nodes of the tree topology. The selector only needs to control the opening of some mesh links, ring links, and configurable links to configure the tree topology structure. The root node of the tree topology can be selected according to the needs of horizontal expansion.

[0068] Example 6:

[0069] Figure 8 Schematic diagram of a hypercube topology structure of a sub-network according to an embodiment of the present invention. Figure 8 As shown, the gray links are disabled links, and the black links are enabled links. The selector only needs to control some mesh links and configurable links to be enabled to configure a hypercube topology.

[0070] The embodiments of the present invention increase the variability of the topology of the on-chip network by adding selectors and partially configurable links. The topology can be configured into a desired topology according to the application scenario, and the topology can also be customized according to user needs, which greatly improves the types and range of configurable topologies and has advantages over a single type of topology in terms of execution performance of different applications.

[0071] In addition, in terms of the global topology integration method of the hierarchical topology structure, multiple topologies can be selected as the hierarchical topology, and sub-networks can be directly connected for communication.

[0072] In an exemplary embodiment, the sub-network includes bridge nodes, and the bridge nodes of different sub-networks are connected via the network links.

[0073] Exemplarily, the nodes in a sub-network can be divided into pier nodes and non-pier nodes. The pier nodes of different sub-networks are connected via network links, and different sub-networks communicate with each other via the pier nodes.

[0074] As an example, the pier node can be selected based on the processing capability of the nodes in the sub-network or the amount of tasks to be processed. For example, if the corner node in the sub-network has high processing capability and a small amount of tasks to be processed, the corner node can be selected as the pier node for cross-sub-network communication.

[0075] It should be noted that the above selection of the corner node in the subnetwork as the pier node is only an example of the present invention. Those skilled in the art can select any node in the subnetwork as the pier node according to actual conditions, and the embodiment of the present invention does not limit this.

[0076] In an exemplary embodiment, the network on chip further includes a bridge node, and the bridge node is located between sub-networks; wherein each of the pier nodes is connected to a bridge node, and a plurality of adjacent pier nodes are connected to the same bridge node.

[0077] In the embodiment of the present invention, different sub-networks can communicate directly through their respective pier nodes, or can add bridge nodes between sub-networks to establish connections between adjacent pier nodes for communication. Those skilled in the art can choose to add bridge nodes according to actual task scenarios.

[0078] Exemplarily, in order to ensure that the number of communication hops between sub-networks is minimized and to reduce contention, a bridge node can be added outside the sub-network to be responsible for the communication between the sub-networks. The nodes connected to the bridge nodes are pier nodes. Each pier node can be connected to a bridge node, and multiple adjacent pier nodes can be connected to the same bridge node.

[0079] In an exemplary embodiment, a plurality of the bridge nodes are connected via the network link; and the selector is connected between adjacent bridge nodes.

[0080] For example, there can be multiple bridge nodes, and multiple bridge nodes can be connected through network links. Selectors are connected between adjacent bridge nodes. The selector can configure the topological structure between sub-networks by controlling the on and off of network links between bridge nodes. For example, the degree of bridge nodes and pier nodes can be set to 5, and redundant links can be connected using selectors.

[0081] As an example, the topology between the bridge nodes between sub-networks can select mesh, torus or tree topologies according to the number of sub-networks, or the topology between the bridge nodes can be customized. The links in the configurable on-chip network topology can be appropriately increased or decreased according to application requirements, which is not limited in this embodiment.

[0082] As an example, heterogeneous sub-networks can be globally integrated to obtain networks on a chip of different sizes. The following further illustrates the global integration of heterogeneous sub-networks through some examples:

[0083] Example 7:

[0084] Fig. 9 is a schematic diagram of a global integration of 2x2 heterogeneous sub-networks according to an embodiment of the present invention, referring to Fig. 9 , the corner nodes of each sub-network are used as pier nodes, and the adjacent pier nodes between sub-networks are connected by a bridge node. Each sub-network can have different topological structures, such as Fig. 9 As shown in the figure, the subnetwork topologies from left to right and from top to bottom are mesh, torus, tree, and cmesh. The bridge nodes between subnetworks are connected by ring-shaped links.

[0085] Fig. 9 The four 4x4 sub-networks are horizontally expanded into an 8x8 on-chip network, which includes four intra-sub-network topologies and one 3x3 inter-sub-network topology.

[0086] Example 8:

[0087] Fig.10 is a schematic diagram of a global integration of 2x4 heterogeneous sub-networks according to an embodiment of the present invention, referring to Fig.10 , the corner nodes of each sub-network are used as pier nodes, and the adjacent pier nodes between sub-networks are connected by a bridge node. Each sub-network can have different topological structures, such as Fig.10 As shown in the figure, the topological structures of the subnetworks from left to right and from top to bottom are mesh, torus, mesh, torus, tree, cmesh, tree, cmesh. The bridge nodes between subnetworks are connected by ring-shaped links.

[0088] Fig.10 The eight 4x4 sub-networks are horizontally expanded into an 8x16 on-chip network, which includes eight intra-sub-network topologies and one 3x5 inter-sub-network topology.

[0089] Example 9:

[0090] Fig.11 is a schematic diagram of a global integration of 4x4 heterogeneous sub-networks according to an embodiment of the present invention, referring to Fig.11 , the corner nodes of each sub-network are used as pier nodes, and the adjacent pier nodes between sub-networks are connected by a bridge node. Each sub-network can have different topological structures, such as Fig.11 As shown in the figure, the topological structures of the subnetworks from left to right and from top to bottom are mesh, torus, mesh, torus, tree, cmesh, tree, cmesh, mesh, torus, mesh, torus, tree, cmesh, tree, cmesh. The bridge nodes between subnetworks are connected by ring-shaped links.

[0091] Fig.11 The 16 4x4 sub-networks are expanded horizontally and vertically into a 16x16 on-chip network, which includes 16 intra-sub-network topologies and one 5x5 inter-sub-network topology.

[0092] That is, global integration is based on the connection of sub-networks. Pier nodes that can communicate across sub-networks can be selected in the sub-networks first, and then bridge nodes that can communicate can be added between the sub-networks, and the bridge nodes and the pier nodes in the corresponding sub-networks are connected. The bridge nodes between sub-networks can be connected by selecting a topological structure. For example, a topological structure such as a mesh structure or a torus structure can be selected for connection, thereby obtaining an expanded on-chip network.

[0093] In an exemplary embodiment, the bridge nodes in the same row or column are connected via the ring link.

[0094] As an example, when horizontally expanding 4 or 8 4x4 configurable sub-network topologies, in order to ensure the minimum number of communication hops between sub-networks and equal support for multiple topologies, the corner nodes of the sub-network can be selected as pier nodes, and bridge nodes can be added outside the pier nodes. The bridge nodes in the same row or column can be connected in a ring-shaped topology.

[0095] In an exemplary embodiment, the topology of the on-chip network includes an intra-subnetwork topology and an inter-subnetwork topology, and the intra-subnetwork topology and the inter-subnetwork topology are configured with different routing algorithms; wherein the inter-subnetwork topology is a topology formed by connecting multiple bridge nodes through the network links.

[0096] Exemplarily, the topology structure of the network on chip may include an intra-subnetwork topology structure and an inter-subnetwork topology structure, and the intra-subnetwork topology structure and the inter-subnetwork topology structure are configured with different routing algorithms.

[0097] Among them, the inter-subnetwork topology structure is a topology structure formed by connecting multiple bridge nodes through network links; the intra-subnetwork topology structure is a topology structure formed by connecting multiple intra-subnetwork nodes through network links.

[0098] In an exemplary embodiment, the bridge node is configured with an inter-sub-network routing algorithm according to the inter-sub-network topology structure.

[0099] Exemplarily, a sub-network routing algorithm may be configured for the bridge nodes between sub-networks according to the topological structure between sub-networks. For example, if the sub-network routing algorithm is a deterministic routing algorithm (such as an xy-order routing algorithm), and the topological structure between sub-networks is a mesh structure, the source address and the target address may be determined according to the mesh structure, and the corresponding coordinates may be configured for each bridge node in the mesh structure.

[0100] As an example, the inter-subnetwork routing algorithm can also perform inter-subnetwork isolation functions.

[0101] In an exemplary embodiment, the sub-network further includes non-pier nodes, and the non-pier nodes in the topological structure within the sub-network and the pier nodes in the topological structure within the sub-network are configured with different routing algorithms.

[0102] Exemplarily, non-pier nodes in the topological structure within a sub-network do not directly participate in cross-network node communications, and pier nodes can participate not only in communications within the sub-network, but also in communications between sub-networks and bridge nodes. Therefore, non-pier nodes and pier nodes can be configured with different routing algorithms.

[0103] In an exemplary embodiment, the non-bridge node is configured with a label relabeling algorithm, and the bridge node is configured with a fusion routing algorithm of the inter-subnetwork routing algorithm and the relabeling algorithm.

[0104] Exemplarily, a label rewriting relabeling algorithm may be configured for non-pier nodes, and a fusion routing algorithm of an inter-subnetwork routing algorithm and a relabeling algorithm may be configured for pier nodes, that is, a relabeling algorithm may be used within a subnetwork.

[0105] As an example, since the routing algorithm determines the routing direction based on the routing number, when the topology changes, the relabeling algorithm will rearrange the routing numbers according to the new topology and synchronously configure them to each routing node. The routing algorithm then routes according to the new numbers to achieve the conversion of physical ID and virtual ID, which facilitates the routing of various topologies, and is simple to implement and low cost.

[0106] The following example further illustrates the routing algorithm within a subnetwork:

[0107] Example 10:

[0108] Fig.12 : is a schematic diagram of routing numbers in a network according to an embodiment of the present invention, where the starting routing number in the sub-network is as follows: Fig.12 As shown in the figure, the digital numbers represent the three dimensions of z, y and x respectively, where y and x are the routing numbers within the network, and z is the routing number between sub-networks. Numbers 000, 003, 030, and 033 can be selected as pier nodes within the sub-network, and the remaining nodes can be selected as non-pier nodes within the sub-network. The source node and the target node can be selected according to the application scenario, and the route can be routed from the source node to the target node according to the number on the node; when the topology is switched, the routing algorithm configured on the node can change the corresponding number to adapt to the new topology, thereby realizing the function of real-time configuration of the topology without changing the routing algorithm.

[0109] In the embodiment of the present invention, a set of routing algorithms can be used within a sub-network to solve the communication problem of multiple routing heterogeneous sub-networks, with low cost and strong feasibility.

[0110] In this embodiment, the configurable on-chip network of the present application may include one or more sub-networks of k-ary and n-dimensional nodes, the nodes of the on-chip network are connected by network links, and selectors are provided between adjacent nodes, and the on-off of all network links within the sub-network and all network links between sub-networks is controlled by the selector to configure the topological structure of the on-chip network. The topological structure of the on-chip network can be flexibly configured according to task requirements, so that the on-chip network has good scalability, thereby solving the problems of large transmission delay and single transmission path in the existing on-chip network topological structure in complex task scenarios.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A configurable on-chip network, characterized in that: The on-chip network includes at least one k-element n-dimensional sub-network of nodes; the nodes of the on-chip network are connected via network links; a selector is connected between two adjacent nodes; The selector is used to configure the topology of the on-chip network by controlling the on-off of all network links of the on-chip network.

2. The network on chip according to claim 1, characterized in that: The sub-network includes bridge nodes, and the bridge nodes of different sub-networks are connected via the network links.

3. The network on chip according to claim 2, characterized in that: The network on chip also includes a bridge node, and the bridge node is located between the sub-networks; wherein each of the pier nodes is connected to a bridge node, and a plurality of adjacent pier nodes are connected to the same bridge node.

4. The network on chip according to claim 3, characterized in that: A plurality of the bridge nodes are connected via the network link; and the selector is connected between adjacent bridge nodes.

5. The network on chip according to any one of claims 1 to 4, characterized in that: The network link includes at least one of the following types: a mesh link, a ring link, and a configurable link.

6. The network on chip according to claim 5, characterized in that: Two ends of the configurable link are respectively connected to different selectors; wherein the configurable link is a cross-node link, and the two ends of the configurable link are configured to cross one or more nodes.

7. The network on chip according to claim 6, characterized in that: The selector is also used to select one of the network links to be connected when multiple network links are connected.

8. The network on chip according to claim 5, characterized in that: The bridge nodes in the same row or column are connected via the ring link.

9. The network on chip according to claim 4, characterized in that: The topological structure of the on-chip network includes an intra-subnetwork topological structure and an inter-subnetwork topological structure, and the intra-subnetwork topological structure and the inter-subnetwork topological structure are configured with different routing algorithms; wherein the inter-subnetwork topological structure is a topological structure formed by connecting multiple bridge nodes through the network links.

10. The network on chip according to claim 9, characterized in that: The bridge node is configured with an inter-sub-network routing algorithm according to the inter-sub-network topology structure.

11. The network on chip according to claim 9, characterized in that: The sub-network also includes non-pier nodes, and the non-pier nodes in the topological structure within the sub-network and the pier nodes in the topological structure within the sub-network are configured with different routing algorithms.

12. The network on chip according to claim 11, characterized in that: The non-bridge nodes are configured with a label relabeling algorithm, and the bridge nodes are configured with a fusion routing algorithm of the inter-subnetwork routing algorithm and the relabeling algorithm.

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