Delay-locked loop, control method thereof and memory

Abstract

The embodiment of the invention provides a delay-locked loop, a control method thereof and a memory. The delay-locked loop includes: a phase detection circuit configured to receive a reference clock signal and a feedback clock signal, and generate an instruction signal by comparing phases of the reference clock signal and the feedback clock signal; the time delay circuit is connected with the phase detection circuit and is configured to receive the instruction signal and output the received instruction signal in a delayed manner; the control circuit is connected with the delay circuit and is configured to receive the instruction signal output in a delayed manner and generate a control signal according to the instruction signal; and the clock adjustment circuit is connected with the control circuit and the phase detection circuit, and is configured to receive the control signal and the reference clock signal, and output a feedback clock signal based on the control signal and the reference clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a delay locked loop and a control method thereof, and a memory. Background Art

[0002] When performing read and write operations, memories such as Dynamic Random Access Memory (DRAM) need to turn on the Delay Lock Loop (DLL) to eliminate the clock offset between the internal clock signal and the external clock signal, thereby ensuring the phase alignment of the external clock signal and the data selection signal (DQS), thereby ensuring the synchronization of the external clock signal and the data selection signal, and achieving high-quality data communication. However, in practical applications, there are still many problems with the delay locked loop that need to be solved. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a delay locked loop and a control method thereof, and a memory. Among them, one aspect of the embodiments of the present disclosure provides a delay locked loop, including:

[0004] a phase detection circuit configured to receive a reference clock signal and a feedback clock signal, and generate a command signal by comparing the phases of the reference clock signal and the feedback clock signal;

[0005] A delay circuit, connected to the phase detection circuit, configured to receive the command signal and delay the received command signal for output;

[0006] A control circuit, connected to the delay circuit, configured to receive the delayed output command signal and generate a control signal according to the command signal;

[0007] The clock adjustment circuit is connected to both the control circuit and the phase detection circuit, and is configured to receive the control signal and the reference clock signal, and output the feedback clock signal based on the control signal and the reference clock signal.

[0008] In some embodiments, the delay circuit is configured to receive the instruction signal and the reference clock signal, generate a clock frequency division signal based on the reference clock signal, and delay the instruction signal by using the clock frequency division signal.

[0009] In some embodiments, the delay circuit includes a frequency division circuit, a clock selection circuit, and an output circuit; wherein:

[0010] The frequency division circuit is configured to receive the reference clock signal and perform frequency division processing on the reference clock signal to generate at least one clock frequency division signal;

[0011] The clock selection circuit is connected to the frequency division circuit and is configured to receive the at least one clock frequency division signal, the reference clock signal and a selection signal, and output a target clock signal based on the selection signal; the target clock signal is one of the at least one clock frequency division signal and the reference clock signal;

[0012] The output circuit is connected to both the clock selection circuit and the phase detection circuit, and is configured to receive the instruction signal and the target clock signal, and delay and output the received instruction signal based on the target clock signal.

[0013] In some embodiments, the frequency division circuit includes a first trigger, or multiple first triggers cascaded in series; the data input terminal of the first trigger is connected to the data complementary output terminal, and the data output terminal of the previous first trigger of two adjacent first triggers is connected to the clock input terminal of the next first trigger.

[0014] In some embodiments, the clock selection circuit includes: a data selector, or a plurality of data selectors in a cascade relationship in series; the control input end of the data selector is configured to receive the selection signal, and the two data input ends of the data selector are respectively configured to receive the reference clock signal and two clock signals of the at least one divided clock signal; the output end of the first data selector of two adjacent data selectors is connected to a data input end of the second data selector; the output end of the last data selector is connected to the input end of the output circuit;

[0015] The data selector is configured to select one of the data input from the two data input terminals and output it from the output terminal according to the selection signal.

[0016] In some embodiments, the select signal is stored in a one-time programmable storage element.

[0017] In some embodiments, the output circuit includes a second flip-flop;

[0018] Among them, the data input end of the second trigger is connected to the phase detection circuit and is configured to receive the instruction signal; the clock input end of the second trigger is connected to the clock selection circuit and is configured to receive the target clock signal; the output end of the second trigger is connected to the control circuit and is configured to delay the received instruction signal and output it to the control circuit according to the target clock signal.

[0019] On the other hand, a memory is provided, comprising: one or more delay locked loops as described in the above embodiments of the present disclosure.

[0020] On the other hand, a control method of a delay locked loop is provided, wherein the delay locked loop includes a phase detection circuit, a delay circuit, a control circuit, and a clock adjustment circuit; wherein the control method includes:

[0021] The phase detection circuit receives a reference clock signal and a feedback clock signal, and generates a command signal by comparing the phases of the reference clock signal and the feedback clock signal;

[0022] The delay circuit receives the command signal and delays the received command signal for output;

[0023] The control circuit receives the delayed output command signal and generates a control signal according to the delayed output command signal;

[0024] The clock adjustment circuit receives the control signal and the reference clock signal, and outputs the feedback clock signal based on the control signal and the reference clock signal.

[0025] In some embodiments, the delay circuit at least receives the instruction signal and delays the output of the received instruction signal, including:

[0026] The delay circuit receives the instruction signal and the reference clock signal, generates a clock frequency division signal based on the reference clock signal, and delays and outputs the instruction signal using the clock frequency division signal.

[0027] In some embodiments, the delay circuit includes a frequency division circuit, a clock selection circuit, and an output circuit;

[0028] The delay circuit receives the instruction signal and the reference clock signal, generates a clock frequency division signal based on the reference clock signal, and delays the instruction signal by using the clock frequency division signal, including:

[0029] The frequency division circuit receives the reference clock signal, and performs frequency division processing on the reference clock signal to generate at least one clock frequency division signal;

[0030] The clock selection circuit receives the at least one clock frequency division signal, the reference clock signal and a selection signal, and outputs a target clock signal based on the selection signal; the target clock signal is one of the at least one clock frequency division signal and the reference clock signal;

[0031] The output circuit receives the instruction signal and the target clock signal, and outputs the received instruction signal with a delay based on the target clock signal.

[0032] The delay phase-locked loop provided in each embodiment of the present disclosure includes a phase detection circuit, a delay circuit, a control circuit, and a clock adjustment circuit; wherein, the received command signal is delayed and outputted through the delay circuit, thereby causing the control circuit to delay outputting the control signal generated thereby, thereby avoiding over-adjustment of the clock adjustment circuit, thereby controlling the update speed of the phase detection circuit, thereby enabling the phase detection circuit to more efficiently compare the phases of the reference clock signal and the feedback clock signal, thereby reducing the waste of the locking time of the delay phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a delay-locked loop provided in one embodiment of the present disclosure;

[0034] Figure 2 A schematic diagram of the structure of another delay-locked loop provided in an embodiment of the present disclosure;

[0035] Figure 3 A signal transmission schematic diagram of a delay-locked loop provided in one embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram of signal transmission between a phase detection circuit, a delay circuit and a control circuit is shown in FIG.

[0037] Figure 5 A schematic diagram of the structure of a frequency division circuit provided in an embodiment of the present disclosure;

[0038] Figure 6 A schematic diagram of the composition structure of another frequency division circuit provided in an embodiment of the present disclosure;

[0039] Figure 7 A schematic diagram of the structure of a clock selection circuit provided in an embodiment of the present disclosure;

[0040] Figure 8 A schematic diagram of the structure of another clock selection circuit provided in an embodiment of the present disclosure;

[0041] Fig. 9 A schematic diagram of the structure of an output circuit provided in an embodiment of the present disclosure;

[0042] Fig.10 The present invention is a flowchart of a control method for a delay-locked loop provided in an embodiment of the present invention.

[0043] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0044] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0046] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0047] The delay locked loop involved in the embodiments of the present disclosure can be used in a variety of memory chips or logic chips. In some embodiments, the memory chip can be a dynamic random access memory chip, etc. In the following embodiments, only the dynamic random access memory is used as an example for description, but it should be understood that the following description of the dynamic random access memory is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure.

[0048] With the development of integrated circuits, clock quality has become a focus of attention. Delay-locked loops are widely used in the control of internal chip clocks, such as clock delay elimination, frequency multiplication and division, and clock correction. The delay-locked loop adjusts the delay time on the variable delay line so that the rising edge of the output clock signal of the delay-locked loop and the reference clock signal (Refelk) are aligned, that is, the phase difference between the two is zero, thereby achieving the purpose of phase locking.

[0049] Exemplary, reference Figure 1 , Figure 1 Schematic diagram of the structure of a delay-locked loop provided in one embodiment of the present disclosure; Figure 1As shown, the delay locked loop 100 includes a phase detection circuit 101, a control circuit 102, a replica circuit 103 and a DLL delay line 104; wherein, an input clock signal (i.e., a reference clock signal (Refclk)) enters the DLL delay line 104, and generates an output clock signal (i.e., a data selection signal (DQS)) after delay and phase adjustment, and the output clock signal generates a feedback clock signal (fbclk) after passing through the replica circuit 103, and the input clock signal and the feedback clock signal are compared in phase in the phase detection circuit 101, and then an instruction signal is output to the control circuit 102, and the control circuit 102 generates an adjustment code (Code) according to the instruction signal, and outputs the adjustment code to the DLL delay line 104 to control the DLL delay line 104 to adjust and realize signal delay adjustment, until the phase of the input clock signal and the feedback clock signal are aligned, thereby completing the phase locking function.

[0050] However, in actual applications, the frequency at which the control circuit 102 outputs the adjustment code to the DLL delay line 104 is too fast, so that the DLL delay line 104 also adjusts the phase very quickly. The DLL delay line 104 outputs the signal to the replica circuit 103, generates a feedback clock signal after passing through the replica circuit 103, and then transmits the feedback clock signal to the phase detection circuit 101. It takes a certain amount of time. In this way, when the feedback clock signal is transmitted to the phase detection circuit 101 and the second comparison is performed, the DLL delay line 104 has adjusted the phase for many times. In other words, the frequency at which the control circuit 102 outputs the adjustment code is higher than the frequency at which the feedback clock signal is output to the phase detection circuit 101. Therefore, before the phase detection circuit 101 performs the next comparison, the control circuit 102 has controlled the DLL delay line 104 to make many adjustments. This causes excessive adjustment of the DLL delay line 104, thereby wasting the locking time of the delay locked loop.

[0051] Based on this, in order to solve one or more of the above problems, another delay phase-locked loop is proposed in the embodiment of the present disclosure, which can control the update speed of the delay signal output by the phase detection circuit by increasing the control of the adjustment code output speed or update speed, thereby aligning the edges of the input clock signal and the output clock signal (here is the feedback clock signal).

[0052] like Figure 2 As shown, Figure 2 FIG. 2 is a schematic diagram of the composition structure of another delay locked loop provided in an embodiment of the present disclosure; the delay locked loop 200 includes:

[0053] The phase detection circuit 201 is configured to receive a reference clock signal and a feedback clock signal, and generate a command signal by comparing the phases of the reference clock signal and the feedback clock signal;

[0054] The delay circuit 202 is connected to the phase detection circuit and is configured to receive the command signal and delay the received command signal for output;

[0055] The control circuit 203 is connected to the delay circuit and is configured to receive the delayed output command signal and generate a control signal according to the command signal;

[0056] The clock adjustment circuit 204 is connected to both the control circuit and the phase detection circuit, and is configured to receive the control signal and the reference clock signal, and output the feedback clock signal based on the control signal and the reference clock signal.

[0057] That is to say, the above-mentioned delay phase-locked loop 200 can output a command signal according to the comparison result of the phase detection circuit 201. The delay circuit 202 delays the output of the received command signal, thereby causing the control circuit 203 to delay the output of the control signal it generates, thereby avoiding excessive adjustment of the clock adjustment circuit 204, and then controlling the update speed of the phase detection circuit, ensuring that the phase detection circuit can correctly compare the phases of the reference clock signal and the feedback clock signal, providing favorable data support for edge alignment, thereby reducing the waste of locking time of the delay phase-locked loop.

[0058] In order to more clearly understand the invention of the present disclosure, the following will be combined with Figures 2 to 9 The composition structure and working principle of the delay phase-locked loop provided by the embodiment of the present disclosure are described in detail.

[0059] like Figure 2 , Figure 3 and Figure 4 As shown, Figure 3 A signal transmission schematic diagram of a delay-locked loop provided in one embodiment of the present disclosure; Figure 4 A schematic diagram of signal transmission between a phase detection circuit, a delay circuit and a control circuit is shown in FIG. Figure 3The delay locked loop 200 also includes a clock buffer (CLK BUF) 205, which is connected to the phase detection circuit 201. In some embodiments, the clock buffer can be, for example, a buffer circuit. The clock buffer 205 is used to receive an input clock signal (CLK) and buffer the received input clock signal to generate a reference clock signal (Refclk). The reference clock signal (Refclk) can be transmitted to the phase detection circuit 201. The phase detection circuit 201 is used to receive the reference clock signal (Refclk) and the feedback clock signal (fbclk) generated by the clock adjustment circuit 204, and perform phase comparison on the reference clock signal (Refclk) and the feedback clock signal (fbclk). Here, the feedback clock signal (fbclk) is the clock signal after the reference clock signal is adjusted by the control circuit 203 and the clock adjustment circuit 204. The phase detection circuit 201 can generate an instruction signal (Lupt, also called a phase detection result signal) according to the comparison result, and transmit the instruction signal (Lupt) to the delay circuit 202. Here, the instruction signal (Lupt) can be used to characterize the relationship or sequence of the phases between the reference clock signal (Refclk) and the feedback clock signal (fbclk), that is, which signal is in front and which signal is in the back of the reference clock signal (Refclk) and the feedback clock signal (fbclk). The instruction signal (Lupt) can specifically characterize the relationship between the two, and provide favorable data support for edge alignment. The delay circuit 202 is used to receive a command signal and delay the output of the received command signal.

[0060] In some embodiments, the delay circuit 202 is configured to receive the instruction signal and the reference clock signal, generate a clock frequency division signal based on the reference clock signal, and delay the instruction signal by using the clock frequency division signal.

[0061] It should be noted that the delay circuit is not only used to receive the command signal, but also used to receive the reference clock signal. After receiving the reference clock signal and the command signal, the delay circuit generates one or more different clock frequency division signals based on the reference clock signal, and then uses different clock frequency division signals to delay the command signal and output it to the control circuit. Here, different clock frequency division signals make the output frequency of the command signal different, that is, the delay output time is different.

[0062] Exemplary, reference Figure 4 ,from Figure 4It can be seen that the phase detection circuit 201 outputs the command signal (Lupt) after performing phase comparison on the reference clock signal (Refclk) and the feedback clock signal (fbclk); one end of the delay circuit 202 receives the command signal (Lupt) and the other end receives the reference clock signal (Refclk), and generates one or more different clock division signals (Refclk_div) based on the reference clock signal (Refclk), and delays the command signal (Lupt) and outputs it to the control circuit 203 according to different clock division signals or reference clock signals.

[0063] It should be noted that, generally speaking, the control circuit 203 outputs the adjustment code for performing a delay operation. At this time, in order to increase the delay, the control codeword needs to increase the count value. However, in some control circuits, due to other reasons (such as the inverted control signals of PMOS and NMOS, etc.), the delay will be increased, and the control codeword needs to decrease the count value.

[0064] In some embodiments, the phase detection circuit 201 can also divide the command signal (Lupt) into a first sub-command signal (DLL_up) and a second sub-command signal (DLL_dn) according to the order of the phases of the reference clock signal (Refclk) and the feedback clock signal (fbclk), wherein the first sub-command signal (DLL_up) is used to characterize that the reference clock signal (Refclk) is before the feedback clock signal (fbclk); the second sub-command signal (DLL_dn) is used to characterize that the feedback clock signal (fbclk) is before the reference clock signal (Refclk). After the phase detection circuit 201 transmits the first sub-command signal (DLL_up) and the second sub-command signal (DLL_dn) to the delay circuit 202, the delay circuit 202 delays the first sub-command signal (DLL_up) or the second sub-command signal (DLL_dn) and outputs it to the control circuit 203 according to actual needs. The control circuit 203 generates adjustment codes with different values, such as 0000 and 0011, according to the different phase relationships represented by the received first sub-command signal (DLL_up) or the second sub-command signal (DLL_dn), and outputs the adjustment codes with different values ​​to the clock adjustment circuit 204. The clock adjustment circuit 204 adjusts the rising edge forward or backward according to the corresponding adjustment code.

[0065] In other embodiments, the sequence relationship between the reference clock signal (Refclk) and the feedback clock signal (fbclk) can also be represented by an instruction signal. Exemplarily, the instruction signal (Lupt) only includes the first sub-instruction signal (DLL_up), that is, whether the first sub-instruction signal (DLL_up) is 0 or 1, to characterize two different results of the sequence of the phases of the reference clock signal (Refclk) and the feedback clock signal (fbclk); for example, the first sub-instruction signal (DLL_up) is 1, which indicates that the reference clock signal (Refclk) is after the feedback clock signal (fbclk); the first sub-instruction signal (DLL_up) is 0, which indicates that the feedback clock signal (fbclk) is after the reference clock signal (Refclk). The control circuit 203 determines whether to increase or decrease the value of the adjustment code (for example, 010 to 011) according to whether the received delayed output first sub-instruction signal (DLL_up) is 0 or 1, that is, which of the reference clock signal (Refclk) and the feedback clock signal (fbclk) comes first or second. Adjustment codes with different values ​​are used to indicate whether to increase or decrease the delay of the signal; the clock adjustment circuit 204 adjusts the rising edge of the signal forward or backward according to the value of the corresponding adjustment code.

[0066] It should be understood that the command signal may include only one signal, such as the first sub-command signal, or may include two signals, such as the first sub-command signal and the second sub-command signal (eg Figure 4 As shown), the specific selection can be set according to the actual circuit situation. For ease of understanding, here and below, the instruction signal only includes the first sub-instruction signal (DLL_up) as an example for explanation.

[0067] Exemplarily, after receiving the instruction signal (the first sub-instruction signal (DLL_up)), the control circuit 203 generates an adjustment code with different values ​​according to whether the first sub-instruction signal (DLL_up) is 0 or 1; exemplarily, the first sub-instruction signal (DLL_up) received by the control circuit 203 is 1, which means that the value of the adjustment code is increased. After the adjustment code with the increased value is output to the clock adjustment circuit 204, the clock adjustment circuit 204 moves the rising edge of the reference clock signal forward or backward according to the value of the adjustment code. In this way, the phases of the reference clock signal and the feedback clock signal are aligned, and the output frequencies match, thereby reducing the waste of the locking time of the delay locked loop.

[0068] It should be noted that after the phase detection circuit 201 passes the command signal (Lupt) through the delay circuit 202, the delay circuit 202 delays (or reduces the frequency) the command signal through different frequencies such as 2-division or 4-division, so that the frequency of the delayed command signal output to the control circuit becomes slower, and the speed or frequency of the control circuit 203 generating the adjustment code becomes slower, thereby matching the delay of the clock adjustment circuit 204.

[0069] Combine the following Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 The working principle of the delay circuit is explained in detail. Figure 5 A schematic diagram of the structure of a frequency division circuit provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of the composition structure of another frequency division circuit provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of the structure of a clock selection circuit provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of the structure of another clock selection circuit provided in an embodiment of the present disclosure; Fig. 9 The present invention is a schematic diagram of the structure of an output circuit provided in an embodiment of the present invention.

[0070] In some specific embodiments, reference Figure 4 , the delay circuit 202 includes a frequency division circuit 501, a clock selection circuit 502, and an output circuit 503; wherein:

[0071] The frequency division circuit 501 is configured to receive the reference clock signal, and perform frequency division processing on the reference clock signal to generate at least one clock frequency division signal;

[0072] The clock selection circuit 502 is connected to the frequency division circuit and is configured to receive the at least one clock frequency division signal, the reference clock signal and a selection signal, and output a target clock signal based on the selection signal; the target clock signal is one of the at least one clock frequency division signal and the reference clock signal;

[0073] The output circuit 503 is connected to both the clock selection circuit and the phase detection circuit, and is configured to receive the instruction signal and the target clock signal, and delay the received instruction signal and output it based on the target clock signal.

[0074] The frequency division circuit 501 can output the reference clock signal according to a certain frequency division, and its function is to divide a high frequency signal into a low frequency signal, or to divide a low frequency signal into a lower frequency signal. In other words, the frequency multiple of the signal processed by the frequency division circuit becomes smaller, and the period multiple becomes larger. Here, the frequency division circuit 501 performs at least one frequency division process on the received reference clock signal (Refclk), and outputs at least one clock frequency division signal after the frequency division process, the frequency of the frequency division clock signal is less than the frequency of the reference clock signal, and the period of the frequency division clock signal is greater than the period of the reference clock signal.

[0075] In some specific embodiments, the frequency division circuit 501 includes a first trigger, or a plurality of first triggers cascaded in series; the data input terminal of the first trigger is connected to the data complementary output terminal, and the data output terminal of the previous first trigger of two adjacent first triggers is connected to the clock input terminal of the next first trigger.

[0076] Exemplary, reference Figure 5 The frequency division circuit 501 includes a first trigger 5011, the first

[0078] The trigger 5011 includes a clock input terminal C, a data input terminal D, and a data complementary output terminal and data output terminal Q; wherein the clock input terminal C of the first trigger is used to receive a reference clock signal (Refclk), the first

[0080] The data input terminal D of a trigger is complementary to the data output terminal of the first trigger. The data output terminal Q of the first trigger is used to output the clock frequency division signal. The first trigger 5011 also includes a reset input terminal R, which is used to receive an indication signal, and the indication signal is used to indicate whether to perform a reset operation on the first trigger 5011.

[0081] Exemplary, reference Figure 6 The frequency division circuit 501 includes three first triggers in a cascade relationship, which are the first first trigger 5011, the second first trigger 5011 and the third first trigger 5011 which are closest to the total input terminal. The first first trigger 5011, the second first trigger 5011 and the third first trigger 5011 all include a clock input terminal C, a data input terminal D, a data complementary-output terminal Q and a data output terminal Q; wherein the clock input terminal C of the first first trigger 5011 is used to receive the reference clock signal Refclk, and the data input terminal D of the first first trigger 5011 is connected to the first

[0082] —The data complementary output terminal Q of the first flip-flop 5011 is connected, the data output terminal Q of the first first flip-flop 5011 is connected to the clock input terminal C of the second first flip-flop 5011, and the second first flip-flop 5011 is connected

[0083] —’s data input terminal D is connected to the data complementary output terminal Q of the second first trigger 5011, the data output terminal Q of the second first trigger 5011 is connected to the clock input terminal C of the third first trigger 5011, the data input terminal D of the third first trigger 5011 is connected to the data complementary output terminal Q of the third first trigger 5011, and the data output terminal Q of the third first trigger 5011 is used to output a clock division signal.

[0084] It should be noted that the data output terminals Q of the first first trigger 5011, the second first trigger 5011, and the third first trigger 5011 are respectively used to output different clock division signals (Refclk_div). For example, the data output terminal Q of the first first trigger 5011 is used to output the first clock division signal (Refclk_div2) after the first division q0, the data output terminal Q of the second first trigger 5011 is used to output the second clock division signal (Refclk_div4) after the second division q1, and the data output terminal Q of the third first trigger 5011 is used to output the third clock division signal (Refclk_div8) after the third division q2.

[0085] In some specific embodiments, the first clock division signal (Refclk_div2) is a clock signal divided by 2 of the reference clock signal (Refclk), the second clock division signal (Refclk_div4) is a clock signal divided by 2 of the first clock division signal (Refclk_div2), and the third clock division signal (Refclk_div8) is a clock signal divided by 2 of the second clock division signal (Refclk_div4); in this way, the division circuit 501 can perform three division processes on the received reference clock signal (Refclk), and output three different clock division signals after the division processes.

[0086] It should be noted that the shorter the clock period of the signal, the higher the frequency. Here, the clock period of the reference clock signal is the shortest, and the clock periods of the first clock frequency division signal, the second clock frequency division signal, and the third clock frequency division signal gradually increase in sequence. Specifically, the clock period of the third clock frequency division signal is twice the clock period of the second clock frequency division signal; the clock period of the second clock frequency division signal is twice the clock period of the first clock frequency division signal; the clock period of the first clock frequency division signal is twice the clock period of the reference clock signal. In other words, the frequency of the reference clock signal is the largest, and the frequencies of the first clock frequency division signal, the second clock frequency division signal, and the third clock frequency division signal gradually decrease in sequence. The frequency of the reference clock signal is twice the frequency of the first clock frequency division signal; the clock period of the first clock frequency division signal is twice the clock period of the second clock frequency division signal; the clock period of the second clock frequency division signal is twice the clock period of the third clock frequency division signal.

[0087] It should be understood that Figure 6 Only the three first triggers required for frequency division by 2, by 4, and by 8 are shown. Figure 6 The number of first triggers is not used to limit the number of first triggers included in the frequency division circuit 501 in the present disclosure. In actual applications, the number of first triggers can be set according to actual conditions. For example, when 2-division or 4-division is required, the number of first triggers can be 2; when 2-division, 4-division, 8-division, or 16-division is required, the number of first triggers can be 4, and so on.

[0088] In some embodiments, the first trigger of the plurality of first triggers further includes a reset input terminal, and the reset input terminal is used to receive an indication signal and perform a reset operation. Figure 6 Among the three first triggers 5011, the first first trigger 5011 may also include a reset input terminal R for receiving an indication signal, wherein the indication signal is used to indicate whether a reset operation is performed on the first first trigger 5011 in the frequency dividing circuit 501.

[0089] In actual applications, after the frequency division circuit 501 divides the reference clock signal (Refclk), multiple different clock division signals (Refclk_div) are transmitted to the clock selection circuit 502. The clock selection circuit 502 is used to receive multiple different clock division signals and a reference clock signal and a selection signal (TMF, Test Mode Fuse), and select one of the multiple different clock division signals (Refclk_div) and the reference clock signal (Refclk) according to the selection signal, and output the selected signal as the target clock signal (pdclk) to the output circuit 503.

[0090] In some embodiments, the clock selection circuit 502 includes: a data selector (Mux, Multiplexer), or a plurality of data selectors in a cascade relationship in series; the control input end of the data selector is configured to receive the selection signal, and the two data input ends of the data selector are respectively configured to receive the reference clock signal and two clock signals of the at least one divided clock signal; the output end of the first data selector of two adjacent data selectors is connected to a data input end of the second data selector; the output end of the last data selector is connected to the input end of the output circuit;

[0091] The data selector is configured to select one of the data input from the two data input terminals and output it from the output terminal according to the selection signal.

[0092] Exemplarily, in some specific embodiments, the clock selection circuit 502 may include a data selector, which includes multiple control input terminals, multiple data input terminals and a signal output terminal; wherein the control input terminal is used to receive a multi-bit selection signal, the multiple data input terminals are used to receive a reference clock signal (Refclk) and the multiple data input terminals are used to receive the data output terminal Q of the first trigger to output the clock division signal (Refclk_div), and the signal output terminal is used to output the target clock signal (pdclk).

[0093] Exemplary, reference Figure 7 The clock selection circuit 502 may include a data selector 601, which includes two control input terminals, four data input terminals and a signal output terminal; wherein the control input terminal is used to receive a selection signal (TMF_PD_CLKMUX0, TMF_PD_CLKMUX1), one data input terminal is used to receive a reference clock signal (Refclk), and the other three data input terminals are used to receive clock division signals (such as Refclk_div2, Refclk_div4, Refclk_div8) output by the data output terminals Q of the three first triggers, and the signal output terminal is used to output a target clock signal (pdclk).

[0094] In other specific embodiments, the clock selection circuit 502 may include multiple cascaded data selectors, which include a control input terminal, two data input terminals and a signal output terminal; wherein the control input terminal is used to receive a one-bit selection signal, the two data input terminals are used to receive a reference clock signal (Refclk) and the multiple data input terminals are used to receive two of the data output terminals Q output clock division signals (Refclk_div) of the first trigger, and the signal output terminal is used to output the target clock signal (pdclk).

[0095] Exemplary, reference Figure 8 , the clock selection circuit 502 may include three data selectors (such as the first data selector 701, the second data selector 702, and the third data selector 703) in a cascade relationship in series. The three data selectors can select and transmit the signals received by multiple receiving ends to a unique common data channel. In the process of transmitting multiple data or signals, any one of the selected signals can be output as the target clock signal (pdclk) as needed (such as the indication of the selection signal). Here, each of the three data selectors includes multiple control input terminals, two data input terminals, and a signal output terminal. The three control input terminals corresponding to the three data selectors are respectively used to receive three different selection signals (such as TMF_PD_CLKMUX <0> 、TMF_PD_CLKMUX <1> 、TMF_PD_CLKMUX <2> ), the three data input terminals corresponding to the three data selectors are respectively used to receive three different clock frequency division signals (such as q0, q1, q2 or Refclk_div2, Refclk_div4, Refclk_div8), and the signal output terminal of the last data selector is used to output a selected signal (one of the different clock frequency division signals or the reference clock signal) as the target clock signal (pdclk). Here, the output terminal of the first data selector 701 is connected to a data input terminal of the second data selector 702; the output terminal of the second data selector 702 is connected to a data input terminal of the third data selector 703; the output terminal of the third data selector 703 is connected to the input terminal of the output circuit.

[0096] It should be noted that Figure 7 and Figure 8 Only several numbers and composition forms of data selectors in the clock selection circuit 502 are shown. These composition forms are not used to limit the number and composition form of data selectors in the clock selection circuit 502 in the present disclosure. In actual applications, the number and composition form of data selectors in the clock selection circuit 502 can be set according to actual conditions. For example, when 2-frequency division or 4-frequency division is required, the number of data selectors in the clock selection circuit 502 can be one or three cascaded data selectors.

[0097] In some embodiments, the select signal is stored in a one-time programmable storage element.

[0098] In some specific embodiments, the one-time programmable memory element may be a fuse cell or an anti-fuse cell.

[0099] In some embodiments, reference Fig. 9, the output circuit 503 may include a second trigger; wherein the data input terminal of the second trigger is connected to the phase detection circuit and is configured to receive the instruction signal; the clock input terminal of the second trigger is connected to the clock selection circuit and is configured to receive the target clock signal; the output terminal of the second trigger is connected to the control circuit and is configured to delay the received instruction signal and output it to the control circuit according to the target clock signal.

[0100] In practical applications, the second trigger can be the same as or different from the first trigger. Fig. 9 The second trigger includes a data input terminal D, a clock input terminal C and an output terminal Q; wherein the data input terminal D is used to receive a command signal (Lupt), the clock input terminal C is used to receive a target clock signal (pdclk), and the output terminal Q delays the received command signal (Lupt) and outputs it to the control circuit 203 according to the target clock signal (pdclk).

[0101] As mentioned above, the delayed output instruction signal may include one sub-instruction signal or two sub-instruction signals. Based on this, the output end of the second trigger may include one output interface or two output interfaces. In other words, when the instruction signal only includes the first sub-instruction signal (DLL_up), the output end of the second trigger includes only one output interface, which is used to output the first sub-instruction signal (DLL_up); when the instruction signal includes the first sub-instruction signal (DLL_up) and the second sub-instruction signal (DLL_dn), the output end of the second trigger includes two output interfaces, wherein one output interface is used to output the first sub-instruction signal (DLL_up) and the other output interface is used to output the second sub-instruction signal (DLL_dn).

[0102] In this way, by selecting different frequencies (clock division signals), the delay circuit delays the instruction signal to different degrees, and outputs the instruction signals with different delays to the control circuit. The control circuit outputs different adjustment codes according to the different delayed instruction signals, so that the generation and control of the adjustment code will be reduced in frequency, so that the reference clock signal matches the clock period of the feedback signal.

[0103] In some embodiments, reference Figure 3 , the clock adjustment circuit 204 includes: a delay adjustment circuit 2041 and a copy adjustment circuit 2042;

[0104] The delay adjustment circuit 2041 is connected to the control circuit, and is configured to receive the reference clock signal and the control signal, and perform duty cycle adjustment and delay processing on the reference clock signal, and output an adjusted clock signal;

[0105] The replica adjustment circuit 2042 is connected to both the delay adjustment circuit and the phase detection circuit, and is configured to replicate the duty cycle adjustment and delay processing of the data selection signal (DQS) on the transmission path, and output a feedback clock signal;

[0106] The sum of the delay amount of the delay adjustment circuit and the delay amount of the replica adjustment circuit is equal to an integer multiple of clock cycles of the reference clock signal.

[0107] In some embodiments, the delay adjustment circuit 2041 includes: a first duty cycle correction circuit (DCC0), a fine adjustment delay circuit (CDL), a coarse adjustment delay circuit (FDL), and a second duty cycle correction circuit (DCC1);

[0108] Among them, the first duty cycle correction circuit is configured to adjust the first duty cycle of the reference clock signal; the fine adjustment delay circuit is connected to the first duty cycle correction circuit and the control circuit, and is configured to perform a first delay processing on the reference clock signal; the coarse adjustment delay circuit is connected to the fine adjustment delay circuit and the control circuit, and is configured to perform a second delay processing on the reference clock signal; the second duty cycle correction circuit is connected to the coarse adjustment delay circuit and the replica circuit, and is configured to adjust the second duty cycle of the reference clock signal.

[0109] In some embodiments, the delay adjustment circuit 2041 may also include a frequency division circuit (DIV), a driving circuit (DRV), a service termination circuit (TSAC), and the replication adjustment circuit 2042 also includes a frequency division circuit (DIV) and a driving circuit (DRV).

[0110] In some embodiments, the replica adjustment circuit 2042 further includes a frequency division circuit (DIV), a first duty cycle correction circuit (DCC0), a fine adjustment delay circuit (CDL), a coarse adjustment delay circuit (FDL), a second duty cycle correction circuit (DCC1), a driving circuit (DRV) and a replica circuit (Replica); wherein the delay amount of the replica circuit is substantially equal to the delay amount of the data strobe signal (DQS) on the path outside the delay locked loop. The frequency division circuit has been described above and will not be described here; the application of the driving circuit (DRV) and the service terminal circuit (TSAC) in the relevant technology is relatively mature and will not be described here.

[0111] Based on this, in each embodiment of the present disclosure, the received command signal is delayed and outputted through a delay circuit, so that the control circuit delays the output of the control signal it generates, thereby avoiding over-adjustment of the clock adjustment circuit, thereby controlling the update speed of the phase detection circuit, and ensuring that the phase detection circuit can correctly compare the phases of the reference clock signal and the feedback clock signal, thereby reducing the waste of locking time of the delay phase-locked loop.

[0112] According to another aspect of the embodiments of the present disclosure, a memory is provided, wherein the memory includes one or more delay locked loops as described in the foregoing embodiments.

[0113] According to another aspect of the present disclosure, a control method for a delay-locked loop is provided, wherein the delay-locked loop includes a phase detection circuit, a delay circuit, a control circuit, and a clock adjustment circuit; wherein, Fig.10 ; Fig.10 The present invention is a schematic diagram of a control method for a delay-locked loop according to an embodiment of the present invention; the control method comprises the following steps:

[0114] Step S1001: the phase detection circuit receives a reference clock signal and a feedback clock signal, and generates a command signal by comparing the phases of the reference clock signal and the feedback clock signal;

[0115] Step S1002: the delay circuit receives the command signal and delays the received command signal for output;

[0116] Step S1003: the control circuit receives the delayed output command signal, and generates a control signal according to the delayed output command signal;

[0117] Step S1004: the clock adjustment circuit receives the control signal and the reference clock signal, and outputs the feedback clock signal based on the control signal and the reference clock signal.

[0118] In some embodiments, the delay circuit at least receives the instruction signal and delays the output of the received instruction signal, including:

[0119] The delay circuit receives the instruction signal and the reference clock signal, generates a clock frequency division signal based on the reference clock signal, and delays and outputs the instruction signal using the clock frequency division signal.

[0120] In some embodiments, the delay circuit includes a frequency division circuit, a clock selection circuit, and an output circuit;

[0121] The delay circuit receives the instruction signal and the reference clock signal, generates a clock frequency division signal based on the reference clock signal, and delays the instruction signal by using the clock frequency division signal, including:

[0122] The frequency division circuit receives the reference clock signal, and performs frequency division processing on the reference clock signal to generate at least one clock frequency division signal;

[0123] The clock selection circuit receives the at least one clock frequency division signal, the reference clock signal and a selection signal, and outputs a target clock signal based on the selection signal; the target clock signal is one of the at least one clock frequency division signal and the reference clock signal;

[0124] The output circuit receives the instruction signal and the target clock signal, and outputs the received instruction signal with a delay based on the target clock signal.

[0125] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0126] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0127] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0128] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A delay-locked loop, characterized in that: include: a phase detection circuit configured to receive a reference clock signal and a feedback clock signal, and generate a command signal by comparing the phases of the reference clock signal and the feedback clock signal; A delay circuit, connected to the phase detection circuit, configured to receive the command signal and delay the received command signal for output; A control circuit, connected to the delay circuit, configured to receive the delayed output command signal and generate a control signal according to the command signal; The clock adjustment circuit is connected to both the control circuit and the phase detection circuit, and is configured to receive the control signal and the reference clock signal, and output the feedback clock signal based on the control signal and the reference clock signal.

2. The delay locked loop according to claim 1, characterized in that: The delay circuit is configured to receive the instruction signal and the reference clock signal, generate a clock frequency division signal based on the reference clock signal, and delay the instruction signal by using the clock frequency division signal.

3. The delay locked loop according to claim 2, characterized in that: The delay circuit includes a frequency division circuit, a clock selection circuit, and an output circuit; wherein: The frequency division circuit is configured to receive the reference clock signal and perform frequency division processing on the reference clock signal to generate at least one clock frequency division signal; The clock selection circuit is connected to the frequency division circuit and is configured to receive the at least one clock frequency division signal, the reference clock signal and a selection signal, and output a target clock signal based on the selection signal; the target clock signal is one of the at least one clock frequency division signal and the reference clock signal; The output circuit is connected to both the clock selection circuit and the phase detection circuit, and is configured to receive the instruction signal and the target clock signal, and delay and output the received instruction signal based on the target clock signal.

4. The delay locked loop according to claim 3, characterized in that: The frequency division circuit includes a first trigger, or multiple first triggers connected in series in a cascade relationship; the data input terminal of the first trigger is connected to the data complementary output terminal, and the data output terminal of the previous first trigger of two adjacent first triggers is connected to the clock input terminal of the next first trigger.

5. The delay locked loop according to claim 3, characterized in that: The clock selection circuit comprises: a data selector, or a plurality of data selectors connected in series in a cascade relationship; a control input end of the data selector is configured to receive the selection signal, and two data input ends of the data selector are respectively configured to receive a reference clock signal and two clock signals of the at least one frequency-divided clock signal; an output end of a preceding data selector of two adjacent data selectors is connected to a data input end of a succeeding data selector; and an output end of the last data selector is connected to an input end of the output circuit; The data selector is configured to select one of the data input from the two data input terminals and output it from the output terminal according to the selection signal.

6. The delay locked loop according to claim 3, characterized in that: The selection signal is stored in a one-time programmable storage element.

7. The delay locked loop according to claim 3, characterized in that: The output circuit includes a second trigger; Among them, the data input end of the second trigger is connected to the phase detection circuit and is configured to receive the instruction signal; the clock input end of the second trigger is connected to the clock selection circuit and is configured to receive the target clock signal; the output end of the second trigger is connected to the control circuit and is configured to delay the received instruction signal and output it to the control circuit according to the target clock signal.

8. A memory, characterized in that: include: One or more delay locked loops as claimed in any one of claims 1 to 7.

9. A control method for a delay-locked loop, characterized in that: The delay locked loop includes a phase detection circuit, a delay circuit, a control circuit, and a clock adjustment circuit; wherein the control method includes: The phase detection circuit receives a reference clock signal and a feedback clock signal, and generates a command signal by comparing the phases of the reference clock signal and the feedback clock signal; The delay circuit receives the command signal and delays the received command signal for output; The control circuit receives the delayed output command signal and generates a control signal according to the command signal; The clock adjustment circuit receives the control signal and the reference clock signal, and outputs the feedback clock signal based on the control signal and the reference clock signal.

10. The control method according to claim 9, characterized in that: The delay circuit at least receives the instruction signal and delays the received instruction signal for output, comprising: The delay circuit receives the instruction signal and the reference clock signal, generates a clock frequency division signal based on the reference clock signal, and delays and outputs the instruction signal using the clock frequency division signal.

11. The control method according to claim 10, characterized in that: The delay circuit includes a frequency division circuit, a clock selection circuit, and an output circuit; The delay circuit receives the instruction signal and the reference clock signal, generates a clock frequency division signal based on the reference clock signal, and delays the instruction signal by using the clock frequency division signal, including: The frequency division circuit receives the reference clock signal, and performs frequency division processing on the reference clock signal to generate at least one clock frequency division signal; The clock selection circuit receives the at least one clock frequency division signal, the reference clock signal and a selection signal, and outputs a target clock signal based on the selection signal; the target clock signal is one of the at least one clock frequency division signal and the reference clock signal; The output circuit receives the instruction signal and the target clock signal, and outputs the received instruction signal with a delay based on the target clock signal.

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