Method for multiplexing on-chip information and related device

Abstract

The invention relates to the field of data processing, in particular to an on-chip information multiplexing method and a related device. The method comprises the following steps: acquiring on-chip information generated by each module in the system on chip, and storing the on-chip information in a first-level first-in first-out (FIFO) buffer matched with each module; according to a shared scheduling rule, on-chip information is transmitted to a second-level FIFO buffer from a first-level FIFO buffer which is temporarily stored at present through a first-level polling arbiter; the second-stage FIFO buffer is a public storage area shared by a plurality of modules; transmitting the on-chip information from the secondary FIFO buffer to an on-chip logic analyzer through a secondary polling arbiter; and processing the on-chip information through the on-chip logic analyzer so as to realize multiplexing processing of the on-chip information generated by the plurality of modules. According to the method, multiplexing of the on-chip information can be realized, the debugging and tracking efficiency of the on-chip system is effectively improved, and meanwhile, the complexity and the cost of the system are reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to an on-chip information multiplexing method and related devices. Background Art

[0002] System on Chip (SoC) is an integrated circuit that integrates multiple functional modules that work together to achieve a complete system function. The system on chip integrates tasks that are usually completed by multiple independent modules into the same circuit, thereby improving performance, reducing power consumption and cost, and reducing the size of the overall system.

[0003] In the related technology, it is necessary to manage and transmit the debugging information (Debug) and tracing information (Trace) generated by each module in the system on chip. Debug information and tracing information usually need to be transmitted at the same time, so they will compete for the bandwidth resources of the same bus. This competition may cause transmission delays for some information, affecting the real-time performance of debugging and tracing. Since the transmission requirements of debugging and tracing information may vary greatly at different times, the bus bandwidth cannot be fully utilized in certain time periods, resulting in a waste of resources.

[0004] Therefore, it is urgent to design a technical solution to solve at least one of the above technical problems. Summary of the invention

[0005] In order to solve the technical problems existing in the prior art, the present application provides an on-chip information multiplexing method and related devices, which are used to realize the multiplexing of on-chip information through a multi-level buffer, a polling arbitrator, and a priority polling mechanism in the on-chip system, thereby effectively improving the debugging and tracing efficiency of the on-chip system and reducing the system complexity and cost.

[0006] In a first aspect, an embodiment of the present application provides a method for multiplexing on-chip information, the method being applied to a system on chip including multiple modules, the method comprising: Acquire on-chip information generated by each module in the on-chip system, and store it in a first-in-first-out FIFO buffer matching each module; the on-chip information at least includes: debugging information and / or tracing information; According to the shared scheduling rule, the on-chip information is respectively transmitted from the respective currently temporarily stored first-level FIFO buffers to the second-level FIFO buffers through the first-level polling arbiter; the second-level FIFO buffer is a common storage area shared by multiple modules; transmitting the on-chip information from the secondary FIFO buffer to an on-chip logic analyzer via a secondary polling arbiter; The on-chip information is processed by the on-chip logic analyzer to implement multiplexing processing of on-chip information generated by multiple modules.

[0007] In a second aspect, an embodiment of the present application provides an on-chip information multiplexing device, which is applied to an on-chip system including multiple modules, and the device includes at least the following units: A first-level first-in-first-out FIFO buffer is configured to obtain and store on-chip information generated by each module in the on-chip system; the on-chip information at least includes: debugging information and / or tracing information; A first-level polling arbiter is configured to transfer the on-chip information from the first-level FIFO buffers currently temporarily stored to the second-level FIFO buffers according to the shared scheduling rules; the second-level FIFO buffers are common storage areas shared by multiple modules; a secondary polling arbiter configured to transfer the on-chip information from the secondary FIFO buffer to an on-chip logic analyzer according to a static scheduling rule; The on-chip logic analyzer is configured to process the on-chip information to implement multiplexing processing of the on-chip information generated by multiple modules.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: at least one processor, memory, and input-output unit; The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the on-chip information multiplexing method of the first aspect.

[0009] According to a fourth aspect, a computer-readable storage medium is provided, which includes instructions. When the instructions are executed on a computer, the computer executes the on-chip information multiplexing method according to the first aspect.

[0010] The beneficial effect of the present application is: providing a method for multiplexing on-chip information and a related device. In this technical solution, first, the on-chip information generated by each module in the on-chip system is obtained and stored in a first-level first-out FIFO buffer matching each module; the on-chip information at least includes: debugging information and / or tracing information. Then, according to the shared scheduling rules, the on-chip information is transferred from the first-level FIFO buffer currently temporarily stored to the second-level FIFO buffer through a first-level polling arbitrator; the second-level FIFO buffer is a common storage area shared by multiple modules. Then, the on-chip information is transferred from the second-level FIFO buffer to the on-chip logic analyzer through a second-level polling arbitrator. Finally, the on-chip information is processed by the on-chip logic analyzer to realize the multiplexing processing of the on-chip information generated by multiple modules.

[0011] The technical solution of the present application, the multiplexing of on-chip information not only solves the problems of resource competition, increased chip area, increased system complexity and performance bottlenecks, but can also be easily expanded by adding more modules and corresponding FIFO buffers without significantly increasing the design complexity. The polling arbitrator can dynamically adjust the order of information transmission according to different needs and priorities, thereby improving the flexibility of the system. The design of the FIFO buffer and the polling arbitrator can ensure the integrity and order of information and reduce data loss and errors. The technical solution of the present application, through the multiplexing of on-chip information by the multi-level buffer in the on-chip system and the polling arbitrator, effectively improves the debugging and tracing efficiency of the on-chip system, while reducing system complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flowchart of a method for multiplexing on-chip information according to an embodiment of the present application; Figure 2 It is a schematic diagram of the principle of a system on a chip according to an embodiment of the present application; Figure 3 is a schematic diagram of the structure of a system on chip according to an embodiment of the present application; Figure 4 It is a structural schematic diagram of an on-chip information multiplexing method and device according to an embodiment of the present application; Figure 5 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application; Figure 6 It is a structural schematic diagram of a medium device according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0014] A system on chip is an integrated circuit that integrates multiple functional modules that work together to achieve a complete system function. The system on chip integrates tasks that are usually completed by multiple independent modules into the same circuit, thereby improving performance, reducing power consumption and cost, and reducing the size of the overall system.

[0015] In the related technology, it is necessary to manage and transmit the debugging information (Debug) and tracing information (Trace) generated by each module in the system on chip. Debug information and tracing information usually need to be transmitted at the same time, so they will compete for the bandwidth resources of the same bus. This competition may cause transmission delays for some information, affecting the real-time performance of debugging and tracing. Since the transmission requirements of debugging and tracing information may vary greatly at different times, the bus bandwidth cannot be fully utilized in certain time periods, resulting in a waste of resources.

[0016] In addition, the prior art usually uses two independent buses to transmit debugging information and tracing information respectively. Although this method avoids competition between information to a certain extent, it increases the physical area of ​​the chip, especially the wiring and connection parts of the bus. Although adding an independent bus improves the independence and reliability of information transmission, it also increases the manufacturing cost and debugging complexity of the chip, especially in high-density integrated circuits, where the increase in area is particularly significant. In addition, since debugging and tracing information are transmitted on different buses, delays in information merging and processing may occur, especially when the amount of information is large. This delay may affect the performance of the overall system. When a multi-bus system processes information requests, the response time may increase due to bus arbitration and switching, affecting the real-time performance of the system.

[0017] Therefore, it is urgent to design a technical solution to solve at least one of the above technical problems.

[0018] In order to solve at least one technical problem in the related art, an embodiment of the present application provides an on-chip information multiplexing method and a related device.

[0019] In the technical solution provided by the present application, for the resource competition problem in the related art, the debugging information and tracking information generated by each module are first stored in their respective first-level FIFO buffers. In this way, each module has an independent buffer, avoiding direct competition for bus bandwidth. Through the first-level polling arbitrator and the second-level polling arbitrator, the information transmission of each module can be managed and scheduled in an orderly manner. This arbitration mechanism ensures that the information of each module is transmitted at the right time, avoiding delays and bottlenecks caused by resource competition.

[0020] Secondly, to address the problem of increased chip area, multiple modules share a secondary FIFO buffer as a common storage area, rather than setting up independent buses and buffers for each module. This greatly reduces the chip area occupied, especially for high-density integrated circuits. Through the FIFO buffer and polling arbitrator, the interconnection structure between modules can be simplified, reducing wiring complexity and further saving chip area.

[0021] Thirdly, each module has an independent first-level FIFO buffer. This modular design makes the control logic of the system simpler and more intuitive. During debugging and testing, the FIFO buffer of each module can be verified separately, rather than the entire complex bus system. Through the shared polling arbitrator, the information transmission of different modules can be uniformly managed and scheduled, reducing the complexity brought by multiple independent buses. This unified scheduling mechanism also facilitates the design and maintenance of the system.

[0022] Finally, for the performance bottleneck problem, the FIFO buffer can temporarily store information, reduce the instantaneous pressure on the bus bandwidth, and reduce transmission delays. The polling arbitrator ensures that information is transmitted at the right time, avoiding long waits. The shared secondary FIFO buffer and polling arbitrator can quickly respond to information requests, reducing the time for bus switching and arbitration. This makes the system more efficient and real-time when processing information requests. The on-chip logic analyzer can centrally process the on-chip information transmitted from the secondary FIFO buffer, optimize the data processing flow, and improve the performance of the overall system.

[0023] In the technical solution of the present application, the multiplexing of on-chip information not only solves the problems of resource competition, increased chip area, increased system complexity and performance bottlenecks, but can also be easily expanded by adding more modules and corresponding FIFO buffers without significantly increasing the design complexity. The polling arbitrator can dynamically adjust the order of information transmission according to different needs and priorities, thereby improving the flexibility of the system. The design of the FIFO buffer and the polling arbitrator can ensure the integrity and order of information and reduce data loss and errors. In the technical solution of the present application, the on-chip information multiplexing method effectively improves the debugging and tracking efficiency of the on-chip system by reasonably managing and scheduling information transmission, while reducing system complexity and cost.

[0024] The multiplexing scheme of on-chip information provided in the embodiments of the present application can also be executed by an electronic device, which can be a server, a server cluster, or a cloud server. The electronic device can also be a terminal device such as a mobile phone, a computer, a tablet computer, a wearable device, or a dedicated device (such as a dedicated terminal device with a multiplexing method system for on-chip information). These electronic devices can also be equipped with the chips introduced in the above embodiments. Alternatively, these electronic devices can also be installed with a service program for executing the multiplexing scheme of on-chip information.

[0025] Figure 1 A schematic diagram of a flow chart of a method for multiplexing on-chip information provided in an embodiment of the present application, such as Figure 1 As shown, the method comprises the following steps: 101, obtaining on-chip information generated by each module in the on-chip system, and storing it in a first-in-first-out FIFO buffer matching each module; 102, according to the shared scheduling rule, the on-chip information is respectively transferred from the respective currently temporarily stored first-level FIFO buffers to the second-level FIFO buffers through the first-level polling arbitrator; 103, transmitting the on-chip information from the secondary FIFO buffer to the on-chip logic analyzer through the secondary polling arbitrator; 104 , processing the on-chip information by the on-chip logic analyzer to implement multiplexing processing of the on-chip information generated by multiple modules.

[0026] In an embodiment of the present application, the on-chip information includes at least: debugging information (Debug) and / or tracing information (Trace). Debug information (Debug) mainly focuses on the current specific status information, which is used to help engineers diagnose and solve problems in the system during development and maintenance. Register content: displays the value of the current register to help engineers understand the internal state of the CPU or other modules. Signal status: reflects the status of each signal line in the system, including input and output signals, interrupt signals, etc., to help engineers analyze the timing and status of signals. Memory content: displays the data currently in the memory, including variables, data structures, etc., to help engineers understand the usage of system memory. Error code: records errors or exceptions that occur in the system to help engineers quickly locate problems. Current instruction address: displays the address of the currently executed instruction to help engineers track the execution process of the program. Module status: records the current status of the module, such as running status, pause status, reset status, etc.

[0027] Tracing information mainly captures sequential event information, which is used to record the detailed execution process and state changes of the system over a period of time. For example, instruction pipeline: records the execution order of CPU instructions, including the stages of instruction fetch, decode, execute and write back for each instruction. Data cache operation: records the hits and misses of the data cache, including cache read, write, replace and other operations. System call: records the sequence of system calls, including the called functions, parameters, return values, etc. Task scheduling: records the scheduling of tasks, including events such as task creation, destruction, switching, etc. Interrupt handling: records the triggering and processing process of interrupts, including interrupt type, processing time, etc. Data flow: records the transmission path and operation of data in the system, including events such as data reading, writing, and transmission.

[0028] In the related art, since multiple modules on a chip may generate debugging and tracing information at the same time, it is a challenge to efficiently manage and schedule this information to avoid transmission delays and resource waste.

[0029] In the embodiment of the present application, each module is equipped with a FIFO (first-in-first-out) buffer for temporarily storing its tracking information. Here, a first-level FIFO buffer is configured separately for each module to temporarily store the tracking and debugging information generated by the module. This ensures that the information has a temporary storage area before transmission, avoiding direct competition for bus bandwidth.

[0030] As an optional embodiment, the first-level FIFO buffer matched with each module is a FIFO buffer independently set on each module side. Among them, the first-level FIFO buffer matched with each module is used to store the tracking information of each module respectively, and the first-level FIFO buffer matched with each module is connected to the second-level FIFO buffer. In this embodiment of the application, the second-level FIFO buffer is a common storage area shared by multiple modules.

[0031] Further optionally, the system on chip is also provided with a second level FIFO buffer, the second level FIFO buffer is used to store the debugging information generated by each module. Further, the second level FIFO buffer and the second level FIFO buffer in the system on chip are connected to the on-chip logic analyzer through the second level polling arbiter.

[0032] In practical applications, it is assumed that the system on chip contains n modules, each module generates different debugging information, and a first-level FIFO buffer is configured for each module. Figure 2 As shown, a single FIFO buffer is configured for each module. Figure 2 , . . . , level 1 cache n. Optionally, a second level FIFO buffer may be provided to receive debugging information of n modules, where the second level FIFO buffer is denoted as level 1 cache n.

[0033] For example, the circuit structure of the system on chip can refer to Figure 3 The circuit diagram is shown.

[0034] In an embodiment of the present application, a polling arbiter is used to extract tracking information from each FIFO according to a predetermined scheduling strategy. Further optionally, a weighted round robin (WRR) strategy is adopted. WRR is a scheduling algorithm that can be used in the present application for fair allocation of shared resources, such as on-chip network traffic management and CPU time slice allocation. Compared with simple round robin scheduling (Round Robin), WRR introduces the concept of weight, so that different tasks or data flows can obtain different resource allocation ratios according to their importance or needs.

[0035] Specifically, in an embodiment of the present application, the on-chip information generated by each module is assigned a weight, which reflects the resource share it can obtain in one cycle. The greater the weight, the more resources are allocated. The scheduler allocates resources to each task in turn in a cyclic order, but the amount allocated varies according to their respective weights. If the weight of a task is twice that of another task, then the resources it obtains in the same round will also be twice that of the latter.

[0036] In each round-robin scheduling cycle, available resources are accumulated to each task according to the weight until it reaches the corresponding weight value, and then resources are allocated to the next task. If a task cannot be fully processed within its allocated time slice, it will continue to be processed in the next cycle. This ensures that all tasks will eventually get a chance to be processed. The selected tracking information will be directly written to a common FIFO for further processing. The secondary FIFO buffer is a common storage area shared by multiple modules and is used to temporarily store information transmitted from the primary FIFO buffer.

[0037] The SoC has a debug bus and a trace bus. The debug bus and the trace bus are not enabled at the same time to avoid race conditions. When the trace information (Trace) is selected, the trace bus is enabled; when the debug information (Debug) is selected, the debug bus is enabled. Users can choose to focus on the debug information or the trace information as needed. When the debug information is selected, the debug bus always has a higher priority than the trace bus; when the trace information is selected, the trace bus always has a higher priority than the debug bus.

[0038] In the last stage, an additional polling arbiter is used to select debug or trace information to enter OCLA. An additional polling arbiter is used to select information transmitted by the debug bus or trace bus to enter OCLA. The fixed priority scheduling strategy ensures that the debug bus and trace bus are not enabled at the same time. Specifically, when the user selects the trace bus, the trace bus always has a higher priority than the debug bus. Conversely, when the user selects the debug bus, the debug bus always has a higher priority than the trace bus.

[0039] In 101, the modules generate debugging or tracing information and temporarily store it in their respective FIFO buffers. Each module generates debugging or tracing information during its operation and writes the information into its corresponding first-level FIFO buffer.

[0040] In 102, the polling arbiter extracts the tracking information from each FIFO in turn according to the set priority. The first-level polling arbiter extracts information from the first-level FIFO buffer of each module in turn according to the weighted polling scheduling strategy, and writes the extracted information into the second-level FIFO buffer.

[0041] In 103, the extracted information is multiplexed and the debug bus or the trace bus is selected for transmission. By using a union data structure, different data types are allowed to share the same memory location. This means that debug information and trace information can share the same transmission path. Based on the user's selection, the corresponding debug bus or trace bus is enabled. When the trace bus is enabled, the secondary polling arbiter transfers the information from the secondary FIFO buffer to the trace bus. When the debug bus is enabled, the information is transferred to the debug bus.

[0042] In practical applications, a union is a data structure that allows different data types to share the same memory location. Although it can only store one value at a time, it can flexibly switch between different data types. In the multiplexing process, the union data structure can be used to debug the bus and track the information transmission of the bus. By sharing the same memory space, two buses can use the same path, thereby saving chip area and simplifying the design.

[0043] Finally, in 104, the on-chip logic analyzer (OCLA) is used to monitor and store information transmitted from the debug bus or the trace bus for subsequent analysis and debugging. The selected information is monitored and stored by OCLA. The debug or trace information is selected to enter OCLA through an additional polling arbitrator. Here, OCLA monitors and stores this information, providing a centralized processing and analysis platform. Users can view and analyze debug information or trace information through OCLA to debug and optimize the system.

[0044] Based on the above steps, each module has an independent buffer, which avoids direct competition for bus bandwidth. It ensures the orderly transmission of information and avoids the long-term neglect of some module information, thereby improving the overall response speed of the system. Multiple modules share a secondary FIFO buffer, reducing the additional chip area. Through multi-level FIFO buffers and polling arbitrators, the interconnection structure between modules is simplified and the wiring complexity is reduced. Each module has an independent primary FIFO buffer, the system design is more modular, and the control logic is simpler. The primary and secondary polling arbitrators provide a unified scheduling mechanism, which simplifies the design and maintenance of the system. The primary and secondary FIFO buffers can temporarily store information, reduce the instantaneous pressure on the bus bandwidth, and reduce transmission delays. The polling arbitrator can quickly respond to information requests, reduce the time of bus switching and arbitration, and improve the real-time performance of the system. OCLA centrally processes the information transmitted from the secondary FIFO buffer, optimizes the data processing process, and improves the performance of the overall system.

[0045] Through the above-mentioned multi-level buffering and arbitration mechanism, the on-chip information multiplexing method not only effectively manages the debug and trace information, but also ensures the efficient transmission and processing of information, solving problems such as resource competition, increased chip area, increased system complexity and performance bottlenecks.

[0046] As an optional embodiment, in 102, according to the shared scheduling rule, the on-chip information is respectively transmitted from the respective currently temporarily stored first-level FIFO buffers to the second-level FIFO buffers through the first-level polling arbitrator, which can be implemented as the following steps: 1021, obtaining task information of each module; the task information at least includes: task scheduling information of each module and data processing task information currently executed by each module; 1022, configuring a corresponding task weight in each polling cycle for each module based on the task information; 1023. Read the corresponding on-chip information from the primary FIFO buffer of each module through the primary polling arbitrator according to the task weight, and store it in the secondary FIFO buffer.

[0047] For example, by introducing the weight configuration and the scheduling mechanism based on task information in step 102, the performance and efficiency of the on-chip information multiplexing system can be significantly improved. Assume that there are four modules (A, B, C, D) in a system on chip, and each module generates debug and trace information. The data processing task performed by module A is very important and needs to be frequently monitored, while the task of module B is relatively unimportant, and the tasks of modules C and D are of medium importance.

[0048] The task scheduling information of module A shows that its task frequency is high, and the data processing task currently being executed is very critical. The task scheduling information of module B shows that its task frequency is low, and the current task is relatively minor. The task scheduling information of modules C and D shows that their task frequency is medium, and the current task is also of medium importance. Based on the above task information, the weight of module A is configured to be 4, the weight of module B is 1, and the weights of modules C and D are 2. The information generated by module A will be extracted by the first-level polling arbitrator first to ensure that its important information can be transmitted to the second-level FIFO buffer in time. Since the information of module B has a lower weight, it will be extracted when there is no high-priority information to be transmitted, thereby reducing resource waste. The information of modules C and D will be extracted at the appropriate time according to their medium weight to ensure fair use of resources.

[0049] In a system-on-chip for real-time processing tasks, the debugging information generated by module A needs to be processed in a very short time to ensure the real-time performance of the system. The information generated by modules B and C can tolerate a certain delay. The task scheduling information and data processing task information of module A show that it has extremely high requirements for real-time performance. The task scheduling information and data processing task information of modules B and C show that they have lower requirements for real-time performance. Configure a higher weight for module A to ensure priority transmission of its information. Configure lower weights for modules B and C to reduce resource competition.

[0050] In this way, the debugging information of module A will be extracted and transmitted first, reducing the delay caused by resource competition and ensuring the real-time performance of the system. Although there will be some delay in the information of modules B and C, it will not significantly affect the overall performance of the system.

[0051] In a system-on-chip for complex computing, module A generates a large amount of data processing tasks, while module B generates a small amount of tasks. Module A generates a large amount of debugging and tracing information, which needs to be transmitted frequently. Module B generates a small amount of debugging and tracing information, which has a low transmission requirement. Configure a higher weight for module A to support its large amount of information transmission requirements. Configure a lower weight for module B to reduce unnecessary resource usage. The large amount of information from module A can be transmitted to the secondary FIFO buffer in a timely manner, optimizing the data processing process. The small amount of information from module B does not occupy too many resources, improving the overall resource utilization of the system.

[0052] In the system-on-chip used to handle critical tasks, the tasks processed by module A have an important impact on system reliability, while the tasks of module B have lower reliability requirements. The task scheduling information and data processing task information of module A show that its tasks have an important impact on system reliability. The task scheduling information and data processing task information of module B show that it has lower reliability requirements. Configure a higher weight for module A to ensure that its information can be processed and transmitted first. Configure a lower weight for module B to reduce excessive attention to its information. The critical information generated by module A can be processed and stored by OCLA in a timely manner, which improves the reliability of the system. Although the information of module B is transmitted slowly, it will not affect the overall reliability of the system.

[0053] In a system-on-chip for processing multi-module parallel processing, the task information of each module is different. The system design can be simplified through weight configuration and a scheduling mechanism based on task information. The task information generated by module A needs to be frequently monitored and processed. The task information generated by module B needs to be paid attention to only in specific circumstances. The task information generated by modules C and D needs to be checked regularly. Configure a higher weight for module A to ensure high-frequency transmission of its information. Configure a lower weight for module B and transmit its information only in specific circumstances. Configure medium weights for modules C and D and transmit their information regularly. Through weight configuration, the design and maintenance of the system are simplified and complex control logic is reduced. The system can dynamically adjust resource allocation according to the importance and needs of the task, which improves the flexibility and scalability of the system.

[0054] By introducing the task weight configuration and weighted polling scheduling mechanism based on task information in step 102, the resource utilization efficiency of the on-chip information multiplexing system can be significantly improved, transmission delay can be reduced, data processing flow can be optimized, system reliability can be improved, and system design can be simplified. This mechanism ensures the orderly and efficient transmission of information, making the on-chip system more flexible and reliable when processing the debugging and tracing information generated by multiple modules.

[0055] As an optional embodiment, in 1023, according to the task weight, the corresponding on-chip information is read from the primary FIFO buffer of each module through the primary polling arbitrator and stored in the secondary FIFO buffer, which can be implemented as follows: First, according to the task weight in each polling cycle, the resource configuration ratio configured for each module in each polling cycle is determined; the resource configuration ratio is the ratio between the available resource amount corresponding to each module and the total available resource amount in each polling cycle. Then, according to the resource configuration ratio in each polling cycle, the debugging information to be extracted in each module is read from the primary FIFO buffer to the secondary FIFO buffer through the primary polling arbitrator.

[0056] Exemplarily, in step 1023, by determining the resource allocation ratio in each polling cycle according to the task weight, and reading the debug information from the primary FIFO buffer of each module through the primary polling arbitrator according to these ratios and storing it in the secondary FIFO buffer, more efficient and orderly resource management can be achieved. Assume that there are three modules (A, B, C) in a system, and each module generates debug information and trace information. Module A is used to process high-frequency tasks, generates a large amount of debug information, and has high real-time requirements, with a weight of 4. Module B is used to process low-frequency tasks, generates a small amount of debug information, and has low real-time requirements, with a weight of 1. Module C is used to process medium-frequency tasks, generates a medium amount of debug information, and has medium real-time requirements, with a weight of 2.

[0057] Assume further that the total amount of resources available in each polling cycle is 100 units.

[0058] Based on this, the first-level polling arbiter reads the debugging information from the first-level FIFO buffer of each module according to the above resource configuration ratio and stores it in the second-level FIFO buffer. Module A generates a large amount of debugging information and has high real-time requirements. By allocating a higher resource ratio (57%), it ensures that its information can be extracted and transmitted first, reducing the delay caused by resource competition. At the same time, module B generates less debugging information and has lower real-time requirements. It allocates a lower resource ratio (14%) to avoid resource waste. Resource allocation is more reasonable, which improves resource utilization efficiency and ensures timely processing of high-frequency tasks. The debugging information generated by module A needs to be processed in a very short time to ensure the real-time performance of the system. With a higher resource ratio (57%), the information of module A can be extracted and transmitted first in each polling cycle, reducing transmission delay. The information transmission delay of critical tasks is significantly reduced, improving the real-time response capability of the system. Module C generates a moderate amount of debugging information and has moderate real-time requirements. By allocating a moderate resource ratio (29%), it ensures that its information can be extracted and transmitted at the right time, which not only meets its needs but also does not occupy too many resources. The data processing process is more optimized, achieving a dynamic balance of resources and improving the overall performance of the system. The tasks processed by module A have an important impact on system reliability. Through a higher resource ratio (57%), it ensures that the key debugging information it generates can be processed and transmitted in a timely manner, reducing the risk of system failure caused by information delay. The system reliability is significantly improved, and the information of key tasks can be monitored and processed in a timely manner.

[0059] Through weight configuration and resource allocation ratio, the system on chip can dynamically adjust resource allocation, avoiding complex fixed resource allocation schemes. For example, module B generates less debugging information and has lower real-time requirements, so it allocates a lower resource ratio (14%), simplifying the system control logic. System design and maintenance are simpler, the complexity of control logic is reduced, and the scalability and flexibility of the system are improved.

[0060] By determining the resource allocation ratio in each polling cycle based on the task weight in step 1023, and reading and transmitting the debugging information through the first-level polling arbiter according to these ratios, reasonable allocation and efficient management of resources can be achieved. This mechanism not only optimizes the process of information transmission and processing, improves resource utilization efficiency and real-time response capability, but also simplifies system design, improves the overall performance and reliability of the system, and makes the on-chip system more efficient and flexible when processing the debugging information generated by multiple modules.

[0061] Based on the on-chip system structure introduced in the above embodiment, in 103, the on-chip information is transmitted from the secondary FIFO buffer to the on-chip logic analyzer through the secondary polling arbitrator, which can be implemented as follows: 1031, determining the target on-chip information to be selected in the current polling cycle through the secondary polling arbiter; 1032, based on the information type of the target on-chip information, start a matching debug bus or trace bus; 1033 , transmitting the target on-chip information from the secondary FIFO buffer to an on-chip logic analyzer via a debug bus or a trace bus.

[0062] In the embodiment of the present application, the bus types include at least: a debug bus and a trace bus. In practical applications, the debug bus and the trace bus cannot be enabled at the same time, otherwise a race condition will occur, resulting in a transmission conflict of on-chip information. In a system on a chip, the debug bus and the trace bus are two different communication buses used to transmit different debugging and tracing information. The design purpose of these two buses is to optimize the transmission and processing of on-chip information, avoid race conditions and transmission conflicts, and improve the debugging and tracing capabilities of the system.

[0063] The debug bus is mainly used to transmit data related to system debugging, such as register status, memory content, hardware breakpoints, etc. The data transmitted by the debug bus is usually low-frequency, high-priority information, which needs to be accessed and processed in a timely manner during the debugging process. It helps developers and test engineers locate and solve system problems and ensure the normal operation of the system. It can use serial or parallel transmission methods and support point-to-point or broadcast transmission. Usually the bandwidth requirement is low, but low latency and high reliability need to be ensured.

[0064] The tracking bus is mainly used to transmit data related to system operation status and event tracking, such as instruction execution sequence, data flow, event log, etc. The data transmitted by the tracking bus is usually high-frequency, low-priority information, which is used to record the operation track and events of the system. It helps developers and test engineers analyze the operation status of the system and optimize performance and functions. It adopts high-speed serial transmission mode to support high bandwidth and large amount of data transmission. It has high bandwidth requirements and is used to transmit a large amount of high-speed generated tracking information.

[0065] In the above-mentioned system-on-chip structure, the specific steps of transmitting the on-chip information from the secondary FIFO buffer to the on-chip logic analyzer through the secondary polling arbiter are as follows: The secondary polling arbiter reads the on-chip information to be transmitted from the secondary FIFO buffer. According to the predetermined polling rules and priorities, the target on-chip information to be transmitted in the current polling cycle is determined. For example, the target information can be selected according to the weight ratio of each module or the urgency of the information. For example, assume that the debug information and trace information of modules A, B, and C are stored in the secondary FIFO buffer. The weight ratio (module A: 57%, module B: 14%, module C: 29%) is used for selection. If module A has more information and a higher weight, its information will be selected first.

[0066] The secondary polling arbiter identifies the type of target on-chip information and determines whether it is debug information or trace information. Depending on the type of information, the corresponding debug bus or trace bus is started. Debug information uses the debug bus, and trace information uses the trace bus. For example, if the target on-chip information is debug information generated by module A, the secondary polling arbiter will start the debug bus. If the target on-chip information is trace information generated by module C, the secondary polling arbiter will start the trace bus.

[0067] The secondary polling arbiter transfers the target on-chip information from the secondary FIFO buffer to the on-chip logic analyzer via the enabled debug bus or trace bus. In the same polling cycle, the debug bus and trace bus cannot be enabled at the same time to avoid race conditions and transfer conflicts.

[0068] For example, assuming that the target on-chip information selected in the current polling cycle is the debug information of module A, the secondary polling arbitrator starts the debug bus and transmits the debug information to the on-chip logic analyzer. In the next polling cycle, assuming that the target on-chip information selected is the trace information of module C, the secondary polling arbitrator starts the trace bus and transmits the trace information to the on-chip logic analyzer.

[0069] In this way, through the dynamic selection mechanism of the secondary polling arbitrator, the reasonable allocation of resources can be ensured, the information of high-frequency tasks is transmitted first, and the information of low-frequency tasks is transmitted on demand, avoiding resource waste. By giving priority to high-priority information types (such as debug information), its transmission delay can be significantly reduced, ensuring the real-time processing of key information. The clear division of labor and mutual exclusive activation mechanism of the debug bus and the trace bus avoids competition and conflict in information transmission, making the data processing process more optimized and orderly. By ensuring that the debug bus and the trace bus are mutually exclusive, the risk of transmission conflict is reduced and the reliability and stability of the system are improved. The dynamic selection mechanism of the secondary polling arbitrator and the clear division of labor of the bus simplify system design and maintenance, reduce the complexity of control logic, and improve the flexibility and scalability of the system.

[0070] By introducing the dynamic selection mechanism of the secondary polling arbiter and the mutually exclusive enabling mechanism of the debug bus and the trace bus in step 103, on-chip information can be effectively managed and transmitted, improving the resource utilization efficiency of the system, reducing transmission delay, optimizing the data processing flow, improving system reliability and simplifying system design. This mechanism ensures the orderly and efficient transmission of information, making the on-chip system more flexible and reliable when processing the debug and trace information generated by multiple modules.

[0071] Further optionally, in 1031, the target on-chip information to be executed is selected by the secondary polling arbitrator based on the task information of each module. Alternatively, in 1031, the secondary polling arbitrator may receive a user instruction and determine the target on-chip information to be executed based on the user instruction.

[0072] For example, users can actively select information that needs to be transmitted first. For example, in the critical debugging stage, users can indicate that the debugging information of module A should be transmitted first to ensure the efficient debugging process. Users have enhanced control over the system and can flexibly adjust the information transmission strategy according to actual needs. In different debugging scenarios, users can dynamically adjust the type of information that needs to be transmitted first through instructions. For example, in the performance optimization scenario, users can indicate that the tracking information of module C should be transmitted first to help analyze system performance. The system can better adapt to various debugging and optimization scenarios, improving the flexibility and applicability of the system.

[0073] For example, users can specify modules that need to be focused on. For example, during debugging, users can indicate that the debugging information of module A should be transmitted first to help quickly locate problems. The debugging efficiency is significantly improved, and users can obtain the required information more quickly, speeding up problem solving. Users can indicate that the information of module B should not be transmitted temporarily to avoid unnecessary resource occupation. Unnecessary information transmission is reduced, further improving resource utilization efficiency and the real-time performance of the system. Through user instructions, the information transmission strategy is dynamically adjusted, and system maintenance personnel can flexibly adjust it according to actual conditions and quickly respond to different debugging needs. System maintenance is more convenient, the response speed is faster, and the maintainability of the system is improved.

[0074] In the embodiments of the present application, the multiplexing of on-chip information not only solves the problems of resource competition, increased chip area, increased system complexity and performance bottlenecks, but can also be easily expanded by adding more modules and corresponding FIFO buffers without significantly increasing the design complexity. The polling arbitrator can dynamically adjust the order of information transmission according to different needs and priorities, thereby improving the flexibility of the system. The design of the FIFO buffer and the polling arbitrator can ensure the integrity and order of information and reduce data loss and errors. In the technical solution of the present application, the on-chip information multiplexing method effectively improves the debugging and tracking efficiency of the on-chip system by reasonably managing and scheduling information transmission, while reducing system complexity and cost.

[0075] In another embodiment of the present application, a multiplexing device for on-chip information is provided, and the device is applied to a system on chip including multiple modules. Figure 4 The device comprises the following units: A first-level first-in-first-out FIFO buffer is configured to obtain and store on-chip information generated by each module in the on-chip system; the on-chip information at least includes: debugging information and / or tracing information; A first-level polling arbiter is configured to transfer the on-chip information from the first-level FIFO buffers currently temporarily stored to the second-level FIFO buffers according to the shared scheduling rules; the second-level FIFO buffers are common storage areas shared by multiple modules; a secondary polling arbiter configured to transfer the on-chip information from the secondary FIFO buffer to an on-chip logic analyzer according to a static scheduling rule; The on-chip logic analyzer is configured to process the on-chip information to implement multiplexing processing of the on-chip information generated by multiple modules.

[0076] Further optionally, the first-level FIFO buffer, according to the shared scheduling rule, transmits the on-chip information from the first-level FIFO buffer currently temporarily stored to the second-level FIFO buffer through the first-level polling arbitrator, and is configured as follows: Acquire task information of each module; the task information at least includes: task scheduling information of each module and data processing task information currently executed by each module; Based on the task information, configure the corresponding task weight in each polling cycle for each module; According to the task weight, the corresponding on-chip information is read from the primary FIFO buffer of each module and stored in the secondary FIFO buffer.

[0077] Further optionally, the primary FIFO buffer reads the corresponding on-chip information from the primary FIFO buffer of each module through the primary polling arbitrator according to the task weight, and stores it in the secondary FIFO buffer, and is configured as follows: According to the task weight in each polling cycle, determine the resource allocation ratio configured for each module in each polling cycle; the resource allocation ratio is the ratio between the available resource amount corresponding to each module and the total available resource amount in each polling cycle; According to the resource allocation ratio in each polling cycle, the debugging information to be extracted in each module is read from the primary FIFO buffer to the secondary FIFO buffer.

[0078] Further optionally, the first-level FIFO buffer matched with each module is a FIFO buffer independently set on each module side; The first level FIFO buffers matched with each module are respectively used to store the tracking information of each module, and the first level FIFO buffers matched with each module are connected to the second level FIFO buffers.

[0079] Further optionally, a second level FIFO buffer is also provided in the system on chip, and the second level FIFO buffer is used to store the debugging information generated by each module.

[0080] Further optionally, the secondary FIFO buffer and the second primary FIFO buffer in the on-chip system are connected to the on-chip logic analyzer through the secondary polling arbitrator.

[0081] Further optionally, the secondary polling arbiter, which transmits the on-chip information from the secondary FIFO buffer to the on-chip logic analyzer through the secondary polling arbiter, is specifically configured as follows: Determine the target on-chip information to be selected in the current polling cycle; Based on the information type of the target on-chip information, a matching debug bus or trace bus is started; wherein the bus type includes at least: a debug bus and a trace bus; The target on-chip information is transmitted from the secondary FIFO buffer to an on-chip logic analyzer via a debug bus or a trace bus.

[0082] Further optionally, the secondary polling arbiter determines the target on-chip information to be selected in the current polling cycle, and is specifically configured as follows: Based on the task information of each module, the target on-chip information to be executed is selected through the secondary polling arbitrator; or, the user instruction is received through the secondary polling arbitrator, and the target on-chip information to be executed is determined based on the user instruction.

[0083] The system can implement various steps in the above method embodiment, which will not be expanded here.

[0084] In the embodiment of the present application, an on-chip information multiplexing device is used, ...

[0085] See also Figure 5 , Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present application. Figure 5 As shown, an embodiment of the present application provides an electronic device 500, including a memory 510, a processor 520, and a computer program 511 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, the following steps are implemented: obtaining on-chip information generated by each module in the on-chip system, and storing it in a first-level first-out FIFO buffer matching each module; the on-chip information at least includes: debugging information and / or tracing information; according to the shared scheduling rule, the on-chip information is respectively transferred from the first-level FIFO buffer currently temporarily stored to the second-level FIFO buffer through a first-level polling arbitrator; the second-level FIFO buffer is a common storage area shared by multiple modules; the on-chip information is transferred from the second-level FIFO buffer to the on-chip logic analyzer through a second-level polling arbitrator; the on-chip information is processed by the on-chip logic analyzer to realize multiplexing processing of on-chip information generated by multiple modules.

[0086] See also Figure 6 , Figure 6 A schematic diagram of an embodiment of a computer-readable storage medium provided in an embodiment of the present application. Figure 6 As shown, this embodiment provides a computer-readable storage medium 600, on which a computer program 611 is stored. When the computer program 611 is executed by a processor, the following steps are implemented: obtaining on-chip information generated by each module in the on-chip system, and storing it in a first-level first-out FIFO buffer matching each module; the on-chip information at least includes: debugging information and / or tracing information; according to the shared scheduling rule, the on-chip information is transmitted from the respective currently temporarily stored first-level FIFO buffers to the second-level FIFO buffers through a first-level polling arbitrator; the second-level FIFO buffer is a common storage area shared by multiple modules; the on-chip information is transmitted from the second-level FIFO buffer to the on-chip logic analyzer through a second-level polling arbitrator; the on-chip information is processed by the on-chip logic analyzer to realize multiplexing processing of the on-chip information generated by multiple modules.

[0087] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0088] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0089] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for multiplexing on-chip information, characterized in that: The method is applied to a system on chip including a plurality of modules, and the method comprises: Acquire on-chip information generated by each module in the on-chip system, and store it in a first-in-first-out FIFO buffer matching each module; the on-chip information at least includes: debugging information and / or tracing information; According to the shared scheduling rule, the on-chip information is respectively transmitted from the respective currently temporarily stored first-level FIFO buffers to the second-level FIFO buffers through the first-level polling arbiter; the second-level FIFO buffer is a common storage area shared by multiple modules; transmitting the on-chip information from the secondary FIFO buffer to an on-chip logic analyzer via a secondary polling arbiter; The on-chip information is processed by the on-chip logic analyzer to implement multiplexing processing of on-chip information generated by multiple modules.

2. The on-chip information multiplexing method according to claim 1, characterized in that: The on-chip information is respectively transmitted from the respective currently temporarily stored first-level FIFO buffers to the second-level FIFO buffers through the first-level polling arbitrator according to the shared scheduling rule, including: Acquire task information of each module; the task information at least includes: task scheduling information of each module and data processing task information currently executed by each module; Based on the task information, configure the corresponding task weight in each polling cycle for each module; According to the task weight, the corresponding on-chip information is read from the primary FIFO buffer of each module through the primary polling arbitrator and stored in the secondary FIFO buffer.

3. The on-chip information multiplexing method according to claim 2, characterized in that: The step of reading corresponding on-chip information from the primary FIFO buffer of each module through a primary polling arbitrator according to the task weight and storing the information in the secondary FIFO buffer comprises: According to the task weight in each polling cycle, determine the resource allocation ratio configured for each module in each polling cycle; the resource allocation ratio is the ratio between the available resource amount corresponding to each module and the total available resource amount in each polling cycle; According to the resource allocation ratio in each polling cycle, the debugging information to be extracted in each module is read from the first-level FIFO buffer to the second-level FIFO buffer through the first-level polling arbitrator.

4. The on-chip information multiplexing method according to any one of claims 1 to 3, characterized in that: The first-level FIFO buffer matched with each module is a FIFO buffer independently set on each module side; The first level FIFO buffers matched with each module are respectively used to store the tracking information of each module, and the first level FIFO buffers matched with each module are connected to the second level FIFO buffers.

5. The on-chip information multiplexing method according to claim 4, characterized in that: The system on chip is also provided with a second level FIFO buffer, and the second level FIFO buffer is used to store the debugging information generated by each module.

6. The on-chip information multiplexing method according to claim 5, characterized in that: The secondary FIFO buffer and the second primary FIFO buffer in the on-chip system are connected to the on-chip logic analyzer through the secondary polling arbiter.

7. The on-chip information multiplexing method according to claim 6, characterized in that: The method of transmitting the on-chip information from the secondary FIFO buffer to the on-chip logic analyzer through the secondary polling arbiter comprises: Determine the target on-chip information to be selected in the current polling cycle through the secondary polling arbiter; Based on the information type of the target on-chip information, a matching debug bus or trace bus is started; wherein the bus type includes at least: a debug bus and a trace bus; The target on-chip information is transmitted from the secondary FIFO buffer to an on-chip logic analyzer via a debug bus or a trace bus.

8. The on-chip information multiplexing method according to claim 7, characterized in that: The step of determining the target on-chip information to be selected in the current polling cycle by the secondary polling arbiter includes: Based on the task information of each module, the target on-chip information to be executed is selected through the secondary polling arbitrator; or, The user instruction is received through the secondary polling arbiter, and the target on-chip information to be executed is determined based on the user instruction.

9. An on-chip information multiplexing device, characterized in that: The device is applied to a system on chip including a plurality of modules, and the device comprises the following units, wherein: A first-level first-in-first-out FIFO buffer is configured to obtain and store on-chip information generated by each module in the on-chip system; the on-chip information at least includes: debugging information and / or tracing information; A first-level polling arbiter is configured to transfer the on-chip information from the first-level FIFO buffers currently temporarily stored to the second-level FIFO buffers according to the shared scheduling rules; the second-level FIFO buffers are common storage areas shared by multiple modules; a secondary polling arbiter configured to transfer the on-chip information from the secondary FIFO buffer to an on-chip logic analyzer according to a static scheduling rule; The on-chip logic analyzer is configured to process the on-chip information to implement multiplexing processing of the on-chip information generated by multiple modules.

10. An electronic device, characterized in that: include: Memory for storing computer software programs; A processor is used to read and execute the computer software program, thereby implementing the on-chip information multiplexing method as described in any one of claims 1-8.

11. A computer-readable storage medium, characterized in that: The storage medium stores a computer software program, and when the computer software program is executed by a processor, the on-chip information multiplexing method according to any one of claims 1 to 8 is implemented.

12. A chip, characterized in that: The chip is loaded with a computer software program and / or a hardware unit, and the computer software program and / or the hardware unit is used to implement the on-chip information multiplexing method as described in any one of claims 1-8.

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