Test structure, chip typesetting pattern and test method

Abstract

The invention relates to the technical field of semiconductors, and relates to a test structure, a chip typesetting pattern and a test method.The test structure comprises a test pad and a probe card, the test pad comprises a first edge and a second edge which are distributed in parallel and a third edge and a fourth edge which are distributed in parallel, and a first included angle is formed between the first edge and the third edge; the probe card comprises a probe arm and a test probe, the probe arm comprises a connecting surface, and the test probe is connected with the connecting surface; the orthographic projection of the test probe on the first reference surface and the orthographic projection of the connection surface on the first reference surface form a second included angle; the connecting surface comprises a side edge, a third included angle is formed between the orthographic projection of the test probe on the second reference surface and the orthographic projection of the side edge on the second reference surface, and the first included angle, the second included angle and the third included angle are all larger than 0 degree and smaller than 90 degrees; the first reference surface is any plane perpendicular to the connecting surface and parallel to the side edge, and the second reference surface is any plane parallel to the connecting surface. The test structure can reduce the width of the cutting channel and improve the yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test structure, a chip layout pattern and a test method. Background Art

[0002] During the chip pattern manufacturing process, it is necessary to set up a test structure to perform specific tests on each chip pattern on the wafer (for example, Wafer Acceptable Test (WAT)) to reflect the process fluctuations in the wafer tape-out stage and detect abnormalities in the production line. However, due to the existing test structure, the number of chip patterns that can be set on each wafer is small, and the production efficiency is low.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In view of this, the present disclosure provides a test structure, a chip layout pattern and a test method, which can reduce the width of the cutting path and improve the yield.

[0005] According to one aspect of the present disclosure, a test structure is provided, comprising:

[0006] A test pad, the test pad comprising a first side and a second side arranged in parallel, and a third side and a fourth side arranged in parallel, wherein the first side and the third side form a first angle;

[0007] A probe card comprises a probe arm and a test probe, wherein the probe arm comprises a connecting surface, and the test probe is connected to the connecting surface; the orthographic projection of the test probe on a first reference plane forms a second angle with the orthographic projection of the connecting surface on the first reference plane; the connecting surface comprises a side edge, and the orthographic projection of the test probe on the second reference plane forms a third angle with the orthographic projection of the side edge on the second reference plane, and the first angle, the second angle and the third angle are all greater than 0° and less than 90°; the first reference plane is any plane perpendicular to the connecting surface and parallel to the side edge, and the second reference plane is any plane parallel to the connecting surface.

[0008] In an exemplary embodiment of the present disclosure, the first angle, the second angle and the third angle are all equal.

[0009] In an exemplary embodiment of the present disclosure, the first angle, the second angle and the third angle are all 60°.

[0010] In an exemplary embodiment of the present disclosure, there are multiple test pads, which are spaced apart; there are multiple test probes, which are spaced apart, and a distance between two adjacent test pads is equal to a distance between two adjacent test probes.

[0011] In an exemplary embodiment of the present disclosure, the length ratio of the first side to the third side of the test pad is 7:6-4:3.

[0012] In an exemplary embodiment of the present disclosure, the test probe comprises:

[0013] A probe body, wherein the probe body is in a strip shape, one end of which is in contact with the connecting surface, and the other end of which extends to a side away from the connecting surface, and the orthographic projection of the probe body on the first reference plane and the orthographic projection of the connecting surface on the first reference plane form the second angle; the orthographic projection of the probe body on the second reference plane and the orthographic projection of the side on the second reference plane form the third angle;

[0014] The probe is connected to the end of the probe body away from the connection surface and can contact the test pad.

[0015] According to one aspect of the present disclosure, there is provided a chip layout pattern, comprising a plurality of spaced-apart chip patterns and any one of the above-mentioned test structures, wherein the test structure is located between two adjacent chip patterns.

[0016] In an exemplary embodiment of the present disclosure, a cutting path is provided between two adjacent chip patterns, and the test structure is provided in the cutting path.

[0017] In an exemplary embodiment of the present disclosure, there are multiple test structures, and the multiple test structures are distributed at intervals along the extension direction of the cutting road.

[0018] According to one aspect of the present disclosure, a testing method is provided, the testing method being used to perform parameter measurement using any one of the test structures described above, the testing method comprising:

[0019] placing the test pad opposite to the test probe;

[0020] A pressure is applied to the test probe to make the test probe contact the test pad and slide the test probe along the extending direction of the third side of the test pad.

[0021] In the test structure and test method disclosed in the present invention, the first side, the second side, the third side and the fourth side can form a parallelogram, and the height of the test pad can be reduced without reducing the area of ​​the test pad, which helps to reduce the width of the cutting path where the test pad is located, thereby leaving more space for the layout of the chip graphics, thereby increasing the number of chip graphics that can be laid out on the wafer, and helping to improve the yield. At the same time, since the orthographic projection of the test probe on the first reference plane and the orthographic projection of the connecting surface on the first reference plane form a second angle, the orthographic projection of the test probe on the second reference plane and the orthographic projection of the side on the second reference plane form a third angle, and the first angle, the second angle and the third angle are all greater than 0° and less than 90°, thereby forming an acute angle between the test probe and the probe arm, which helps to reduce the deviation between the sliding direction of the test probe and the inclination direction of the hypotenuse of the parallelogram, and can reduce the probability of the test probe deviating from the test pad during the test process, thereby ensuring the test effect and improving the test accuracy.

[0022] The chip layout pattern disclosed in the present invention, since the first side, second side, third side and fourth side of the test structure form a parallelogram, can reduce the height of the test pad without reducing the area of ​​the test pad, thereby reducing the width of the space required for the test pad, helping to reduce the spacing between adjacent chip patterns, thereby increasing the number of chip patterns that can be layout on the wafer, and helping to improve production.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0025] Figure 1 Schematic diagram of a test pad and a dicing lane in the related art.

[0026] Figure 2 It is a front view of a test probe in the related art.

[0027] Figure 3 Schematic diagram of a test pad in an embodiment of the present disclosure.

[0028] Figure 4 It is a front view of the test structure in the embodiment of the present disclosure.

[0029] Figure 5 FIG. 4 is a top view of the test structure in the embodiment of the present disclosure.

[0030] Figure 6 It is a left view of the test structure in the embodiment of the present disclosure.

[0031] Figure 7 Schematic diagram of chip layout graphics in an embodiment of the present disclosure.

[0032] Figure 8 Schematic diagram of the sliding direction of the probe in the embodiment of the present disclosure.

[0033] Description of reference numerals:

[0034] 100, test pad; 200, test probe; 300, cutting path; 1, test pad; 11, first side; 12, second side; 13, third side; 14, fourth side; 2, probe card; 21, probe arm; 211, connection surface; 2111, side; 22, test probe; 221, probe body; 222, probe head; 500, chip pattern; 600, cutting path; 700, alignment mark; 800, sealing ring; θ1, first angle; θ2, second angle; θ3, third angle. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0036] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0037] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", "third" and "fourth" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0038] Wafer Acceptance Test (WAT) is a test of various parameters on semiconductor wafers after all process steps are completed, such as the resistance of resistors, the capacitance of MOS gate oxide layer, the characteristics of transistors, etc. WAT can reflect the process fluctuations in the wafer tape-out stage and detect abnormalities in the production line, and then reflect the process level of wafer products, maintain the uniformity of chip process in the wafer, and make its electrical and physical properties reach appropriate standards throughout the wafer.

[0039] The WAT test structure is usually designed in the scribe line area. The scribe line is the area between chip patterns. Reducing the width of the scribe line can increase the number of chip patterns on each wafer and improve the yield. With the advancement of the scribe process, the width of the scribe is no longer a bottleneck that limits the further narrowing of the scribe line, but the height of the test pad of the WAT test structure limits the further narrowing of the scribe line. Therefore, under the premise of ensuring the test effect of the test pad, reducing the height of the test pad has become a research hotspot.

[0040] like Figure 1 and Figure 2 As shown, the test structure mainly includes a test pad 100 and a test probe 200, wherein the test pad 100 is arranged in a cutting path 300, and the test pad 100 is rectangular. Figure 1 As shown, the height of the test pad 100 is h1, the width of the cutting path 300 is H1, and during the test process, the sliding distance of the test probe 200 on the test pad 100 is S1, and the sliding direction is as shown in FIG. Figure 1 However, the height h1 of the test pad 100 is relatively large, so that the width H1 of the dicing road 300 is also relatively large, and the number of chip patterns that can be arranged on the wafer is relatively small, and the yield is relatively small.

[0041] Based on this, the present disclosure provides a test structure, such as Figure 3-Figure 5 As shown, the test structure may include a test pad 1 and a probe card 2, wherein:

[0042] The test pad 1 includes a first side 11 and a second side 12 that are arranged in parallel, and a third side 13 and a fourth side 14 that are arranged in parallel, and the first side 11 and the third side 13 form a first angle θ1;

[0043] The probe card 2 includes a probe arm 21 and a test probe 22. The probe arm 21 includes a connecting surface 211, and the test probe 22 is connected to the connecting surface 211. The orthographic projection of the test probe 22 on the first reference plane and the orthographic projection of the connecting surface 211 on the first reference plane form a second angle θ2. The connecting surface 211 includes a side edge 2111. The orthographic projection of the test probe 22 on the second reference plane and the orthographic projection of the side edge 2111 on the second reference plane form a third angle θ3. The first angle θ1, the second angle θ2 and the third angle θ3 are all greater than 0° and less than 90°. The first reference plane is any plane perpendicular to the connecting surface 211 and parallel to the side edge 2111, and the second reference plane is any plane parallel to the connecting surface 211.

[0044] In the test structure disclosed in the present invention, the first side 11, the second side 12, the third side 13 and the fourth side 14 can form a parallelogram, and the height of the test pad 1 can be reduced without reducing the area of ​​the test pad 1, which helps to reduce the width of the cutting road 600 where the test pad 1 is located, thereby leaving more space for the layout of the chip graphics, thereby increasing the number of chip graphics that can be laid out on the wafer, and helping to improve the yield. At the same time, since the orthographic projection of the test probe 22 on the first reference plane and the orthographic projection of the connecting surface 211 on the first reference plane form a second angle θ2, the orthographic projection of the test probe 22 on the second reference plane and the orthographic projection of the side 2111 on the second reference plane form a third angle θ3, and the first angle θ1, the second angle θ2 and the third angle θ3 are all greater than 0° and less than 90°, thereby making the test probe 22 and the probe arm 21 form an acute angle, which helps to reduce the deviation between the sliding direction of the test probe 22 and the inclined direction of the hypotenuse of the parallelogram, and can reduce the probability of the test probe 22 deviating from the test pad 1 during the test process, thereby ensuring the test effect and improving the test accuracy.

[0045] The following is a detailed description of each part of the test structure disclosed in the present invention and its specific details:

[0046] The test pad 1 may be in the form of a sheet, which may include a first side 11 and a second side 12 distributed in parallel, and a third side 13 and a fourth side 14 distributed in parallel, wherein the first side 11 and the third side 13 are at a first angle θ1. In some embodiments of the present disclosure, the first angle θ1 may be greater than 0° and less than 90°, that is, the first angle θ1 may be an acute angle. For example, the first angle θ1 may be 30°, 45°, 60° or 75°, etc. Of course, the first angle θ1 may also be other angles, which are not listed here one by one. For example, the test pad 1 may be in the form of a parallelogram, and optionally, the test pad 1 may be in the form of a rhombus. The material of the test pad 1 may be a conductive material, for example, it may be copper or aluminum, and of course, it may also be other materials with good conductive properties, which are not listed here one by one.

[0047] In some embodiments of the present disclosure, the length ratio of the first side 11 and the third side 13 of the test pad 1 may be 7:6 to 4:3. For example, the length ratio of the first side 11 and the third side 13 of the test pad 1 is 7:6, 6:5, 5:4 or 4:3, etc. Of course, the length ratio of the first side 11 and the third side 13 of the test pad 1 may also be other values, which are not listed here one by one.

[0048] In some embodiments of the present disclosure, please continue to refer to Figure 3 As shown, the number of the test pads 1 can be multiple, and the multiple test pads 1 can be spaced apart along the extension direction of the cutting road 600. For example, the multiple test pads 1 can be spaced apart at equal intervals along the extension direction of the cutting road 600. The heights of different test pads 1 can be equal, so as to leave more space for the chip pattern without wasting the space of the cutting road 600. Of course, the heights of different test pads 1 can also be unequal, which is not particularly limited here.

[0049] The probe card 2 can contact the test pad 1 to perform parameter testing (for example, the resistance value of a resistor, the gate oxide capacitance value of a MOS, the characteristics of a transistor, etc.). Figure 4-Figure 6 As shown, the probe card 2 may include a probe arm 21 and a test probe 22, wherein:

[0050] Please continue to see Figure 4 and Figure 5 As shown, the probe arm 21 may be in a strip or sheet shape, and the probe arm 21 may include a connecting surface 211, and the connecting surface 211 may be a plane. In some embodiments of the present disclosure, please continue to refer to Figure 5 As shown, the connection surface 211 may include at least one side 2111, and the side 2111 may be linear. For example, the connection surface 211 may be rectangular, and any side of the rectangular connection surface 211 may serve as the side 2111. The material of the probe arm 21 may be a conductive material so as to deliver current to the test probe 22 during the test process. For example, the material of the probe arm 21 may be copper or aluminum, etc. Of course, the material of the probe arm 21 may also be other materials with good conductivity, which is not particularly limited here. The test probe 22 may be connected to the connection surface 211. For example, the test probe 22 may be in contact with the connection surface 211, for example, the test probe 22 and the connection surface 211 may be connected together by welding or the like.

[0051] Please continue to see Figure 4-Figure 6As shown, the test probe 22 may be in a strip shape, and one end thereof may be in contact with and connected to the connection surface 211. The test probe 22 may be arranged at an angle relative to the connection surface 211. For example, the orthographic projection of the test probe 22 on the first reference plane and the orthographic projection of the connection surface 211 on the first reference plane form a second angle θ2. The second angle θ2 may be greater than 0° and less than 90°, that is, the second angle θ2 may be an acute angle. For example, the second angle θ2 may be 30°, 45°, 60° or 75°, etc. Of course, the second angle θ2 may also be other angles, which are not listed here one by one. In some embodiments of the present disclosure, the second angle θ2 may be equal to the first angle θ1, for example, the second angle θ2 and the first angle θ1 may both be 30°, 45°, 60° or 75°. Preferably, the second angle θ2 and the first angle θ1 may both be 60°.

[0052] The orthographic projection of the test probe 22 on the second reference plane and the orthographic projection of the side 2111 on the second reference plane form a third angle θ3, and the third angle θ3 may be greater than 0° and less than 90°, that is, the third angle θ3 may be an acute angle. For example, the third angle θ3 may be 30°, 45°, 60° or 75°, etc. Of course, the third angle θ3 may also be other angles, which are not listed here one by one. In some embodiments of the present disclosure, the third angle θ3 may be equal to the first angle θ1 and the second angle θ2. During the test process, the tilt direction of the test probe 22 can be ensured to be consistent with the tilt direction of the second side 12 and the fourth side 14 of the test pad 1. After applying pressure to the test probe 22, the sliding direction of the test probe 22 is consistent with the tilt direction of the third side 13 or the fourth side 14 of the test pad 1, thereby ensuring that the test probe 22 will not slide out of the surface of the test pad 1, and the probability of the test probe 22 deviating from the test pad 1 during the test process can be reduced, thereby ensuring the test effect and improving the test accuracy. For example, the third angle θ3, the second angle θ2 and the first angle θ1 can all be 30°, 45°, 60° or 75°. Preferably, the third angle θ3, the second angle θ2 and the first angle θ1 can all be 60°.

[0053] It should be noted that the first reference plane is any plane perpendicular to the connection surface 211 and parallel to the side 2111, and the second reference plane can be any plane parallel to the connection surface 211. The first reference plane and the second reference plane are only virtual planes constructed to illustrate the positional relationship between the test probe 22 and the connection surface 211, and the first reference plane and the second reference plane are not actual physical structures.

[0054] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 4-Figure 6 As shown, the test probe 22 may include a probe body 221 and a probe head 222, wherein:

[0055] The probe body 221 may be in a strip shape, one end of which may be in contact with the connection surface 211, and the other end of which may extend to a side away from the connection surface 211. The probe body 221 may be arranged obliquely relative to the connection surface 211. Figure 4 As shown, the orthographic projection of the probe body 221 on the first reference plane and the orthographic projection of the connecting surface 211 on the first reference plane form a second angle θ2. Figure 5 As shown, the orthographic projection of the probe body 221 on the second reference plane forms a third angle θ3 with the orthographic projection of the side 2111 on the second reference plane. The material of the probe body 221 can be a conductive material, for example, copper or aluminum, or other materials with good conductive properties. The material of the probe body 221 is not particularly limited here.

[0056] The probe 222 can be connected to the end of the probe body 221 away from the connection surface 211, and when the test probe 22 is placed opposite to the test pad 1 and pressure is applied to the probe arm 21, the probe 222 can contact the test pad 1. In some embodiments of the present disclosure, the probe 222 can be in the form of a sheet, a strip, a block or a plate. The probe 222 can have a preset angle with the probe body 221, and the preset angle can be an acute angle. When the test probe 22 is placed opposite to the test pad 1, the angle between the probe 222 and the test pad 1 can be smaller than the angle between the probe body 221 and the test pad 1. The material of the probe 222 can be a conductive material, for example, the material can be copper or aluminum, and of course, it can also be other materials with good conductive properties. The material of the probe 222 is not specifically limited here. It should be noted that the material of the probe 222 and the probe body 221 can be the same or different, and is not specifically limited here.

[0057] In an exemplary embodiment of the present disclosure, the number of test probes 22 may be multiple, and the multiple test probes 22 may be connected to the same probe arm 21, and each test probe 22 may be spaced apart along the extension direction of the side 2111 of the connection surface 211 of the probe arm 21, and the spacing between different test probes 22 matches the spacing between different test pads 1. For example, when each test pad 1 is spaced apart at an equal spacing, each test probe 22 is also spaced apart at an equal spacing, and the spacing between two adjacent test pads 1 is equal to the spacing between two adjacent test probes 22. During the test process, each test probe 22 may contact and connect with a corresponding test pad 1.

[0058] It should be noted that the angles between different test probes 22 connected to the same probe arm 21 and the connection surface 211 can be equal, so that parameter tests can be performed on multiple spaced test pads 1 simultaneously through the same test probe 22, which helps to ensure the stability of test data.

[0059] The present disclosure also provides a chip layout pattern, such as Figure 7 As shown, the chip layout pattern includes a plurality of spaced-apart chip patterns 500 and a test structure in any of the above embodiments, and the test structure is located between two adjacent chip patterns 500 .

[0060] The chip layout pattern disclosed in the present invention, since the first side 11, the second side 12, the third side 13 and the fourth side 14 of the test pad 1 form a parallelogram, the height of the test pad 1 can be reduced without reducing the area of ​​the test pad 1, thereby reducing the width of the space required for the test pad 1, which helps to reduce the spacing between adjacent chip patterns 500, thereby increasing the number of chip patterns 500 that can be layout on the wafer, and helping to improve production.

[0061] In an exemplary embodiment of the present disclosure, the chip pattern 500 may be a chip unit including a word line, a bit line, a capacitor, a redistribution layer, and a control circuit. A plurality of chip patterns 500 may be formed on a wafer, and the plurality of chip patterns 500 are arranged in rows and / or columns. For example, the plurality of chip patterns 500 may be distributed in an array. A cutting road 600 is provided between two adjacent chip patterns 500, and the cutting road 600 outside each chip pattern 500 may surround the chip pattern 500 in a ring shape. For example, the cutting road 600 may surround the periphery of the chip pattern 500 in accordance with the edge shape of the chip pattern 500. For example, when the chip pattern 500 is rectangular, the cutting road 600 may be a rectangular ring. It should be noted that the test structure of the present disclosure may be provided in the cutting road 600, and when the number of the test structures is multiple, the plurality of test structures may be distributed at intervals along the extension direction of the cutting road 600. Of course, the test structure may also be arranged in the vacant area between the chip patterns 500 in the chip layout pattern, and no special limitation is made to the specific arrangement position of the test structure.

[0062] In an exemplary embodiment of the present disclosure, the chip layout pattern of the present disclosure may further include an alignment mark 700, which may also be located in the cutting road 600 and may be spaced apart from the test structure. In some embodiments of the present disclosure, the alignment mark 700 may be located in the cutting road 600 on the periphery of at least one chip pattern 500 located in the central area of ​​the wafer; or, the alignment mark 700 may be provided in the cutting road 600 of at least one chip pattern 500 located around the wafer; or, at least one alignment mark 700 may be provided in the cutting road 600 of each chip pattern 500, and the alignment mark 700 may be spaced apart from the test structure in the cutting road 600 along the extension direction of the cutting road 600. When the width of the cutting road 600 is reduced, the height of the alignment mark 700 may also be reduced accordingly. For example, the width of the cutting road 600 in the embodiment of the present disclosure is H2, the height of the test pad 1 is h2, and the sliding distance of the test probe 22 on the test pad 1 is S2. Compared with the test pad 100 in the prior art (the width of the cutting path 300 is H1, the height of the test pad 100 is h1, and the sliding distance of the test probe 200 on the test pad 100 is S1), the height of the test pad 1 is reduced by one seventh, the width of the cutting path 600 is reduced by one sixth, and the sliding distance of the test probe 22 on the test pad 1 remains unchanged, that is, H1:H2 is 6:5; h1:h2 is 7:6; S2=S1.

[0063] In some embodiments of the present disclosure, please continue to refer to Figure 3 As shown, when the test pad 1 is located in the cutting path 300, a sealing ring 800 may be further provided on the outer side of the test pad 1. The sealing ring 800 may be located between the test pad 1 and the edge of the cutting path 300, and may surround the chip pattern 500 in a ring shape. When cutting the wafer, the chip pattern 500 may be protected by the sealing ring 800 to prevent the chip pattern 500 from being damaged when cutting the wafer. In the embodiment of the present disclosure, the width of the cutting path 300 is twice the width of the sealing ring 800 plus the height of the test pad 1. In some embodiments of the present disclosure, the material of the sealing ring 800 may be a metal material.

[0064] The present disclosure also provides a test method, which is used to measure parameters using the test structure in any of the above embodiments. The test method may include steps S110 and S120, wherein:

[0065] Step S110, placing the test pad 1 and the test probe 22 opposite to each other;

[0066] Step S120 , applying pressure to the test probe 22 to make the test probe 22 contact the test pad 1 , and make the test probe 22 slide along the extending direction of the third side 13 of the test pad 1 .

[0067] In the test method disclosed in the present invention, since the orthographic projection of the test probe 22 on the first reference plane and the orthographic projection of the connecting surface 211 on the first reference plane form a second angle θ2, the orthographic projection of the test probe 22 on the second reference plane and the orthographic projection of the side 2111 on the second reference plane form a third angle θ3, and the first angle θ1, the second angle θ2 and the third angle θ3 are all greater than 0° and less than 90°, thereby making an acute angle between the test probe 22 and the probe arm 21, which can reduce the deviation between the sliding direction of the test probe 22 and the inclination direction of the hypotenuse of the parallelogram, and can reduce the probability of the test probe 22 deviating from the test pad 1 during the test process, thereby ensuring the test effect and improving the test accuracy.

[0068] In step S110 , the test probe 22 is placed opposite to the test pad 1 .

[0069] After all the process technologies of the wafer are completed, the wafer can be subjected to wafer acceptance test (WAT), and then the process fluctuations in the wafer tape-out stage and the abnormality of the detection production line can be judged according to the test results, and then the process level of the wafer product can be judged, and further judged whether the electrical and physical properties of the wafer meet the appropriate standards in the entire wafer. Before performing the wafer acceptance test, the probe 222 of the test probe 22 can be placed opposite to the test pad 1, that is, the probe 222 of each test probe 22 connected to the probe arm 21 is respectively arranged opposite to a test pad 1.

[0070] It should be noted that when the test probe 22 includes the probe head 222, when the test probe 22 is placed relative to the test pad 1, the angle between the probe head 222 and the surface of the test pad 1 may be smaller than the angle between the probe body 221 and the surface of the test pad 1, and the distance between the test probe 22 and the test pad 1 is relatively small, that is, after applying pressure to the test probe 22, the probe head 222 may contact the test pad 1 and may slide along the inclined direction of the oblique edge (e.g., the third edge 13 or the fourth edge 14) of the test pad 1. Of course, the probe head 222 may also be in direct contact with the surface of the test pad 1.

[0071] In step S120 , pressure is applied to the test probe 22 to make the test probe 22 contact the test pad 1 and make the test probe 22 slide along the extending direction of the third side 13 of the test pad 1 .

[0072] Pressure can be applied to the test probe 22, thereby increasing the contact area between the probe 222 and the test pad 1 and reducing the contact impedance. After the pressure is applied, the probe 222 can slide along the tilt direction of the probe body 221. During this process, since the test probe 22 and the probe arm 21 form an acute angle, the deviation between the sliding direction of the test probe 22 and the tilt direction of the hypotenuse of the parallelogram can be reduced, and the probability of the test probe 22 deviating from the test pad 1 during the test process can be reduced, thereby ensuring the test effect and improving the test accuracy. In some embodiments of the present disclosure, when the first angle θ1, the second angle θ2 and the third angle θ3 are all equal, during the test process, the inclination direction of the test probe 22 can be ensured to be consistent with the inclination direction of the third side 13 and the fourth side 14 of the test pad 1. After pressure is applied to the test probe 22, the sliding direction of the test probe 22 is consistent with the inclination direction of the third side 13 or the fourth side 14 of the test pad 1, thereby ensuring that the test probe 22 will not slide out of the surface of the test pad 1, which can reduce the probability of the test probe 22 deviating from the test pad 1 during the test process, thereby ensuring the test effect and improving the test accuracy.

[0073] For example, Figure 8 As shown, during the test, after applying pressure to the probe arm 21, the probe 222 may contact the test pad 1. When the pressure is continuously applied, since the first angle θ1, the second angle θ2 and the third angle θ3 are all equal, the sliding direction of the probe 222 is consistent with the inclination direction of the third side 13 and the fourth side 14, that is, the probe 222 may move along Figure 8 Sliding in the direction of the middle arrow, the sliding distance may be S2. Since S2 is equal to S1, the test pad 1 in the present disclosure will not shorten the sliding distance.

[0074] It should be noted that, although the steps of the test method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0075] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A test structure, characterized in that: include: A test pad, the test pad comprising a first side and a second side arranged in parallel, and a third side and a fourth side arranged in parallel, wherein the first side and the third side form a first angle; A probe card, comprising a probe arm and a test probe, wherein the probe arm comprises a connection surface, and the test probe is connected to the connection surface; The orthographic projection of the test probe on the first reference plane and the orthographic projection of the connecting surface on the first reference plane form a second angle; the connecting surface includes a side edge, and the orthographic projection of the test probe on the second reference plane and the orthographic projection of the side edge on the second reference plane form a third angle, and the first angle, the second angle and the third angle are all greater than 0° and less than 90°; the first reference plane is any plane perpendicular to the connecting surface and parallel to the side edge, and the second reference plane is any plane parallel to the connecting surface.

2. The test structure according to claim 1, characterized in that: The first angle, the second angle and the third angle are all equal.

3. The test structure according to claim 2, characterized in that: The first angle, the second angle and the third angle are all 60°.

4. The test structure according to any one of claims 1 to 3, characterized in that: There are multiple test pads, which are spaced apart; there are multiple test probes, which are spaced apart, and the distance between two adjacent test pads is equal to the distance between two adjacent test probes.

5. The test structure according to any one of claims 1 to 3, characterized in that: The length ratio of the first side to the third side of the test pad is 7:6 to 4:

3.

6. The test structure according to any one of claims 1 to 3, characterized in that: The test probe comprises: A probe body, wherein the probe body is in a strip shape, one end of which is in contact with the connecting surface, and the other end of which extends to a side away from the connecting surface, and the orthographic projection of the probe body on the first reference plane and the orthographic projection of the connecting surface on the first reference plane form the second angle; the orthographic projection of the probe body on the second reference plane and the orthographic projection of the side on the second reference plane form the third angle; The probe is connected to the end of the probe body away from the connection surface and can contact the test pad.

7. A chip layout pattern, characterized in that: It comprises a plurality of chip patterns distributed at intervals and the test structure according to any one of claims 1 to 6, wherein the test structure is located between two adjacent chip patterns.

8. The chip layout pattern according to claim 7, characterized in that: A cutting path is arranged between two adjacent chip patterns, and the test structure is arranged in the cutting path.

9. The chip layout pattern according to claim 8, characterized in that: There are multiple test structures, and the multiple test structures are distributed at intervals along the extending direction of the cutting path.

10. A testing method, characterized in that: The test method is used to perform parameter measurement using the test structure according to any one of claims 1 to 6, and the test method comprises: placing the test pad opposite to the test probe; A pressure is applied to the test probe to make the test probe contact the test pad and make the test probe slide along the extending direction of the third side of the test pad.

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