Simulation method, device and equipment for semiconductor device comprising quantum bound region

Abstract

The embodiment of the invention discloses a method, a device and equipment for simulating a semiconductor device containing a quantum bound area, and the method comprises the steps: dividing a structure model corresponding to a semiconductor device to be simulated into at least two structure sub-models according to the information of a target position where at least one quantum bound area is located; generating at least one low-dimensional grid unit for a boundary area between the structure sub-models with adjacent spatial positions to form a low-dimensional grid, generating high-dimensional grid units for the adjacent structure sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtaining a target structure model corresponding to the semiconductor device to be simulated after grid construction is completed; based on the preset electric energy equation set, the electric energy distribution information of each grid point in the target structure model corresponding to the to-be-simulated semiconductor device is determined, the performance loss caused by interpolation between two different dimensions of grids in the numerical simulation solving process of the semiconductor device is avoided, and the calculation efficiency and numerical precision of semiconductor device simulation are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor simulation technology, and in particular to a semiconductor device simulation method, device and equipment including a quantum confinement region. Background Art

[0002] With the rapid development of computer technology, semiconductor device models corresponding to physical semiconductor devices can be designed in semiconductor device simulation platforms, and the performance of semiconductor device models can be explored through numerical simulation algorithms, which can help engineers and scientists better understand and optimize the design of semiconductor devices. Near the interfaces of different materials in many semiconductor devices, due to their small size or drastic changes in band structure, quantum confinement effects that have a significant impact on device performance will appear. This effect can be modeled and calculated in semiconductor device simulation platforms.

[0003] At present, for semiconductor devices with quantum confinement effects, the commonly used simulation method is: in addition to the high-dimensional equations of the entire device, an additional low-dimensional partial differential equation needs to be solved. For example, an additional low-dimensional grid is generated in the quantum confinement region of the high-dimensional grid (representing the semiconductor device model); the high-dimensional equations of the entire device are solved on the high-dimensional grid, and the quantum confinement equations are solved on the low-dimensional grid; the two grids are interpolated, and the solution of one grid is used as the parameter of the other grid; the above steps are repeated until convergence to a self-consistent solution.

[0004] However, the existing technical solutions require repeated interpolation between two grids of different dimensions, which will lose simulation efficiency and accuracy. At the same time, the process of semiconductor device simulation and solution is to solve equations on two grids of different dimensions, which slows down the convergence speed. Based on this, there are technical problems such as slow simulation efficiency and low accuracy of semiconductor devices containing quantum confinement regions. Summary of the invention

[0005] The present invention provides a semiconductor device simulation method, device and equipment including a quantum confinement region, so as to avoid the performance loss caused by interpolation between two grids of different dimensions in the process of solving the numerical simulation of the semiconductor device, and improve the computational efficiency and numerical accuracy of the semiconductor device simulation.

[0006] In a first aspect, an embodiment of the present invention provides a simulation method for a semiconductor device including a quantum confinement region, the method comprising:

[0007] According to target position information of at least one quantum confinement region, the structural model corresponding to the semiconductor device to be simulated is divided into at least two structural sub-models;

[0008] For the boundary area between the structural sub-models that are adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary area to form a low-dimensional grid, and at least one high-dimensional grid unit is generated for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and when the grid construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained; wherein the low-dimensional grid unit includes at least two grid points and connecting edges between each of the grid points, and the high-dimensional grid unit includes at least three grid points and connecting edges between each of the grid points;

[0009] Based on a preset electric energy equation group, electric energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated is determined.

[0010] In a second aspect, an embodiment of the present invention further provides a simulation device including a quantum confinement region semiconductor device, the device comprising:

[0011] A sub-model division module, used for dividing the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region;

[0012] A grid unit generation module, for generating at least one low-dimensional grid unit in the boundary area between the structural sub-models adjacent in spatial position to form a low-dimensional grid, and generating at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtaining a target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed; wherein the low-dimensional grid unit includes at least two grid points and connecting edges between each of the grid points, and the high-dimensional grid unit includes at least three grid points and connecting edges between each of the grid points;

[0013] The model simulation module is used to determine the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated based on a preset power equation group.

[0014] In a third aspect, an embodiment of the present invention further provides an electronic device, the electronic device comprising:

[0015] one or more processors;

[0016] a storage device for storing one or more programs,

[0017] When one or more programs are executed by one or more processors, the one or more processors implement a simulation method for a semiconductor device including a quantum confinement region as described in any one of the embodiments of the present invention.

[0018] In a fourth aspect, an embodiment of the present invention further provides a storage medium comprising computer executable instructions, which, when executed by a computer processor, are used to perform a simulation method of a semiconductor device comprising a quantum confinement region as described in any of the embodiments of the present invention.

[0019] The technical solution of the embodiment of the present invention is to divide the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region, and then, for the boundary region between the structural sub-models adjacent in spatial position, generate at least one low-dimensional grid unit in the boundary region to form a low-dimensional grid, and generate at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtain the target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed, wherein the low-dimensional grid unit includes at least two grid points and the connecting edges between each grid point, and the high-dimensional grid unit includes at least three grid points and the connecting edges between each grid point, so that the electric energy distribution information at each grid point in the target structural model corresponding to the semiconductor device to be simulated is determined based on the preset electric energy equation group. The technical solution of this embodiment, when generating grid units for the structural model corresponding to the semiconductor device, the grid generation is performed with the quantum confinement region as the reference benchmark, so that the high-dimensional grid of the device in the semiconductor device model is matched with the low-dimensional grid corresponding to the quantum confinement region, avoiding the performance loss caused by the interpolation between the two grids of different dimensions, and improving the computational efficiency and numerical accuracy of the semiconductor device simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required to describe the embodiments. Obviously, the drawings introduced are only drawings of a part of the embodiments to be described in the present invention, rather than all the drawings. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic flow chart of a simulation method for a semiconductor device including a quantum confinement region provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of the division of a structural model including a quantum confinement region involved in an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of the division of a structural model including two quantum confinement regions involved in an embodiment of the present invention;

[0024] Figure 4 A schematic flow chart of another simulation method for a semiconductor device including a quantum confinement region provided by an embodiment of the present invention;

[0025] Figure 5 A schematic flow chart of another simulation method for a semiconductor device including a quantum confinement region provided by an embodiment of the present invention;

[0026] Figure 6 A schematic structural diagram of a simulation device including a quantum confinement region semiconductor device provided by an embodiment of the present invention;

[0027] Figure 7 The present invention is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Figure 1 A flow chart of a simulation method for a semiconductor device including a quantum confinement region provided in an embodiment of the present invention is provided. This embodiment is applicable to situations where numerical simulation of a semiconductor device including a quantum confinement region is required. The method can be executed by a simulation device, which can be implemented in the form of software and / or hardware. The hardware can be an electronic device, such as a mobile terminal, a PC, or a server.

[0029] like Figure 1 As shown, the simulation method of the semiconductor device including the quantum confinement region includes:

[0030] S110 , dividing the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region.

[0031] Near the interfaces of different materials in many semiconductor devices, due to their small size or drastic changes in the band structure, there will be a quantum confinement effect that has a significant impact on the performance of the device. This specific area is called the quantum confinement region. It should be noted that if the semiconductor device is a three-dimensional device, the quantum confinement region is a two-dimensional surface; if the semiconductor device is a two-dimensional device, the quantum confinement region is a one-dimensional point. In other words, the quantum confinement region must have one less dimension than the semiconductor device.

[0032] The semiconductor device to be simulated is a semiconductor device to be subjected to numerical simulation. The structural model is a model used to characterize the structure of the semiconductor device to be simulated. For example, the structural model corresponding to the semiconductor device to be simulated can be a three-dimensional structural model, and the corresponding quantum confinement region is a two-dimensional surface; the structural model corresponding to the semiconductor device to be simulated can be a two-dimensional structural model, and the corresponding quantum confinement region is a one-dimensional point. The target position information indicates the position of the quantum confinement region in the structural model. The structural model can be split into two or more structural sub-models.

[0033] Specifically, a structural model corresponding to the semiconductor device to be simulated can be drawn in the semiconductor device simulation platform according to the actual spatial shape of the semiconductor device to be simulated. According to the characteristics of the quantum confinement region (the quantum confinement region is located in a narrow transition region), it can be determined which quantum confinement regions are included in the model structure, so that the structural model can be divided into two or more structural sub-models according to the quantum confinement region.

[0034] Optionally, according to target position information of at least one quantum confinement region, the structural model corresponding to the semiconductor device to be simulated is divided into at least two structural sub-models, including: obtaining the structural model corresponding to the semiconductor device to be simulated; in response to a triggering operation on the structural model, determining the triggered position as the target position information of the quantum confinement region; and dividing the structural model based on at least one target position information into at least two structural sub-models.

[0035] In the following embodiments, the structural model corresponding to the semiconductor device to be simulated is a three-dimensional structural model as an example for explanation. On the basis of drawing the structural model corresponding to the semiconductor device to be simulated in the semiconductor device simulation platform, the structural model can be obtained and displayed in the current display page. The user can trigger any position on the structural model in the current display. When a certain position is detected to be clicked, the corresponding position coordinates of the triggered position can be determined as the target position information where the quantum confinement region is located. If the structural model includes multiple quantum confinement regions, the user can perform multiple trigger operations to obtain the target position information corresponding to the multiple quantum confinement regions. Based on this, the cross section corresponding to the target position information can be determined, and the structural model can be divided into two or more structural sub-models based on these cross sections. More specifically, if it is determined that the structural model includes a quantum confinement region, the structural model can be divided into two structural sub-models; if it is determined that the structural model includes two quantum confinement regions, the structural model can be divided into three structural sub-models; if it is determined that the structural model includes three quantum confinement regions, the structural model can be divided into four structural sub-models, ..., and so on.

[0036] For an exemplary schematic diagram of the structural model division including a quantum confinement region, see Figure 2 ,like Figure 2 As shown, a quantum confinement region divides the structural model into structural sub-model A and structural sub-model B. See the schematic diagram of the structural model division including two quantum confinement regions. Figure 3 ,like Figure 3 As shown, the two quantum confinement regions divide the structural model into structural sub-model R, structural sub-model T and structural sub-model Y.

[0037] S120. For the boundary area between structural sub-models adjacent in spatial position, generate at least one low-dimensional grid unit in the boundary area to form a low-dimensional grid, and generate at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtain the target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed.

[0038] The spatial dimension corresponding to the high-dimensional grid is consistent with the spatial dimension of the structural model corresponding to the semiconductor device to be simulated, and the spatial dimension corresponding to the low-dimensional grid is one dimension lower than the high-dimensional grid.

[0039] Among them, the low-dimensional grid unit is the basic unit that constitutes the low-dimensional network. The high-dimensional grid unit is the basic unit that constitutes the high-dimensional network. The low-dimensional grid unit includes at least two grid points and the connecting edges between the grid points, and the high-dimensional grid unit includes at least three grid points and the connecting edges between the grid points. For example, the three-dimensional grid unit can be a triangular prism or a tetrahedron; the two-dimensional grid unit can be a triangular facet, a quadrilateral facet, etc.; the one-dimensional grid unit can be a line. Each vertex in the grid unit can be called a grid point.

[0040] More specifically, if the structural model corresponding to the semiconductor device to be simulated is a two-dimensional structural model, the high-dimensional grid refers to a two-dimensional grid, and the high-dimensional grid unit includes at least 3 grid points and connecting edges between each grid point; the low-dimensional grid refers to a one-dimensional grid, and the low-dimensional grid unit includes at least 2 grid points and connecting edges between each grid point.

[0041] If the structural model corresponding to the semiconductor device to be simulated is a three-dimensional structural model, the high-dimensional grid refers to a three-dimensional grid, and the high-dimensional grid unit includes at least 4 grid points and connecting edges between each grid point. The low-dimensional grid refers to a two-dimensional grid, and the low-dimensional grid unit includes at least 3 grid points and connecting edges between each grid point.

[0042] The target structural model is a model obtained by performing high-dimensional meshing and low-dimensional generation processing on the structural model of the semiconductor device to be simulated.

[0043] Specifically, the following takes the structural model corresponding to the semiconductor device to be simulated as a three-dimensional structural model as an example to illustrate how to generate and construct a low-dimensional grid and a high-dimensional grid to obtain a target structural model corresponding to the semiconductor device to be simulated.

[0044] If the three-dimensional structural model includes a quantum bound surface, multiple reference grid points can be determined on the quantum bound surface, and then connecting edges between these reference grid points can be established to obtain multiple two-dimensional grid units, and these two-dimensional grid units constitute a two-dimensional grid. The structural sub-model with the quantum bound surface as the right side can be called the first structural sub-model, and the structural sub-model with the quantum bound surface as the left side can be called the second structural sub-model. For the first structural sub-model, with the reference grid points on these two-dimensional grids as the generation starting point, multiple three-dimensional grid units are generated to the left to form a three-dimensional grid; for the second structural sub-model, with the reference grid points on these two-dimensional grids as the generation starting point, multiple three-dimensional grid units are generated to the right to form a three-dimensional grid. When all three-dimensional grids and two-dimensional grids are constructed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0045] If the structural model includes two quantum bound surfaces, for each quantum bound surface, multiple reference grid points can be determined on the quantum bound surface, and then the connecting edges between these reference grid points can be established to obtain multiple two-dimensional grid units, which constitute a two-dimensional grid corresponding to each quantum bound surface. For the leftmost structural sub-model, multiple reference grid points on the two-dimensional grid on the right side of the structural sub-model are used as the generation starting point to generate multiple three-dimensional grid units to the left; for the middle structural sub-model, the reference grid points on the two-dimensional grid on the left side of the structural sub-model are used as the generation starting point to generate three-dimensional grid units to the right, and the generation end point of the structural sub-model is made to coincide with the reference grid points on the two-dimensional grid on the right side of the structural sub-model; for the rightmost structural sub-model, multiple reference grid points on the two-dimensional grid on the left side of the structural sub-model are used as the generation starting point to generate multiple three-dimensional grid units to the right. Similarly, when the structural model includes more than two quantum bound surfaces, how to generate and construct low-dimensional grids and high-dimensional grids to obtain the target structural model corresponding to the semiconductor device to be simulated.

[0046] S130 , based on a preset electric energy equation group, determining electric energy distribution information at each grid point in a target structure model corresponding to the semiconductor device to be simulated.

[0047] The preset power equation group is a preset set of equations used to determine power simulation parameters of the semiconductor device to be simulated. The power distribution information includes potential information, electron concentration information and hole concentration information of each grid point.

[0048] In this embodiment, the preset electric energy equation group can be expressed as:

[0049]

[0050] That is, the preset electric energy equation group includes: a first equation (1), a second equation (2), a third equation (3), a fourth equation (4) and a fifth equation (5).

[0051] Where ε represents the permittivity of the material used in the semiconductor device to be simulated, ψ i represents the potential information at the i-th grid point, q represents the charge of the primitive, q = 1.6021892 × 10 -19 C,n i represents the first electron concentration information at the i-th grid point, represents the second electron concentration information at the i-th grid point, p i represents the first hole concentration information at the i-th grid point, represents the second hole concentration information at the i-th grid point, NA represents the concentration of the acceptor dopant of the semiconductor device to be simulated, ND represents the concentration of the donor dopant of the semiconductor device to be simulated, R n The function representing the amount of electrons generated and recombined, R p The function representing the amount of hole generation and recombination, J n A function representing the current intensity of the electrons, J p The function of hole current intensity, C n The function representing the quantum well capture rate of electrons, C p It is a function of the quantum well capture rate of holes. It should be noted that R n , R p , J n J p , C n and C p , all have fixed physical expressions, which will not be repeated here.

[0052] It should be noted that if the structural model corresponding to the semiconductor device to be simulated is a three-dimensional structural model, the first hole concentration information is the hole concentration information corresponding to the three-dimensional grid point, and the second hole concentration information is the hole concentration information corresponding to the two-dimensional grid point; if the structural model corresponding to the semiconductor device to be simulated is a two-dimensional structural model, the first hole concentration information is the hole concentration information corresponding to the two-dimensional grid point, and the second hole concentration information is the hole concentration information corresponding to the one-dimensional grid point.

[0053] In this embodiment, on the basis of obtaining the target structure model corresponding to the semiconductor device to be simulated, certain processing conditions can be given, for example, under a specified voltage, the electric energy distribution information at each grid point in the target structure model is solved by a preset electric energy equation group.

[0054] Optionally, based on a preset electric energy equation group, a specific implementation method for determining the electric energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated may include: for each grid point in the target structure model, if the current grid point is located on a low-dimensional grid, then based on the preset electric energy equation group, solving the electric potential information, first electron concentration information, second electron concentration information, first hole concentration information and second hole concentration information corresponding to the current grid point; if the current grid point is located on a non-low-dimensional grid, then initializing the second electron concentration information and the second hole concentration information in the preset electric energy equation group, and solving the electric potential information, first electron concentration information and first hole concentration information corresponding to the current grid point based on the first equation, the second equation and a third-party formula.

[0055] In this embodiment, the processing process for each grid point is the same, and any one of the grid points is used as the current grid point, and the current grid point is used as an example for exemplary description. If the current grid point is located on a low-dimensional grid, that is, the current grid point is a reference grid point on the quantum confinement surface, then according to the given processing conditions and the preset electric energy equation group (5 equations), the electric potential information, the first electron concentration information, the second electron concentration information, the first hole concentration information, and the second hole concentration information (5 independent variables) corresponding to the current grid point are solved.

[0056] It can be understood that, taking the structural model corresponding to the semiconductor device to be simulated as a three-dimensional structural model as an example, the reference grid point located on the quantum confinement surface is both the grid point corresponding to the corresponding structural sub-model (three-dimensional model) and the grid point corresponding to the quantum confinement surface (two-dimensional surface). Based on this, the first electron concentration information represents the electron concentration distribution information of the current grid point in the corresponding structural sub-model, and the second electron concentration information represents the electron concentration distribution information of the current grid point on the corresponding quantum confinement surface. Similarly, it can be known that the first hole concentration information represents the hole concentration distribution information of the current grid point in the corresponding structural sub-model, and the second hole concentration information represents the hole concentration distribution information of the current grid point on the corresponding quantum confinement surface.

[0057] If the current grid point is located on a non-low-dimensional grid, the second electron concentration information and the second hole concentration information in the preset electric energy equation group may be initialized. For example, the initialization process may include but is not limited to zero initialization process. In this case, the preset electric energy equation group may be expressed as:

[0058]

[0059] Thus, the potential information, the first electron concentration information and the first hole concentration information (3 independent variables) corresponding to the current grid point can be solved according to the given processing conditions and the preset electric energy equation group (3 equations).

[0060] The technical solution of the embodiment of the present invention is to divide the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region, and then, for the boundary region between the structural sub-models adjacent in spatial position, generate at least one low-dimensional grid unit in the boundary region to form a low-dimensional grid, and generate at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtain the target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed, wherein the low-dimensional grid unit includes at least two grid points and the connecting edges between each grid point, and the high-dimensional grid unit includes at least three grid points and the connecting edges between each grid point, so that the electric energy distribution information at each grid point in the target structural model corresponding to the semiconductor device to be simulated is determined based on the preset electric energy equation group. The technical solution of this embodiment, when generating grid units for the structural model corresponding to the semiconductor device, the grid generation is performed with the quantum confinement region as the reference benchmark, so that the high-dimensional grid of the device in the semiconductor device model is matched with the low-dimensional grid corresponding to the quantum confinement region, avoiding the performance loss caused by the interpolation between the two grids of different dimensions, and improving the computational efficiency and numerical accuracy of the semiconductor device simulation.

[0061] Embodiment 2

[0062] Figure 4 A schematic diagram of a simulation method for a semiconductor device including a quantum confinement region provided in an embodiment of the present invention is provided. Based on the above embodiment, S120 is further refined. The specific implementation method thereof can refer to the technical solution of this embodiment. The technical terms that are the same as or corresponding to the above embodiment are not repeated here.

[0063] like Figure 4 As shown, the method specifically comprises the following steps:

[0064] S210 , dividing a structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to target position information of at least one quantum confinement region.

[0065] In this embodiment, when the structural model is a three-dimensional structural model and the semiconductor device to be simulated includes a quantum confinement region, a specific implementation method of determining a target structural model corresponding to the semiconductor device to be simulated is as shown in S220-S240.

[0066] S220 , for a first structural sub-model and a second structural sub-model that are adjacent in spatial position, determining a boundary region between the two structural sub-models as a quantum confinement surface.

[0067] In this embodiment, the first structural sub-model is different from the second structural sub-model. Figure 2, the structural sub-model on the left can be determined as the first structural sub-model, and the structural sub-model on the right can be determined as the second structural sub-model. And the boundary area between these two structural sub-models is determined as the quantum confinement surface.

[0068] S230 , generating at least one two-dimensional grid unit based on a plurality of reference grid points on the quantum confinement surface to form a two-dimensional grid.

[0069] In this embodiment, a plurality of grid reference points may be determined on the quantum confinement surface based on a preset method, for example, the preset method may be: randomly determining a preset number of reference grid points, equidistantly determining a preset number of reference grid points, etc. Further, connecting edges are established between these reference grid points to obtain a plurality of two-dimensional grid units, and these two-dimensional grid units constitute a two-dimensional grid.

[0070] S240, based on the two-dimensional grid, generate at least one three-dimensional grid unit for the first structural sub-model and the second structural sub-model respectively to form a three-dimensional grid, and when all the three-dimensional grids and two-dimensional grids are constructed, a target structural model corresponding to the semiconductor device to be simulated is obtained.

[0071] In this embodiment, multiple reference grid points on the two-dimensional grid can be used as generation starting points to generate multiple three-dimensional grid units for the first structural sub-model and the second structural sub-model respectively. After the grid generation is completed, a target three-dimensional structure model corresponding to the semiconductor device to be simulated is obtained.

[0072] Specifically, based on the two-dimensional grid, a specific implementation method of generating at least one three-dimensional grid unit for the first structural sub-model and the second structural sub-model respectively may include: for the first structural sub-model, taking each reference grid point on the two-dimensional grid as the generation starting point, and generating at least one three-dimensional grid unit for the first structural sub-model along the direction toward the first structural sub-model; for the second structural sub-model, taking each reference grid point on the two-dimensional grid as the generation starting point, and generating at least one three-dimensional grid unit for the second structural sub-model along the direction toward the second structural sub-model.

[0073] On the basis of the above examples, see Figure 2 For the first structural sub-model, each reference grid point on the two-dimensional grid can be used as a generation starting point, and multiple three-dimensional grid units can be generated for the first structural sub-model along the left direction. For the second structural sub-model, each reference grid point on the two-dimensional grid can be used as a generation starting point, and multiple three-dimensional grid units can be generated for the second structural sub-model along the right direction. When all three-dimensional grids and two-dimensional grids are constructed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0074] In particular, if the structural model is a two-dimensional structural model, the semiconductor device to be simulated includes a quantum confinement region, and for the boundary region between the structural sub-models adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary region to form a low-dimensional grid, and based on the low-dimensional grid, at least one high-dimensional grid unit is generated for the adjacent structural sub-models to form a high-dimensional grid. When the grid construction is completed, the target structural model corresponding to the semiconductor device to be simulated is obtained. It can also include: for the first structural sub-model and the second structural sub-model adjacent in spatial position, the boundary region between the two structural sub-models is determined as a quantum confinement line; based on multiple reference grid points on the quantum confinement line, at least one one-dimensional grid unit is generated to form a one-dimensional grid; based on the one-dimensional grid, at least one two-dimensional grid unit is generated for the first structural sub-model and the second structural sub-model to form a two-dimensional grid, and when the grid construction is completed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0075] S250 , based on a preset electric energy equation group, determining electric energy distribution information at each grid point in a target structure model corresponding to the semiconductor device to be simulated.

[0076] According to the technical solution of the embodiment of the present invention, when generating at least one grid unit for each structural sub-model based on the boundary region between the structural sub-models adjacent in spatial position, the semiconductor device to be simulated includes a quantum confinement region, and for the first structural sub-model and the second structural sub-model adjacent in spatial position, the boundary region between the two structural sub-models is determined as a quantum confinement surface, and then, based on multiple reference grid points on the quantum confinement surface, at least one two-dimensional grid unit is generated to form a two-dimensional grid, so that based on the two-dimensional grid, at least one three-dimensional grid unit is generated for the first structural sub-model and the second structural sub-model respectively to form a three-dimensional grid, and when the grid construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The technical solution provided by this embodiment, in the case of including a quantum confinement region, can be used as a reference for grid generation, so that the high-dimensional grid of the device in the semiconductor device model matches the low-dimensional grid corresponding to the quantum confinement region, avoiding the performance loss caused by interpolation between two grids of different dimensions, and improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0077] Embodiment 3

[0078] Figure 5 A schematic diagram of a simulation method for a semiconductor device including a quantum confinement region provided in an embodiment of the present invention is provided. Based on the above embodiment, S120 is further refined. The specific implementation method thereof can refer to the technical solution of this embodiment. The technical terms that are the same as or corresponding to the above embodiment are not repeated here.

[0079] like Figure 5 As shown, the method specifically comprises the following steps:

[0080] S310 , dividing a structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to target position information of at least one quantum confinement region.

[0081] In this embodiment, when the structural model is a three-dimensional structural model and the semiconductor device to be simulated includes two or more quantum confinement regions, a specific implementation method of determining the target structural model corresponding to the semiconductor device to be simulated is as S320-S240.

[0082] S320, for each structural sub-model, determining the boundary region between two structural sub-models adjacent in spatial position as a quantum bound surface, and determining a plurality of reference grid points on each quantum bound surface to form a two-dimensional grid.

[0083] In this embodiment, for each structural sub-model included in the structural model, the boundary region between each pair of two structural sub-models adjacent in spatial position can be determined as a quantum bounding surface, thereby obtaining multiple quantum bounding surfaces. Figure 3 , a first quantum confinement surface between the structural sub-model R and the structural sub-model T, and a second quantum confinement surface between the structural sub-model T and the structural sub-model Y can be obtained. Furthermore, a plurality of reference grid points can be determined on each quantum confinement surface based on a preset method, and then connecting edges between these reference grid points can be established to obtain a plurality of two-dimensional grid units, which constitute a two-dimensional grid corresponding to each quantum confinement surface.

[0084] S330 : For the third structural sub-model on the first side, based on the reference grid points of the two-dimensional grid corresponding to the third structural sub-model, generate a plurality of three-dimensional grid units for the third structural sub-model.

[0085] In this embodiment, for the third structural sub-model located at the first edge side, a reference grid point on the quantum confinement surface corresponding to the third structural sub-model can be used as a generation starting point, and multiple three-dimensional grid units can be generated for the third structural sub-model along the direction toward the third structural sub-model. Figure 3 For the leftmost structural sub-model R, each reference grid point on the first quantum confinement surface (two-dimensional grid) can be used as a generating starting point, and multiple three-dimensional grid units can be generated for the structural sub-model R along the left direction.

[0086] S340 . For the fourth structural sub-model on the second side, based on reference grid points on the two-dimensional grid corresponding to the fourth structural sub-model, generate a plurality of three-dimensional grid units for the fourth structural sub-model.

[0087] In this embodiment, for the fourth structural sub-model located on the second edge side, the reference grid point on the two-dimensional grid corresponding to the fourth structural sub-model can be used as the generation starting point, and multiple four-dimensional grid units are generated for the fourth structural sub-model along the direction toward the fourth structural sub-model. Figure 3 For the rightmost structural sub-model Y, each reference grid point on the second quantum confinement surface (two-dimensional grid) can be used as a starting point to generate multiple three-dimensional grid units for the structural sub-model Y along the right direction.

[0088] S350: For each intermediate structural sub-model located between two structural sub-models, generate at least one grid unit for the intermediate structural sub-model based on reference grid points on two two-dimensional grids corresponding to the intermediate structural sub-model.

[0089] In this embodiment, for each intermediate structure sub-model, a reference grid point on a two-dimensional grid on one side of the intermediate structure sub-model is used as a generation starting point, and three-dimensional grid units are generated in the direction of the other side, and the generation end point of the intermediate structure sub-model is made to coincide with the reference grid point on the two-dimensional grid on the other side of the intermediate structure sub-model. Figure 3 For the structural sub-model T between the structural sub-model R and the structural sub-model Y, the reference grid points on the first quantum confinement surface (two-dimensional grid) can be used as the generation starting point to generate three-dimensional grid units to the right, and the generation end point of the structural sub-model T can be made to coincide with the reference grid points on the second quantum confinement surface (two-dimensional grid).

[0090] S360: When each structural sub-model completes mesh generation, a target structural model corresponding to the semiconductor device to be simulated is obtained.

[0091] In particular, if the structural model is a two-dimensional structural model, the semiconductor device to be simulated includes at least two quantum confinement regions, for the boundary region between the structural sub-models adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary region to form a low-dimensional grid, and at least one high-dimensional grid unit is generated for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and when the grid construction is completed, the target structural model corresponding to the semiconductor device to be simulated is obtained, which may also include: for each structural sub-model, determining the boundary region between two structural sub-models adjacent in spatial position as a quantum confinement line, and determining a plurality of reference grid points on each quantum confinement line to form one-dimensional grid; for the third structural sub-model on the first side, based on the reference grid points on the one-dimensional grid corresponding to the third structural sub-model, generate multiple two-dimensional grid units for the third structural sub-model; for the fourth structural sub-model on the second side, based on the reference grid points on the one-dimensional grid corresponding to the fourth structural sub-model, generate multiple two-dimensional grid units for the fourth structural sub-model; for each intermediate structural sub-model located between the two structural sub-models, based on the reference grid points on the two one-dimensional grids corresponding to the intermediate structural sub-models, generate multiple two-dimensional grid units for the intermediate structural sub-model; when each structural sub-model completes grid generation, a target structural model corresponding to the semiconductor device to be simulated is obtained.

[0092] S370, based on the preset electric energy equation group, determine the electric energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated.

[0093] According to the technical solution of the embodiment of the present invention, when generating at least one grid unit for each structural sub-model based on the boundary region between the structural sub-models adjacent in spatial position, for each structural sub-model, the boundary region between the two structural sub-models adjacent in spatial position is determined as a quantum bound surface, and multiple reference grid points are determined on each quantum bound surface to form a two-dimensional grid; for the third structural sub-model on the first side, based on the reference grid points on the two-dimensional grid corresponding to the third structural sub-model, multiple three-dimensional grid units are generated for the third structural sub-model; for the fourth structural sub-model on the second side, based on the reference grid points on the two-dimensional grid corresponding to the fourth structural sub-model, multiple three-dimensional grid units are generated for the fourth structural sub-model; for each intermediate structural sub-model located between the two structural sub-models, based on the reference grid points on the two two-dimensional grids corresponding to the intermediate structural sub-model, multiple three-dimensional grid units are generated for the intermediate structural sub-model; when the grid generation of each structural sub-model is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The technical solution provided in this embodiment, when including at least quantum confinement regions, can generate a grid based on each quantum confinement region as a reference, so that the high-dimensional grid of the device in the semiconductor device model matches the low-dimensional grid corresponding to the quantum confinement region, avoiding the performance loss caused by interpolation between grids of two different dimensions, and further improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0094] Embodiment 4

[0095] Figure 6 A schematic structural diagram of a simulation device for a quantum confinement region semiconductor device provided by an embodiment of the present invention includes: a sub-model division module 410 , a grid unit generation module 420 and a model simulation module 430 .

[0096] The sub-model division module 410 is used to divide the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region;

[0097] A grid unit generating module 420 is used to generate at least one low-dimensional grid unit in the boundary area between the structural sub-models adjacent in spatial position to form a low-dimensional grid, and to generate at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and to obtain a target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed; wherein the low-dimensional grid unit includes at least two grid points and connecting edges between the grid points, and the high-dimensional grid unit includes at least three grid points and connecting edges between the grid points;

[0098] The model simulation module 430 is used to determine the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated based on the preset power equation group.

[0099] Based on the above device, optionally, the sub-model division module 410 includes:

[0100] A structural model acquisition unit, used to acquire a structural model corresponding to the semiconductor device to be simulated;

[0101] A target position determination unit, configured to determine the triggered position as target position information where the quantum confinement region is located in response to a triggering operation on the structural model;

[0102] The sub-model division unit is used to divide the structure model into at least two structure sub-models based on at least one target position information.

[0103] Based on the above device, optionally, the structural model is a three-dimensional structural model, the semiconductor device to be simulated includes a quantum confinement region, and the grid unit generation module 420 includes:

[0104] A quantum bound surface determination unit is used to determine, for a first structure sub-model and a second structure sub-model adjacent in spatial position, a boundary region between the two structure sub-models as a quantum bound surface;

[0105] A two-dimensional grid generation unit, used to generate at least one two-dimensional grid unit based on a plurality of reference grid points on the quantum confinement surface to form a two-dimensional grid;

[0106] A grid unit generating unit is used to generate at least one three-dimensional grid unit for the first structural sub-model and the second structural sub-model based on the two-dimensional grid to form a three-dimensional grid, and obtain a target structure model corresponding to the semiconductor device to be simulated when the grid construction is completed.

[0107] Based on the above device, optionally, the grid unit generation unit is specifically used to generate at least one three-dimensional grid unit for the first structural sub-model, taking each reference grid point on the two-dimensional grid as a generation starting point, along the direction toward the first structural sub-model; and to generate at least one three-dimensional grid unit for the second structural sub-model, taking each reference grid point on the two-dimensional grid as a generation starting point, along the direction toward the second structural sub-model.

[0108] Based on the above device, optionally, the structural model is a three-dimensional structural model, the semiconductor device to be simulated includes at least two quantum confinement regions, and the grid unit generation module 420 further includes:

[0109] A two-dimensional grid determination unit is used to determine, for each of the structural sub-models, a boundary region between two of the structural sub-models that are adjacent in spatial position as a quantum bound surface, and determine a plurality of reference grid points on each of the quantum bound surfaces to form a two-dimensional grid;

[0110] A first generating unit is configured to generate, for a third structural sub-model on the first side, a plurality of three-dimensional grid units for the third structural sub-model based on the reference grid points on the two-dimensional grid corresponding to the third structural sub-model;

[0111] A second generating unit is configured to generate, for a fourth structural sub-model on a second side, a plurality of three-dimensional grid units for the fourth structural sub-model based on the reference grid points on the two-dimensional grid corresponding to the fourth structural sub-model;

[0112] A third generating unit is configured to generate, for each intermediate structural sub-model located between two structural sub-models, a plurality of three-dimensional grid units for the intermediate structural sub-model based on the reference grid points on the two two-dimensional grids corresponding to the intermediate structural sub-model;

[0113] The target model determination unit is used to obtain a target structure model corresponding to the semiconductor device to be simulated when each structure sub-model completes mesh generation.

[0114] Based on the above device, optionally, the preset electric energy equation group includes:

[0115] First formula:

[0116] Second equation:

[0117] The third equation:

[0118] The fourth formula:

[0119] The fifth equation:

[0120] Where ε represents the permittivity of the material used in the semiconductor device to be simulated, ψ i represents the potential information at the i-th grid point, q represents the charge of the primitive, q = 1.6021892 × 10 -19 C,n i represents the first electron concentration information at the i-th grid point, represents the second electron concentration information at the i-th grid point, p i represents the first hole concentration information at the i-th grid point, represents the second hole concentration information at the i-th grid point, NA represents the concentration of the acceptor dopant of the semiconductor device to be simulated, ND represents the concentration of the donor dopant of the semiconductor device to be simulated, R n The function representing the amount of electrons generated and recombined, R p The function representing the amount of hole generation and recombination, J n A function representing the current intensity of the electrons, J p The function of hole current intensity, C n The function representing the quantum well capture rate of electrons, C p A function representing the quantum well capture rate of holes.

[0121] On the basis of the above-mentioned device, optionally, a model simulation module 430 is specifically used for solving the electric potential information, the first electron concentration information, the second electron concentration information, the first hole concentration information and the second hole concentration information corresponding to the current grid point based on the preset electric energy equation group for each grid point in the target structure model if the current grid point is located on a low-dimensional grid; if the current grid point is located on a non-low-dimensional grid, the second electron concentration information and the second hole concentration information in the preset electric energy equation group are initialized, and the electric potential information, the first electron concentration information and the first hole concentration information corresponding to the current grid point are solved based on the first equation, the second equation and the third-party program.

[0122] The technical solution of the embodiment of the present invention is to divide the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region, and then, for the boundary region between the structural sub-models adjacent in spatial position, generate at least one low-dimensional grid unit in the boundary region to form a low-dimensional grid, and generate at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtain the target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed, wherein the low-dimensional grid unit includes at least two grid points and the connecting edges between each grid point, and the high-dimensional grid unit includes at least three grid points and the connecting edges between each grid point, so that the electric energy distribution information at each grid point in the target structural model corresponding to the semiconductor device to be simulated is determined based on the preset electric energy equation group. The technical solution of this embodiment, when generating grid units for the structural model corresponding to the semiconductor device, the grid generation is performed with the quantum confinement region as the reference benchmark, so that the high-dimensional grid of the device in the semiconductor device model is matched with the low-dimensional grid corresponding to the quantum confinement region, avoiding the performance loss caused by the interpolation between the two grids of different dimensions, and improving the computational efficiency and numerical accuracy of the semiconductor device simulation.

[0123] The simulation device of the semiconductor device including the quantum confinement region provided by the embodiment of the present invention can execute the simulation method of the semiconductor device including the quantum confinement region provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0124] It is worth noting that the various units and modules included in the above system are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the embodiments of the present invention.

[0125] Embodiment 5

[0126] Figure 7 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0127] like Figure 7 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0128] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0129] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a target control object posture control method.

[0130] In some embodiments, the target control object posture control method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the target control object posture control method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the target control object posture control method by any other appropriate means (e.g., by means of firmware).

[0131] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0132] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0133] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0134] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0135] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0136] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0137] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0138] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

[0139] Embodiment 6

[0140] An embodiment of the present invention further provides a storage medium containing computer executable instructions, which, when executed by a computer processor, is used to perform a simulation method of a semiconductor device containing a quantum confinement region, the method comprising:

[0141] According to target position information of at least one quantum confinement region, the structural model corresponding to the semiconductor device to be simulated is divided into at least two structural sub-models;

[0142] For the boundary area between the structural sub-models that are adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary area to form a low-dimensional grid, and at least one high-dimensional grid unit is generated for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and when the grid construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained; wherein the low-dimensional grid unit includes at least two grid points and connecting edges between each of the grid points, and the high-dimensional grid unit includes at least three grid points and connecting edges between each of the grid points;

[0143] Based on a preset electric energy equation group, electric energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated is determined.

[0144] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0145] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0146] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0147] Computer program code for performing the operation of embodiments of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0148] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A simulation method for a semiconductor device including a quantum confinement region, comprising: According to target position information of at least one quantum confinement region, the structural model corresponding to the semiconductor device to be simulated is divided into at least two structural sub-models; For the boundary area between the structural sub-models that are adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary area to form a low-dimensional grid, and at least one high-dimensional grid unit is generated for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and when the grid construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained; wherein the low-dimensional grid unit includes at least two grid points and connecting edges between each of the grid points, and the high-dimensional grid unit includes at least three grid points and connecting edges between each of the grid points; Based on a preset electric energy equation group, electric energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated is determined.

2. The method according to claim 1, characterized in that The method of dividing the structure model corresponding to the semiconductor device to be simulated into at least two structure sub-models according to the target position information of at least one quantum confinement region, comprises: Obtaining a structural model corresponding to the semiconductor device to be simulated; In response to a triggering operation on the structural model, determining the triggered position as target position information where the quantum confinement region is located; The structure model is divided into at least two structure sub-models based on at least one of the target position information.

3. The method according to claim 1, characterized in that The structural model is a three-dimensional structural model, the semiconductor device to be simulated includes a quantum confinement region, the boundary region between the structural sub-models adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary region to form a low-dimensional grid, and at least one high-dimensional grid unit is generated for each of the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and when the grid construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained, including: For a first structural sub-model and a second structural sub-model adjacent in spatial position, a boundary region between the two structural sub-models is determined as a quantum bound surface; Based on a plurality of reference grid points on the quantum confinement surface, generating at least one two-dimensional grid unit to form a two-dimensional grid; Based on the two-dimensional grid, at least one three-dimensional grid unit is generated for the first structural sub-model and the second structural sub-model respectively to form a three-dimensional grid, and when the grid construction is completed, a target structure model corresponding to the semiconductor device to be simulated is obtained.

4. The method according to claim 3, characterized in that The generating at least one three-dimensional grid unit for the first structural sub-model and the second structural sub-model based on the two-dimensional grid respectively comprises: For the first structural sub-model, taking each of the reference grid points on the two-dimensional grid as a generation starting point, and generating at least one three-dimensional grid unit for the first structural sub-model along a direction toward the first structural sub-model; For the second structural sub-model, each of the reference grid points on the two-dimensional grid is used as a generation starting point, and at least one three-dimensional grid unit is generated for the second structural sub-model along a direction toward the second structural sub-model.

5. The method according to claim 1, characterized in that The structural model is a three-dimensional structural model, the semiconductor device to be simulated includes at least two quantum confinement regions, the boundary region between the structural sub-models adjacent in spatial position, at least one low-dimensional grid unit is generated in the boundary region to form a low-dimensional grid, and at least one high-dimensional grid unit is generated for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and when the grid construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained, including: For each of the structural sub-models, a boundary region between two of the structural sub-models that are adjacent in spatial position is determined as a quantum bound surface, and a plurality of reference grid points are determined on each of the quantum bound surfaces to form a two-dimensional grid; For the third structural sub-model on the first side, based on the reference grid points on the two-dimensional grid corresponding to the third structural sub-model, generate a plurality of three-dimensional grid units for the third structural sub-model; For the fourth structural sub-model on the second side, based on the reference grid points on the two-dimensional grid corresponding to the fourth structural sub-model, generate a plurality of three-dimensional grid units for the fourth structural sub-model; For each intermediate structural sub-model located between two structural sub-models, generating a plurality of three-dimensional grid units for the intermediate structural sub-model based on the reference grid points on the two two-dimensional grids corresponding to the intermediate structural sub-model; When the mesh generation of each structural sub-model is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained.

6. The method according to claim 1, characterized in that The preset electric energy equation group includes: First formula: Second equation: The third equation: The fourth formula: The fifth equation: Where ε represents the permittivity of the material used in the semiconductor device to be simulated, ψi represents the potential information at the i-th grid point, q represents the charge of the primitive, q = 1.602189210-19C, n i represents the first electron concentration information at the i-th grid point, represents the second electron concentration information at the i-th grid point, pi represents the first hole concentration information at the i-th grid point, represents the second hole concentration information at the i-th grid point, NA represents the concentration of the acceptor dopant of the semiconductor device to be simulated, ND represents the concentration of the donor dopant of the semiconductor device to be simulated, R n represents the function of the amount of electrons generated and the amount of recombination, Rp represents the function of the amount of holes generated and the amount of recombination, J n represents the function of the electron current intensity, Jp represents the function of the hole current intensity, C n Cp is a function of the quantum well capture rate of electrons and Cp is a function of the quantum well capture rate of holes.

7. The method according to claim 6, characterized in that The step of determining the electric energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated based on a preset electric energy equation group includes: For each grid point in the target structure model, if the current grid point is located on a low-dimensional grid, solving the electric potential information, the first electron concentration information, the second electron concentration information, the first hole concentration information, and the second hole concentration information corresponding to the current grid point based on the preset electric energy equation group; If the current grid point is located on a non-low-dimensional grid, the second electron concentration information and the second hole concentration information in the preset electric energy equation group are initialized, and based on the first equation, the second equation and the third-party program, the potential information, the first electron concentration information and the first hole concentration information corresponding to the current grid point are solved.

8. A simulation device comprising a quantum confinement region semiconductor device, characterized in that: The device includes: A sub-model division module, used for dividing the structural model corresponding to the semiconductor device to be simulated into at least two structural sub-models according to the target position information of at least one quantum confinement region; A grid unit generation module, for generating at least one low-dimensional grid unit in the boundary area between the structural sub-models adjacent in spatial position to form a low-dimensional grid, and generating at least one high-dimensional grid unit for the adjacent structural sub-models based on the low-dimensional grid to form a high-dimensional grid, and obtaining a target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed; wherein the low-dimensional grid unit includes at least two grid points and connecting edges between each of the grid points, and the high-dimensional grid unit includes at least three grid points and connecting edges between each of the grid points; The model simulation module is used to determine the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated based on a preset power equation group.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the simulation method of a semiconductor device including a quantum confinement region according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the simulation method of a semiconductor device containing a quantum confinement region according to any one of claims 1 to 7 when the processor executes the computer instructions.

Images