Semiconductor device and method for manufacturing semiconductor device
By forming an oxidized film layer in a semiconductor device, the problem of insufficient quality performance of the nanosheet spacer or side spacer film is solved, the parasitic capacitance is reduced, and the insulation and electrical characteristics of the device are improved.
Patent Information
- Application Number
- CN202380032112.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-03-29
- Filing Date
- 2023-03-29
- Publication Date
- 2025-01-10
AI Technical Summary
The film quality performance of the inner spacer or side spacer of the nanosheet in existing semiconductor devices is insufficient, resulting in a high parasitic capacitance between the gate and the source and the drain, affecting the electrical characteristics and reliability of the device.
By alternately stacking the sacrificial layer and channel areas on the substrate, the stack layer is grown, forming a sacrificial polysilicon gate and an inner spacer or a side spacer, and heat treatment is performed in a chamber with preset process pressure and temperature to form an oxidized film layer To improve membrane quality.
The thickness uniformity and stability of the inner spacer or side spacer are improved, the parasitic capacitance is reduced, and the insulation and electrical characteristics of semiconductor devices are improved.
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Figure CN119302056A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art
[0002] Semiconductor devices are mainly used as components of devices similar to electronic circuits that utilize the conductive properties of semiconductors. Semiconductors can be divided into memory semiconductors and non-memory semiconductors. Memory semiconductors can be divided into volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM) and non-volatile memories such as mask read-only memory (Mask ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory.
[0003] In order to miniaturize semiconductor devices, new processes and semiconductor devices with corresponding new structures are being developed. A representative example is the gate-all-around (GAA) process. According to the gate-all-around process, since the gate and the channel are in contact on four sides, the flow of current can be accurately controlled, thus overcoming the limitations of existing semiconductor devices.
[0004] Recently, in order to solve the shortcomings of the all-around gate structure, a multi-bridge channel field effect transistor (MBCFET) has been disclosed as a new structure. According to the multi-bridge channel field effect transistor structure, since the channel region is formed in a nanosheet form, the actual area of contact between the gate and the channel increases, and therefore, the amount of current flowing between the gate and the channel also increases. Summary of the invention
[0005] Technical issues
[0006] An object of the present invention is to improve the film quality performance of an inner spacer or a side spacer included in a semiconductor device including a nanosheet.
[0007] The purpose of this specification is not limited to the above purpose, and other purposes and advantages of this specification not mentioned are more clearly understood through the embodiments of this specification described below. In addition, the purposes and advantages of this specification can be achieved through the structural elements and their combinations recorded in the scope of protection of the invention.
[0008] Technical Solution
[0009] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the following steps: alternately stacking sacrificial layers and channel regions on a substrate to grow a stack layer; forming a sacrificial polysilicon gate on the stack layer; forming an inner spacer and a side spacer on the side of the sacrificial layer and the side of the sacrificial polysilicon gate; and performing heat treatment on the inner spacer or the side spacer in a chamber set to a preset process pressure and a preset process temperature.
[0010] A semiconductor device according to an embodiment of the present invention may include: a substrate; a channel region, including a plurality of nanosheets stacked on the substrate; a gate electrode in contact with at least one side of the channel region; a source region and a drain region, respectively disposed on both sides of the channel region; a side spacer, disposed on a side of the gate electrode; and an inner spacer, disposed on a side of the gate electrode, an oxide film layer may be formed on an outer surface of the side spacer or the inner spacer, and the oxide film layer is formed by heat treatment performed in a chamber set to a preset process pressure and a preset process temperature.
[0011] Effects of the Invention
[0012] According to the method for manufacturing a semiconductor device according to an embodiment of the present invention, the film quality performance of the inner spacer or the side spacer of the semiconductor device can be improved. That is, since the thickness of the inner spacer or the side spacer becomes uniform and the stability is improved, the insulation of the inner spacer or the side spacer can be improved. Therefore, since the parasitic capacitance between the gate electrode and the source region and the drain region is reduced, the electrical characteristics and reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
[0014] Figure 2a to Figure 2g A manufacturing process of a semiconductor device according to an embodiment of the present invention is shown.
[0015] Figure 3 The flowchart is a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0016] Figures 4a to 4e A manufacturing process of a semiconductor device according to another embodiment of the present invention is shown.
[0017] Figure 5 FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.
[0018] Figure 6 The graph shows leakage current values measured when voltage is applied to a semiconductor device manufactured according to the conventional technology and a semiconductor device manufactured according to the embodiment of the present specification. DETAILED DESCRIPTION
[0019] With reference to the accompanying drawings, the above-mentioned objects, features and advantages will be described in detail, so that ordinary technicians in the technical field to which this specification belongs can easily implement the embodiments of this specification. In the process of describing this specification, if it is determined that the specific description of the relevant known technology makes the subject of this specification unclear, the detailed description thereof will be omitted. Below, with reference to the accompanying drawings, the preferred embodiments of this specification will be described in detail. In the accompanying drawings, the same reference numerals represent the same or similar structural elements.
[0020] In this specification, "nanosheet" means a conductive structure having a cross-section substantially perpendicular to the direction of current flow through the nanosheet. Also, within a nanosheet, one of the Cartesian cross-sectional dimensions is significantly smaller than the other dimensions. For example, a nanosheet may include a conductive structure having a cross-sectional area ranging from a few nm to about 20 nm in one of the Cartesian cross-sectional dimensions and from about 15 nm to about 70 nm in the other Cartesian cross-sectional dimensions.
[0021] Figure 1 FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
[0022] Reference Figure 1 The semiconductor device 10 according to an embodiment of the present invention may include substrates 110 and 120, a source region 210, a drain region 220, a gate electrode 370, a channel region 150, a channel region 160, a side spacer 180, and an inner spacer 190.
[0023] The base substrate layer 110 may be a single crystal substrate. The base substrate layer 110 may have a single crystal semiconductor layer on at least one surface. The single crystal semiconductor layer may be composed of one of silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), indium antimonide (InSb), gallium arsenide (GaAs), gallium phosphide (GaP), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb) and indium phosphide (InP), but is not limited thereto.
[0024] The buffer substrate layer 120 may be formed by epitaxial growth on the base substrate layer 110. The buffer substrate layer 120 may be formed by doping the base substrate layer 110 with impurities having a material different from that of the base substrate layer 110.
[0025] The buffer substrate layer 120 may have a different lattice constant from the base substrate layer 110 to minimize lattice stress. According to an embodiment, the lattice constant and crystal structure of the buffer substrate layer 120 may be substantially the same as those of the base substrate layer 110 .
[0026] The lattice constant of the buffer substrate layer 120 may be different from layer to layer. For example, the lattice constant of the buffer substrate layer 120 may be larger from the bottom layer to the top layer.
[0027] The source region 210 and the drain region 220 may be disposed at both ends of the channel regions 150 and 160 , respectively.
[0028] The gate electrodes 340 and 370 may control the flow of current through the channel regions 150 and 160. The gate electrodes 340 and 370 may be disposed between the source region 210 and the drain region 220. The gate electrodes 340 and 370 may surround the channel regions 150 and 160, i.e., the upper surface, lower surface, and side surface of the base nanosheet 150 and the nanosheet 160, that is, they may contact the upper surface, lower surface, and side surface of the base nanosheet 150 and the nanosheet 160, respectively.
[0029] The base gate insulating film 130 can prevent parasitic coupling of the substrates 110 and 120 caused by the gate electrodes 340 and 370. The base gate insulating film 130 can prevent a channel with poor conductivity from being formed in the substrates 110 and 120 during the conduction process of the semiconductor device 10. Figure 1 In the embodiment, the base gate insulating film 130 may be provided at the lower portion of the gate electrode 340 located at the lowermost portion. According to an embodiment, the base gate insulating film 130 may also be omitted.
[0030] The channel regions 150 and 160 may include a base nanosheet 150 disposed on the lowermost surface and at least one nanosheet 160 stacked on the upper portion of the base nanosheet 150. In one embodiment, the channel regions 150 and 160 may be spaced apart from each other in a vertical direction and stacked side by side with the gate electrodes 340 and 370. The channel regions 150 and 160 may be disposed between the source region 210 and the drain region 220. The number of nanosheets 160 included in the channel regions 150 and 160 may vary according to the embodiment.
[0031] The channel regions 150 and 160 may also be defined as conductive structures having a cross section perpendicular to the current flow direction. The base nanosheets 150 and 160 may be composed of a material doped with conductive impurities. For example, the base nanosheets 150 and 160 may include III-IV semiconductor materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and indium gallium arsenide (InGaAs).
[0032] The base nanosheet 150 and the nanosheet 160 may be spaced apart from each other in the vertical direction. The base nanosheet 150 and the nanosheet 160 may be in the shape of a plate, and the length in the horizontal direction may be relatively larger than the thickness in the vertical direction.
[0033] The inner spacer 190 can reduce parasitic capacitance between the gate electrode 340 and the source region 210 and the drain region 220 .
[0034] The inner spacer 190 may be disposed at a side of the gate electrode 340. Therefore, the source region 210 and the drain region 220 may be separated from the gate electrode 340. The inner spacer 190 may be in contact with the channel regions 150, 160.
[0035] An oxide film layer 191 may be formed on the outer surface of the inner spacer 190. In one embodiment, the outer surface of the inner spacer 190 may be oxidized by performing a heat treatment on the outer surface of the inner spacer 190, thereby forming the oxide film layer 191. The oxide film layer 191 may improve the film quality performance of the inner spacer 190. By forming the oxide film layer 191, defects of the inner spacer 190 may be reduced and the quality of the inner spacer 190 may be improved.
[0036] The side spacer 180 may be formed to surround a portion or all of the side surface of the gate electrode 370. The side spacer 180 may separate the source region 210 and the drain region 220 from the gate electrode 370. In one embodiment, a heat treatment may be performed on the side spacer 180 to form an oxide film layer on the outer surface of the side spacer 180. The oxide film layer may improve the film quality performance of the side spacer 180. By forming the oxide film layer, defects of the side spacer 180 may be reduced and the quality of the side spacer 180 may be improved.
[0037] Figure 2a to Figure 2g A manufacturing process of a semiconductor device according to an embodiment of the present invention is shown. Figure 3 The flowchart is a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0038] Reference Figure 3 The manufacturing method of a semiconductor device of an embodiment may include a stack layer growth step a1, a sacrificial polysilicon gate and side spacer formation step b1, a side groove formation step c1, an inner spacer formation step d1, and an oxide film layer formation step e1. Further, the manufacturing method of a semiconductor device of an embodiment may also include a source region and a drain region growth step f1 and an interface film formation step g1.
[0039] Reference Figure 2aIn the stacked layer growth step a1, first, a base gate insulating film 130 may be stacked on the substrates 110 and 120. According to an embodiment, the stacking of the base gate insulating film 130 may also be omitted. Next, stacked layers, namely, sacrificial layers 140 and channel regions 150 and 160, may be alternately stacked on the base gate insulating film 130. The sacrificial layers 140 and the channel regions 150 and 160 may be formed epitaxially.
[0040] In one embodiment, the sacrificial layer 140 may include silicon germanium (SiGe), and the channel regions 150 and 160 may include silicon (Si).
[0041] Reference Figure 2b In the sacrificial polysilicon gate and side spacer forming step b1, a sacrificial polysilicon gate 170 and a side spacer 180 may be formed on the stack layer, ie, the sacrificial layer 140 and the upper portion of the channel regions 150 and 160, respectively.
[0042] The sacrificial polysilicon gate 170 may include silicon, such as polysilicon (Poly-Si). The side spacers 180 may include a dielectric material, such as silicon nitride. The side spacers 180 may include a low dielectric material (or low-k material).
[0043] Reference Figure 2c In the side groove forming step c1, the side groove may be formed by selectively removing a portion of the sacrificial layer 140 and the base gate insulating film 130. In the side groove forming step c1, a portion of the sacrificial layer 140 and the base gate insulating film 130 may be removed by wet etching or dry etching, and may be removed by selective etching.
[0044] The sacrificial layer 140 and the base gate insulating film 130 may have a higher selective etching ratio with respect to the channel regions 150 and 160. Therefore, when the sacrificial layer 140 and the base gate insulating film 130 are removed, the channel regions 150 and 160 may not be removed.
[0045] If the stacking process of the base gate insulating film 130 is omitted in the stack layer growing step a1 , only a portion of the sacrificial layer 140 may be selectively removed in the side groove forming step c1 .
[0046] Reference Figure 2d In the inner spacer forming step d1, the inner spacer 190 may be formed in the side groove formed in the side groove forming step c1. In one embodiment, the inner spacer 190 may be formed by atomic layer deposition (ALD). The inner spacer 190 may include a low dielectric material (or low-k material).
[0047] Reference Figure 2eIn the oxide film layer forming step e1 , heat treatment may be performed on the inner spacer 190 .
[0048] More specifically, in the oxide film layer forming step e1, the inner spacer 190 may be subjected to a heat treatment in a chamber set to a preset process pressure and a preset process temperature. In one embodiment, the preset process pressure may be determined within a range of 2 atmospheres to 100 atmospheres. In one embodiment, the preset process temperature may be determined within a range of 200° C. to 600° C.
[0049] When the heat treatment is performed in the oxide film layer forming step e1, an ambient gas may be supplied into the chamber. In one embodiment, the ambient gas may be O2 or H2O. In one embodiment, the concentration of the ambient gas in the chamber may be 100%.
[0050] In one embodiment, the heat treatment performed in the oxide film layer forming step e1 may be performed in any one of a wet environment, a dry environment, or a supercritical environment.
[0051] Reference Figure 2f In the source region and drain region growth step f1, the source region 210 and the drain region 220 can be formed on both sides of the stack layer, i.e., the sacrificial layer 140 and the channel regions 150 and 160. In addition, in the source region and drain region growth step f1, the sacrificial layer 140 and the sacrificial polysilicon gate 170 can be removed by selective etching.
[0052] Reference Figure 2g In the interface film forming step g1, gate electrodes 340 and 370 containing metal components may be formed in the regions where the sacrificial layer 140 and the sacrificial polysilicon gate 170 are removed. An interface film containing oxide may be formed on the outer surfaces of the gate electrodes 340 and 370.
[0053] According to an embodiment, the source region 210 and the drain region 220 may also be formed after removing the sacrificial layer 140 and the sacrificial polysilicon gate 170 and forming the gate electrodes 340 and 370 .
[0054] Figures 4a to 4e The manufacturing process of the semiconductor device according to another embodiment of the present invention is shown. Figure 5 FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.
[0055] Reference Figure 5, the manufacturing method of the semiconductor device of another embodiment of the present invention may include a stack layer growth step a2, a sacrificial polysilicon gate formation step b2, a mask formation step c2, a groove formation step d2, a spacer material layer formation step e2, a side spacer and inner spacer formation step f2, and an oxide film layer formation step g2. Further, the manufacturing method of the semiconductor device of another embodiment of the present invention may also include a source region and a drain region growth step h2 and an interface film formation step i2.
[0056] Reference Figure 4a In the stacked layer growth step a2, first, a base gate insulating film 130 may be stacked on the substrates 110 and 120. According to an embodiment, the stacking of the base gate insulating film 130 may also be omitted. Then, stacked layers, namely, sacrificial layers 140 and channel regions 150 and 160, may be alternately stacked on the base gate insulating film 130. The sacrificial layers 140 and the channel regions 150 and 160 may be formed epitaxially.
[0057] In one embodiment, the sacrificial layer 140 may include silicon germanium (SiGe), and the channel regions 150 and 160 may include silicon (Si).
[0058] Reference Figure 4a In the sacrificial polysilicon gate forming step b2, a sacrificial polysilicon gate 170 may be formed on the stack layer, i.e., the sacrificial layer 140 and the upper portion of the channel regions 150 and 160. The sacrificial polysilicon gates 170 may be formed to be separated from each other. The sacrificial polysilicon gates 170 may include silicon, for example, polysilicon (Poly-Si).
[0059] Reference Figure 4a In the mask forming step c2 , a mask 171 may be formed on an upper portion of the sacrificial polysilicon gate 170 .
[0060] Reference Figure 4b In the groove forming step d2, the groove may be formed by selectively removing a portion of the sacrificial layer 140 and the base gate insulating film 130. In the groove forming step d2, a portion of the sacrificial layer 140 and the base gate insulating film 130 may be removed by wet etching or dry etching, and may be removed by selective etching.
[0061] The sacrificial layer 140 and the base gate insulating film 130 may have a higher selective etching ratio with respect to the channel regions 150 and 160. Therefore, when the sacrificial layer 140 and the base gate insulating film 130 are removed, the channel regions 150 and 160 may not be removed.
[0062] If the stacking process of the base gate insulating film 130 is omitted in the stack layer growing step a2 , only a portion of the sacrificial layer 140 may be selectively removed in the groove forming step d2 .
[0063] Reference Figure 4c In the spacer material layer forming step e2, a spacer material layer 280 may be formed on the side of the groove formed by the groove forming step d2 and the sacrificial polysilicon gate 170. In the spacer material layer forming step e2, the sacrificial polysilicon gate 170 may be used as a support structure and a mask. In one embodiment, the spacer material layer 280 may be formed by atomic layer deposition (ALD). The spacer material layer 280 may include a low dielectric material (or low-k material).
[0064] Reference Figure 4d In the side spacer and inner spacer forming step f2, the side spacers 180 and the inner spacers 190 may be formed by etching a portion of the channel regions 150, 160 and a portion of the spacer material layer 280. In the side spacer and inner spacer forming step f2, the side spacers 180 and the inner spacers 190 may be formed simultaneously.
[0065] Reference Figure 4e In the oxide film layer forming step g2 , heat treatment may be performed on the inner spacer 190 .
[0066] More specifically, in the oxide film layer forming step g2, the inner spacer 190 may be subjected to a heat treatment in a chamber set to a preset process pressure and a preset process temperature. In one embodiment, the preset process pressure may be determined within a range of 2 atmospheres to 100 atmospheres. In one embodiment, the preset process temperature may be determined within a range of 200° C. to 600° C.
[0067] When the heat treatment is performed in the oxide film layer forming step g2, an ambient gas may be supplied into the chamber. In one embodiment, the ambient gas may be O2 or H2O. In one embodiment, the concentration of the ambient gas in the chamber may be 100%.
[0068] In one embodiment, the heat treatment performed in the oxide film layer forming step g2 may be performed in any one of a wet environment, a dry environment, or a supercritical environment.
[0069] According to an embodiment, in the oxide film layer forming step g2 , a heat treatment may also be performed on the side spacer 180 . Therefore, an oxide film layer may also be formed on the outer surface of the side spacer 180 .
[0070] Although not shown, in the source region and drain region growth step h2, the source region 210 and the drain region 220 can be formed on both sides of the stack layer, i.e., the sacrificial layer 140 and the channel regions 150 and 160. In addition, in the source region and drain region growth step h2, the sacrificial layer 140 and the sacrificial polysilicon gate 170 can be removed by selective etching.
[0071] Although not shown, in the interface film forming step i2, gate electrodes 340 and 370 containing metal components may be formed in the regions where the sacrificial layer 140 and the sacrificial polysilicon gate 170 are removed. An interface film containing oxide may be formed on the outer surfaces of the gate electrodes 340 and 370.
[0072] According to an embodiment, the source region 210 and the drain region 220 may also be formed after removing the sacrificial layer 140 and the sacrificial polysilicon gate 170 and forming the gate electrodes 340 and 370 .
[0073] Figure 6 The graph shows leakage current values measured when voltage is applied to a semiconductor device manufactured according to the conventional technology and a semiconductor device manufactured according to the embodiment of the present specification.
[0074] exist Figure 6 In the figure, M0 represents a semiconductor device manufactured according to the prior art, and M1 to M3 represent semiconductor devices manufactured according to an embodiment of the present specification.
[0075] M0 is a semiconductor device manufactured through the same process as that of the first embodiment of the present specification, but without performing a heat treatment on the inner spacer.
[0076] M1 is a semiconductor device manufactured by the same process as that of the first embodiment of this specification, and heat treatment is performed on the inner spacer in a chamber with a process temperature set at 400° C. and a process pressure set at 2 atmospheres.
[0077] M2 is a semiconductor device manufactured by the same process as that of the first embodiment of this specification and subjected to heat treatment on the inner spacer in a chamber with a process temperature set at 400° C. and a process pressure set at 5 atmospheres.
[0078] M3 is a semiconductor device manufactured by the same process as that of the first embodiment of this specification and subjected to heat treatment on the inner spacer in a chamber with a process temperature set at 400° C. and a process pressure set at 10 atmospheres.
[0079] like Figure 6 As shown, the magnitude of the leakage current of the semiconductor devices M1, M2, and M3 that perform heat treatment on the inner spacer of an embodiment of the present invention is smaller than the magnitude of the leakage current of the semiconductor device M0 that does not perform heat treatment on the inner spacer. In particular, the magnitude of the leakage current of the semiconductor devices M1, M2, and M3 that perform heat treatment on the inner spacer of an embodiment of the present invention is confirmed to be maintained below 3.5 mA. Therefore, if the inner spacer is heat treated, the electrical characteristics of the semiconductor device can be improved.
[0080] As described above, this specification is described with reference to the illustrated drawings, but this specification is not limited to the embodiments and drawings disclosed in this specification, and a person skilled in the art of the present invention can make various modifications. Moreover, in the process of describing the embodiments of this specification, although there is no explicit description of the effect based on the structure of this specification, it should be recognized that the effect can be predicted by the structure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The steps include: Alternatingly stacking sacrificial layers and channel regions on a substrate to grow a stacked layer; forming a sacrificial polysilicon gate on the stacked layer; forming inner spacers and side spacers on the side surfaces of the sacrificial layer and the side surfaces of the sacrificial polysilicon gate; as well as The inner spacer or the side spacer is subjected to a heat treatment in a chamber set to a preset process pressure and a preset process temperature.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The above-mentioned preset process pressure is determined within the range of 2 atmospheres to 100 atmospheres.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The above-mentioned preset process temperature is determined within the range of 200°C to 600°C.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: An ambient gas is provided into the chamber, and the ambient gas is O2 or H2O.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: The concentration of the above-mentioned atmosphere gas is 100%.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The above heat treatment is performed in any one of a wet, dry or supercritical environment.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the inner spacer and the side spacer includes the step of forming the side spacer on the stacked layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the inner spacer and the side spacer include the following steps: removing a portion of the sacrificial layer to form a side groove; and An inner spacer is formed in the side groove.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the inner spacer and the side spacer include the following steps: removing a portion of the sacrificial layer to form a groove; forming a spacer material layer on the side surfaces of the groove and the sacrificial polysilicon gate; and The inner spacer and the side spacer are formed by removing a portion of the channel region and a portion of the spacer material layer.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The following steps are also included: forming a source region and a drain region; removing the sacrificial layer and the sacrificial polysilicon gate; and A gate electrode is formed.
11. The method for manufacturing a semiconductor device according to claim 1, wherein: The following steps are also included: removing the sacrificial layer and the sacrificial polysilicon gate; forming a gate electrode; and A source region and a drain region are formed.
12. A semiconductor device, characterized in that: include: substrate; A channel region, comprising a plurality of nanosheets stacked on the substrate; A gate electrode in contact with at least one side of the channel region; The source region and the drain region are respectively arranged on both sides of the channel region; A side spacer disposed on a side of the gate electrode; and An inner spacer is provided on the side of the gate electrode. An oxide film layer is formed on an outer surface of the side spacer or the inner spacer. The oxide film layer is formed by a heat treatment performed in a chamber set to a predetermined process pressure and a predetermined process temperature.
13. The semiconductor device according to claim 12, characterized in that The above-mentioned preset process pressure is determined within the range of 2 atmospheres to 100 atmospheres.
14. The semiconductor device according to claim 12, wherein: The above-mentioned preset process temperature is determined within the range of 200°C to 600°C.
15. The semiconductor device according to claim 12, characterized in that An ambient gas is provided into the chamber, and the ambient gas is O2 or H2O.
16. The semiconductor device according to claim 15, characterized in that The concentration of the above-mentioned atmosphere gas is 100%.
17. The semiconductor device according to claim 12, characterized in that The above heat treatment is performed in any one of a wet, dry or supercritical environment.