Integrated circuit device and internal data transmission control method of integrated circuit device

Abstract

The embodiment of the invention discloses an integrated circuit device and an internal data transmission control method of the integrated circuit device, which are invented for reducing the power consumption of the integrated circuit device. The integrated circuit device includes: a data forwarding unit connected to an upstream unit that transmits or forwards data and to a downstream unit that receives or forwards data; the first input end of the clock gating unit is connected with the normally open clock, and the second input end of the clock gating unit is used for inputting a clock control signal; and the output end of the clock gating unit is connected with the clock input end of the data forwarding unit, so that the clock input end of the data forwarding unit is controlled to have or have no normally open clock signal input according to a clock control signal input by the second input end of the clock gating unit. The method is suitable for data transmission in the chip.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an integrated circuit device and a method for controlling data transmission within the integrated circuit device. Background Art

[0002] In large-scale integrated circuit design, the number of modules in integrated circuit devices such as chips is increasing and their sizes are getting larger. The routing of interconnection lines between modules is also getting longer, resulting in the transmission on the interconnection lines being unable to reach all modules within one clock cycle.

[0003] In order to solve this problem, a common approach is to add data forwarding units between nodes of interconnection lines and between nodes and modules, so that the interconnection lines can extend to every corner of the chip. However, in the prior art, the data forwarding unit uses a normally open clock. Even when there is no data transmission, the clock input end of the data forwarding unit is still flipping, resulting in increased power consumption. Summary of the invention

[0004] In view of this, an embodiment of the present application provides an integrated circuit device and a method for controlling data transmission within the integrated circuit device, so as to reduce the power consumption of the integrated circuit device.

[0005] In a first aspect, an embodiment of the present application provides an integrated circuit device, comprising: a data forwarding unit, the data forwarding unit being connected to an upstream unit that sends or forwards data, and being connected to a downstream unit that receives or forwards data; a clock gating unit, a first input end of the clock gating unit being connected to a normally-open clock, and a second input end being used to input a clock control signal; an output end of the clock gating unit being connected to a clock input end of the data forwarding unit, so as to control whether the clock input end of the data forwarding unit has a normally-open clock signal input or does not have a normally-open clock signal input according to a clock control signal input to the second input end of the clock gating unit.

[0006] According to a specific implementation method of an embodiment of the present application, it also includes a data valid signal sending unit for sending a data valid signal; the data valid signal sending unit is connected to the second input end of the clock gating unit to input the data valid signal as the clock control signal into the second input end of the clock gating unit.

[0007] According to a specific implementation method of the embodiment of the present application, it also includes: a clock selection configuration circuit; the input end of the clock selection configuration circuit is connected to the output end of the data valid signal sending unit, and the output end is connected to the second input end of the clock gating unit; based on the first configuration information, the clock selection configuration circuit outputs a first enable signal to control the output end of the clock gating unit to output a normally-open clock signal; based on the second configuration information, the clock selection configuration circuit outputs a second enable signal to control the output end of the clock gating unit to have a normally-open clock signal output or no normally-open clock signal output.

[0008] According to a specific implementation method of an embodiment of the present application, the clock selection configuration circuit includes: a register and a logic operation circuit; the first input end of the logic operation circuit is connected to the output end of the register, the second input end is connected to the output end of the data valid signal sending unit, and the output end of the logic operation circuit is connected to the second input end of the clock gating unit.

[0009] According to a specific implementation method of an embodiment of the present application, the logic operation circuit includes a NOT gate and an OR gate; the input end of the NOT gate is connected to the output end of the register, and the output end is connected to the first input end of the OR gate; the second input end of the OR gate is connected to the data valid signal sending unit, and the output end of the OR gate is connected to the second input end of the clock gating unit.

[0010] According to a specific implementation of the embodiment of the present application, it also includes an enable signal forwarding unit; The first input end of the enable signal forwarding unit is connected to the output end of the clock selection configuration circuit and to the second input end of the clock gating unit; the second input end of the enable signal forwarding unit is connected to a normally-on clock; the output end of the enable signal forwarding unit is connected to the second input end of the clock gating unit corresponding to the data forwarding unit connected to the data forwarding unit.

[0011] According to a specific implementation method of an embodiment of the present application, it also includes a data valid signal forwarding unit; the first input end of the data valid signal forwarding unit is connected to the output end of the data valid signal sending unit, and the second input end is connected to a normally open clock; the output end of the data valid signal forwarding unit is connected to the second input end of the clock gating unit corresponding to the data forwarding unit connected to the data forwarding unit.

[0012] According to a specific implementation manner of the embodiment of the present application, the data forwarding unit and the data valid signal sending unit respectively include a D flip-flop.

[0013] In a second aspect, an embodiment of the present application provides a method for controlling internal data transmission of an integrated circuit device, comprising: in response to an input of a first signal, controlling a clock input end of a data forwarding unit to input a normally-on clock signal; in response to an input of a second signal, controlling a clock input end of the data forwarding unit to have no normally-on clock signal input; wherein the first signal represents a signal for sending valid data to the data forwarding unit, and the second signal represents a signal for not sending valid data to the data forwarding unit.

[0014] According to a specific implementation method of an embodiment of the present application, in response to the input of a first signal, controlling the clock input end of the data forwarding unit to input a normally-open clock signal includes: inputting the first signal to the first input end of the clock gating unit, and the output end of the clock gating unit outputs a normally-open clock signal; inputting the normally-open clock signal output from the output end of the clock gating unit into the clock input end of the data forwarding unit; in response to the input of a second signal, controlling the clock input end of the data forwarding unit to have no normally-open clock signal input, includes: inputting the second signal to the first input end of the clock gating unit, and the output end of the clock gating unit has no normally-open clock signal output, so that the clock input end of the data forwarding unit has no normally-open clock signal input.

[0015] According to a specific implementation method of an embodiment of the present application, it also includes: configuring a power consumption mode, the power consumption mode includes a first power consumption mode and a second power consumption mode; wherein the power consumption of the data forwarding unit in the first power consumption mode is greater than the power consumption of the data forwarding unit in the second power consumption mode; based on the first power consumption mode, the normally-open clock signal output from the output end of the clock gating unit is input to the clock input end of the data forwarding unit; or based on the second power consumption mode, the first signal or the second signal is input to the first input end of the clock gating unit.

[0016] In the integrated circuit device and the internal data transmission control method of the integrated circuit device of the present embodiment, the data forwarding unit is connected to the upstream unit that sends or forwards data, the first input end of the clock gating unit is connected to the normally open clock, the second input end is used to input the clock control signal, and the output end of the clock gating unit is connected to the clock input end of the data forwarding unit. Since the first input end of the clock gating unit is connected to the normally open clock, the second input end is used to input the clock control signal, and the output end of the clock gating unit is connected to the clock input end of the data forwarding unit, in this way, the output of the output end of the clock gating unit can be controlled according to the clock control signal input to the second input end of the clock gating unit, and then the clock input end of the data forwarding unit is controlled to have a normally open clock signal input or not. When there is data to be transmitted, the clock input end of the data forwarding unit is controlled to input a normally open clock signal, and when there is no data to be transmitted, the clock input end of the data forwarding unit is controlled to have no normally open clock signal, so as to reduce the power consumption of the integrated circuit device in the present embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of an integrated circuit device provided in one embodiment of the present application; Figure 2 A schematic diagram of the structure of an integrated circuit device provided in yet another embodiment of the present application; Figure 3 A schematic diagram of the structure of an integrated circuit device provided in one embodiment of the present application; Figure 4 A schematic diagram of the structure of an integrated circuit device provided in a specific embodiment of the present application; Figure 5 A schematic diagram of the structure of an integrated circuit device provided in another specific embodiment of the present application; Figure 6 is a timing diagram in an embodiment of the present application; Figure 7 A schematic diagram of a flow chart of a method for controlling internal data transmission of an integrated circuit device provided in an embodiment of the present application; Figure 8 A flowchart of a method for controlling internal data transmission in an integrated circuit device provided by yet another embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0021] Figure 1 The schematic diagram of the structure of the integrated circuit device provided in one embodiment of the present application is shown in FIG. The integrated circuit device of this embodiment may also be referred to as a chip, which may be a processor or a system on chip (SOC).

[0022] like Figure 1 As shown, the integrated circuit device of this embodiment may include: a data forwarding unit 11 and a clock gating unit 12; wherein the data forwarding unit 11 is connected to an upstream unit 13 that sends or forwards data, and is connected to a downstream unit 14 that receives or forwards data; a first input end of the clock gating unit 12 is connected to a normally open clock, and a second input end is used to input a clock control signal; an output end of the clock gating unit 12 is connected to a clock input end of the data forwarding unit 11, so as to control the clock input end of the data forwarding unit 11 to have a normally open clock signal input or no normally open clock signal input according to the clock control signal input to the second input end of the clock gating unit 12.

[0023] The data forwarding unit 11 is used to forward received data, which may be data sent by the upstream unit 13 or forwarded by the upstream unit 13. The data forwarding unit 11 sends the received data to the downstream unit 14. In one case, after receiving the data, the downstream unit 14 may no longer forward the data but only process the data; in another case, after receiving the data, the downstream unit 14 may also continue to forward the received data backward.

[0024] In some examples, the data forwarding unit 11 includes a D flip-flop.

[0025] The first input terminal of the clock gating unit 12 (cg) is connected to the normally-open clock, and the second input terminal is used to input a clock control signal. Whether there is a clock signal at the output terminal of the clock gating unit 12 is determined by the input signal of the first output terminal and the input signal of the second input terminal. In this embodiment, when an enable signal is input to the second input terminal of the clock gating unit 12, the output terminal of the clock gating unit 12 outputs a normally-open clock signal; when no enable signal is input to the second input terminal of the clock gating unit 12, no normally-open clock signal is output at the output terminal of the clock gating unit 12.

[0026] When the data forwarding unit 11 needs to forward valid data, an enable signal may be input to the second input terminal of the control clock gating unit 12 to control the clock input terminal of the data forwarding unit 11 to input a normally open clock signal, so that the data forwarding unit 11 forwards valid data. When the data forwarding unit 11 does not have valid data to be forwarded, the enable signal may be not input to the second input terminal of the control clock gating unit to control the clock input terminal of the data forwarding unit 11 to have no normally open clock signal, thereby reducing the power consumption of the integrated circuit device in this embodiment.

[0027] In this embodiment, the data forwarding unit 11 is connected to the upstream unit 13 that sends or forwards data, the first input end of the clock gating unit 12 is connected to the normally open clock, the second input end is used to input the clock control signal, and the output end of the clock gating unit 12 is connected to the clock input end of the data forwarding unit 11. Since the first input end of the clock gating unit 12 is connected to the normally open clock, the second input end is used to input the clock control signal, and the output end of the clock gating unit 12 is connected to the clock input end of the data forwarding unit 11, in this way, the clock input at the second input end of the clock gating unit 12 can be A control signal controls the output of the output end of the clock gating unit 12, and further controls the clock input end of the data forwarding unit 11 to have a normally-open clock signal input or no normally-open clock signal input. When there is data to be transmitted, the clock input end of the data forwarding unit 11 is controlled to have a normally-open clock signal input, and when there is no data to be transmitted, the clock input end of the data forwarding unit 11 is controlled to have no normally-open clock signal, so as to reduce the power consumption of the integrated circuit device in this embodiment and avoid the problem of high power consumption caused by clock flipping at the clock input end of the data forwarding unit 11 in the prior art.

[0028] When the data forwarding unit 11 sends valid data, a data valid signal sending unit needs to be set in the integrated circuit device, and the sending unit is used to send a signal indicating that the data forwarded by the data forwarding unit 11 is valid data. For the clock control signal input to the second input end of the clock gating unit 12, additional control logic can be designed to provide a clock control signal to the second input end of the clock gating unit 12. However, this will make the control logic of the integrated circuit device in this embodiment more complicated, and increase the manufacturing cost of the integrated circuit device. To overcome such problems, see Figure 1 This embodiment provides an integrated circuit device which also includes a data valid signal sending unit 15, which is used to send a data valid signal; the data valid signal sending unit 15 is connected to the second input end of the clock gating unit 12 to input the data valid signal as a clock control signal to the second input end of the clock gating unit 12.

[0029] When the data forwarding unit 11 needs to forward valid data, the data valid signal sending unit 15 sends a first signal. Since the data valid signal sending unit 15 is connected to the second input end of the clock gating unit 12, the first signal is input to the second input end of the clock gating unit 12, so that the output end of the clock gating unit 12 outputs a normally-open clock signal, and then the clock input end of the data forwarding unit 11 inputs a normally-open clock signal; when the data forwarding unit 11 does not need to forward valid data, the data valid signal sending unit 15 sends a second signal. Since the data valid signal sending unit 15 is connected to the second input end of the clock gating unit 12, the second signal is input to the second input end of the clock gating unit 12, so that the output end of the clock gating unit 12 has no normally-open clock signal, and then the clock input end of the data forwarding unit 11 has no normally-open clock signal.

[0030] In some examples, the data valid signal sending unit 15 includes a D flip-flop.

[0031] In this embodiment, the data valid signal sending unit 15 is connected to the second input end of the clock gating unit 12, so that the data valid signal can be used as a clock control signal and input into the second input end of the clock gating unit 12. When the data forwarding unit 11 forwards valid data, there is also a practical need to send a data valid signal separately in the integrated circuit device. In this embodiment, the data valid signal sending unit 15 is multiplexed and the signal generated by it is used as the clock control signal. In this way, the structure of the integrated circuit device of this embodiment can be simplified and the manufacturing cost can be reduced.

[0032] See also Figure 2 In order to improve the reliability and flexibility of the integrated circuit device of the embodiment of the present application, in some examples, the integrated circuit device also includes: a clock selection configuration circuit 16; the input end of the clock selection configuration circuit 16 is connected to the output end of the data valid signal sending unit 15, and the output end is connected to the second input end of the clock gating unit.

[0033] Based on the first configuration information, the clock selection configuration circuit 16 outputs a first enable signal to control the output end of the clock gating unit to output a normally-on clock signal; based on the second configuration information, the clock selection configuration circuit 16 outputs a second enable signal to control the output end of the clock gating unit to have a normally-on clock signal output or no normally-on clock signal output.

[0034] The clock selection configuration circuit 16 can be configured as needed. When a normally-open clock signal is required to be input to the clock input end of the data forwarding unit 11, the clock selection configuration circuit 16 is configured based on the first configuration information so that the clock selection configuration circuit 16 outputs a first enable signal to control the output end of the first clock gating unit 121 to output the normally-open clock signal according to the first enable signal; when a normally-open clock signal is required to be input to the clock input end of the data forwarding unit 11 or no normally-open clock input, the clock selection configuration circuit 16 is configured based on the second configuration information so that the clock selection configuration circuit 16 outputs a second enable signal to control the output end of the second clock gating unit 122 to output the normally-open clock signal or no normally-open clock signal according to the second enable signal.

[0035] The first enable signal is a low power disabling signal, and the second enable signal is a low power enabling signal.

[0036] In this embodiment, based on the first configuration information, the clock selection configuration circuit 16 can output a first enable signal, and then the output end of the clock gating unit outputs a normally-open clock signal; based on the second configuration information, the clock selection configuration circuit 16 can output a second enable signal, and then the output end of the clock gating unit has a normally-open clock signal output or no normally-open clock signal output.

[0037] In a specific example, the clock selection configuration circuit 16 includes: a register and a logic operation circuit.

[0038] The first input terminal of the logic operation circuit is connected to the output terminal of the register, the second input terminal is connected to the output terminal of the data valid signal sending unit 15, and the output terminal of the logic operation circuit is connected to the second input terminal of the clock gating unit.

[0039] Based on the first configuration information, the register can be configured so that the output end of the logic operation circuit outputs a low-power disabling signal, and controls the output end of the clock gating unit 12 to output a normally-open clock signal; based on the second configuration information, the register can be configured so that the output end of the logic operation circuit outputs a low-power enabling signal, and controls the output end of the clock gating unit 12 to have a normally-open clock signal output or no normally-open clock signal output.

[0040] In one embodiment, the logic operation circuit includes a NOT gate and an OR gate; the input end of the NOT gate is connected to the output end of the register, and the output end is connected to the first input end of the OR gate; the second input end of the OR gate is connected to the data valid signal sending unit 15, and the output end of the OR gate is connected to the second input end of the clock gating unit 12.

[0041] Specifically, the register is configured as "0", indicating that the low power consumption function is not enabled. At this time, the signal cken at the output of the OR gate is always "1", and the signal clk_gated output by the clock gating unit 12 is a normally open clock. In this case, the normally open clock is input to the second input of the data forwarding unit 11. The register is configured as "1", indicating that the low power consumption function is enabled. At this time, the signal cken at the output of the OR gate follows the signal valid sent by the valid signal sending unit. When valid is "1", there is a clock on the data forwarding unit 11, and when valid is "0", there is no clock on the data forwarding unit 11.

[0042] The integrated circuit device in this embodiment may further include an enable signal forwarding unit.

[0043] The first input end of the enable signal forwarding unit is connected to the output end of the clock selection configuration circuit 16, and is connected to the second input end of the clock gating unit 12; the second input end of the enable signal forwarding unit is connected to the normally-on clock, and the output end of the enable signal forwarding unit is connected to the second input end of the clock gating unit corresponding to the data forwarding unit connected to the data forwarding unit.

[0044] like Figure 2 In the illustrated embodiment, the enable signal output by the clock selection configuration circuit 16 is input to the second input terminal of the first clock gating unit 121, and the output normally-on clock signal of the output terminal of the first clock gating unit 121 is controlled by the enable signal, or the presence or absence of a normally-on clock signal at the output terminal. In addition, the output terminal of the first enable signal forwarding unit 171 in the present embodiment is connected to the second input terminal of the second clock gating unit 122, that is, the enable signal can be forwarded to the second clock gating unit 122 through the first enable signal forwarding unit 171, so that the power consumption of the second data forwarding unit 112 can be flexibly controlled.

[0045] The input end of the second enable signal forwarding unit 172 can be connected to the output end of the first enable signal forwarding unit 171, so that the enable signal can be further transmitted downward through the second enable signal forwarding unit 172 to control other data forwarding units, thereby flexibly controlling the power consumption of other data forwarding units.

[0046] In some examples, a data valid signal forwarding unit is also included; the first input end of the data valid signal forwarding unit is connected to the output end of the data valid signal sending unit 15, and the second input end is connected to the normally open clock; the output end of the data valid signal forwarding unit is connected to the second input end of the clock gating unit corresponding to the data forwarding unit connected to the data forwarding unit.

[0047] like Figure 3In the embodiment shown, in this embodiment, the output end of the data valid signal sending unit 15 is connected to the first input end of the first data valid signal forwarding unit 181, and is connected to the second input end of the first data forwarding unit 111, and then the data valid signal is input to the second input end of the first clock gating unit 121, and the data valid signal is used as a clock control signal to control the clock input end of the first data forwarding unit 111 to have a normally open clock signal input or no normally open clock signal input.

[0048] In addition, the first data valid signal forwarding unit 181 can forward the data valid signal to the second input end of the second clock gating unit 122, so that the forwarded data valid signal can be used as a clock control signal and input into the second input end of the second clock gating unit 122, thereby reducing the power consumption of the second data forwarding unit 112.

[0049] The input end of the second data valid signal forwarding unit 182 can be connected to the output end of the first data valid signal forwarding unit 181, so that the data valid signal can be further transmitted downward through the second data valid signal forwarding unit 182 to control other data forwarding units, thereby reducing the power consumption of other data forwarding units.

[0050] In this embodiment, the first data valid signal forwarding unit 181 and the second data valid signal forwarding unit 182 include D flip-flops.

[0051] The solution of the present application is described in detail below with a specific embodiment.

[0052] The master module 10 and the slave module 20 in the integrated circuit need to transmit signals or data. In the specific implementation, an interconnection line is connected between the master module 10 and the slave module 20 to transmit signals or data. However, the number of modules in integrated circuit devices such as chips is increasing, and the size is also increasing. The routing of the interconnection lines between the modules is also increasing, resulting in the transmission on the interconnection lines not being able to reach all modules within one clock cycle. In order to solve this problem, a pipeline (transfer module) can be set on the interconnection line between the master module 10 and the slave module 20 to realize the transmission of data between the master module 10 and the slave module 20. The pipeline includes a data forwarding unit 11, and if the distance between the master module 10 and the slave module 20 is far, multiple pipelines can be set in sequence between the master module 10 and the slave module 20, and a data forwarding unit is set in each pipeline. For example, a first transfer module 301 including a first data forwarding unit 111, a second transfer module 302 including a second data forwarding unit 112, and a third transfer module including a third data forwarding unit are sequentially set from the master module 10 to the slave module 20. In Figure 3In the illustrated embodiment, for the first data forwarding unit 111, its corresponding upstream module is the main module 10; for the second data forwarding unit 112, its corresponding upstream module is the first data forwarding unit 111, and for the third data forwarding unit, its corresponding upstream module is the second data forwarding unit 112; for the first data forwarding unit 111, its corresponding downstream module is the second data forwarding unit 112, and for the second data forwarding unit 112, its corresponding downstream module is the third data forwarding unit, and the upstream modules and downstream modules corresponding to other data forwarding units are analogous in this way.

[0053] In one specific example, the interconnection line between the master module 10 and the slave module 20 may be in the form of a bus, that is, the signal or data transmitted between the master module 10 and the slave module 20 follows the bus protocol; in another specific example, the interconnection line between the master module 10 and the slave module 20 is used to transmit independent instructions.

[0054] The master module 10 sends valid data to the slave module 20. A data valid signal sending unit for sending a data valid signal is provided in the master module 10. After receiving the data valid signal, the slave module 20 responds to it.

[0055] In order to make full use of existing circuits and simplify the structure of integrated circuit devices, such as Figure 4 In the illustrated embodiment, a clock gating unit and a data valid signal forwarding unit are provided in each transit module, the first input end of each clock gating unit is connected to a normally open clock, the second input end inputs a data valid signal, and the output end is connected to the clock input end of the data forwarding unit in the transit module where the unit is located. Specifically, the second input end of the first clock gating unit 121 is connected to the output end of the data valid signal sending unit 15; the first input end of the first data valid signal forwarding unit 181 is connected to the output end of the data valid signal sending unit 15, and the second input end is connected to the normally open clock; the output end of the first data valid signal forwarding unit 181 is connected to the first input end of the second data valid signal forwarding unit 182, and is connected to the second input end of the second clock gating unit 122. In this embodiment, the data valid signal sent by the data valid signal sending unit 15 can be used as an input signal of the second input end of the first clock gating unit 121 to control the output of the first clock gating unit 121 through the data valid signal, thereby facilitating the reduction of the power consumption of the first data forwarding unit 111, and similarly facilitating the reduction of the power consumption of the second data forwarding unit 112. At the same time, in this embodiment, the original data valid signal sending unit 15 and the data valid signal forwarding unit in the integrated circuit device are multiplexed to simplify the structure of the integrated circuit device.

[0056] The signals transmitted between the master module 10 and the slave module 20 include valid data, a data validity signal valid, and a free space feedback signal cap_ack.

[0057] Among them, valid and cap_ack are single-bit control signals that need to be transmitted in real time, so the data valid signal forwarding unit and the free space feedback unit (not shown in the figure) use a normally open clock (AON), and the data forwarding unit 11 that transmits the data signal uses a gated clock signal, which is output by the clock gating unit 12.

[0058] The signal forwarded by the data valid signal forwarding unit indicates whether the data forwarded by the data forwarding unit 11 is valid data. When the signal valid forwarded by the data valid signal forwarding unit is "1", it indicates that the data data forwarded by the data forwarding unit 11 is valid data; when valid is "0", it indicates that the data data forwarded by the data forwarding unit 11 is invalid data.

[0059] In this embodiment, in addition to indicating whether the data is valid, the valid signal is also used as the enable terminal of the clock gating unit 12 (cg), that is, only when valid is "1", the trigger dff in the data forwarding unit 11 will have a clock. When the bus is idle, valid is "0", at this time, only the data valid signal forwarding unit and the trigger dff in the idle space feedback unit in each level of the transfer module still have a clock, and the clock on the data forwarding unit 11 is stopped, which greatly reduces the power consumption of the data forwarding unit 11.

[0060] The free space feedback signal cap_ack is sent from the module 20 to the master module 10 . When cap_ack is “1”, it indicates that a piece of data has been read from the first-in first-out queue (FIFO) in the slave module 20 (ie, an entry has been vacated).

[0061] There is a counter inside the master module 10. The initial value of the counter is equal to the depth of the FIFO of the slave module 20. When the master module 10 sends a valid data, the counter is reduced by "1"; when the master module 10 receives cap_ack as "1", the counter is increased by "1", so the counter reflects the free capacity of the FIFO of the slave module 20. Only when the value of the counter is greater than "0" can the master module 10 send valid data.

[0062] In order to improve the reliability and flexibility of the integrated circuit device of the embodiment of the present application, Figure 5In the illustrated embodiment, a data valid signal sending unit 15 and a clock selection configuration circuit 16 are provided in the main module 10, and a clock gating unit and an enable signal forwarding unit are provided in each transfer module. Specifically, the first transfer module 301 includes a first data forwarding unit 111, a first clock gating unit 121, and a first enable signal forwarding unit 171, and the second transfer module 302 includes a second data forwarding unit 112, a second clock gating unit 122, and a second enable signal forwarding unit 172.

[0063] The input end of the clock selection configuration circuit 16 is connected to the output end of the data valid signal sending unit 15, the output end of the clock selection configuration circuit 16 is connected to the first input end of the first enable signal forwarding unit 171, and is connected to the second input end of the first clock gating unit 121, and the output end of the first clock gating unit 121 is connected to the clock input end of the first data forwarding unit 111. In this way, the output of the first clock gating unit 121 can be controlled by the enable signal output from the output end of the clock selection configuration circuit 16, thereby controlling the power consumption of the first data forwarding unit 111.

[0064] The output end of the first enable signal forwarding unit 171 is connected to the second input end of the second clock gating unit 122, so that the output of the second clock gating unit 122 can be controlled by the enable signal forwarded by the first enable signal forwarding unit 171, so as to control the power consumption of the second data forwarding unit 112.

[0065] The enable signal outputted from the output terminal of the second enable signal forwarding unit 172 may also be further transmitted to other clock gating units, so as to control the power consumption of the corresponding data forwarding units.

[0066] In such Figure 5 In the illustrated embodiment, the clock selection configuration circuit 16 includes a register 160 and a logic operation circuit 161 , and the logic operation circuit 161 includes a NOT gate and an OR gate.

[0067] The input of the NOT gate is connected to the output of the register 160 , and the output is connected to the first input of the OR gate; the second input of the OR gate is connected to the data valid signal sending unit 15 , and the output of the OR gate is connected to the second input of the first clock gating unit 121 .

[0068] In a specific example, see Figure 6In area ①, cg is in the on state, or the gate output signal cken and the valid signal sending unit enter the latch inside cg; once entering area ②, the latch inside cg will be immediately locked to "1", thereby ensuring that the clock control signal clk_gated is a valid clock edge, and clk_gated will latch the input data into the D flip-flop of the data forwarding unit 11; when valid is "0", the clk_gated signal does not flip.

[0069] Figure 7 A flow chart of a method for controlling data transmission within an integrated circuit device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the internal data transmission control method of the integrated circuit device of this embodiment may include: S101 . In response to an input of a first signal, control a clock input terminal of a data forwarding unit to input a normally-on clock signal.

[0070] The first signal represents a signal for sending valid data to the data forwarding unit.

[0071] Under the control of the first signal, a normally-on clock signal is input to the clock input terminal of the data forwarding unit, so that the data forwarding unit can forward valid data to the downstream module.

[0072] S102 . In response to the input of the second signal, control the clock input terminal of the data forwarding unit to have no normally-on clock signal input.

[0073] The second signal indicates that no valid data is sent to the data forwarding unit.

[0074] Under the control of the second signal, no normally-on clock signal is input to the clock input end of the data forwarding unit, that is, when there is no need to send valid data, no clock flip occurs at the clock input end of the data forwarding unit.

[0075] In the present embodiment, in response to the input of the first signal, the clock input end of the data forwarding unit is controlled to input a normally-open clock signal, and in response to the input of the second signal, the clock input end of the data forwarding unit is controlled to have no normally-open clock signal input, and the first signal represents a signal for sending valid data to the data forwarding unit, and the second signal represents a signal for not sending valid data to the data forwarding unit. When valid data needs to be forwarded, the clock input end of the data forwarding unit is controlled to input a normally-open clock signal through the first signal, and when valid data does not need to be forwarded, the clock input end of the data forwarding unit is controlled to have no normally-open clock signal input through the input of the second signal. In this way, the power consumption of the integrated circuit device in the present embodiment is reduced, and the problem of high power consumption caused by clock flipping at the clock input end of the data forwarding unit in the prior art is avoided.

[0076] In order to control the clock input end of the data forwarding unit to input a normally open clock signal, a control logic may be designed to input a first signal to the first input end of the clock gating unit. However, this may make the control logic of the integrated circuit device in this embodiment more complicated and increase the control cost. In order to overcome the above problem and reduce the input of the normally open clock signal to the clock input end of the data forwarding unit, in a specific example, in response to the input of the first signal in step S101, controlling the clock input end of the data forwarding unit to input a normally open clock signal may include: S101a, inputting a first signal to a first input terminal of a clock gating unit, and an output terminal of the clock gating unit outputs a normally-on clock signal.

[0077] The first signal is input to the first input terminal of the clock gating unit, and the second input terminal of the clock gating unit inputs the normally-on clock signal. Specifically, the second input terminal of the clock gating unit can be connected to the normally-on clock, so that the output terminal of the clock gating unit outputs the normally-on clock.

[0078] S101b, inputting the normally-on clock signal outputted from the output end of the clock gating unit into the clock input end of the data forwarding unit.

[0079] The output end of the clock gating unit can be connected to the clock input end of the data forwarding unit. When the output end of the clock gating unit outputs a normally-on clock signal, the clock input end of the data forwarding unit inputs the normally-on clock signal.

[0080] A control logic may be designed to control the clock input end of the data forwarding unit to have no normally-open clock signal input. However, this may make the control logic of the integrated circuit device in this embodiment more complicated and increase the control cost. In order to overcome the above problem and reduce the possibility that the clock input end of the data forwarding unit has no normally-open clock signal input, the step S102 in the above embodiment controls the clock input end of the data forwarding unit to have no normally-open clock signal input in response to the input of the second signal, including: S102a, inputting the second signal to the first input terminal of the clock gating unit, and the output terminal of the clock gating unit has no normally-on clock signal output, so that the clock input terminal of the data forwarding unit has no normally-on clock signal input.

[0081] The output end of the clock gating unit can be connected to the clock input end of the data forwarding unit. When the output end of the clock gating unit has no normally-on clock signal output, the clock input end of the data forwarding unit has no normally-on clock signal input.

[0082] See also Figure 8 The integrated circuit device may work in a fixed mode. To improve the reliability and flexibility of the integrated circuit device, in some examples, the method of this embodiment may further include: S103: Configure power consumption mode.

[0083] The power consumption mode in this embodiment may include a first power consumption mode and a second power consumption mode.

[0084] The power consumption of the data forwarding unit in the first power consumption mode is greater than that in the second power consumption mode. The first power consumption mode can be used preferentially according to actual conditions, thereby reducing the power consumption of the data forwarding unit in forwarding valid data.

[0085] S104 . Based on the first power consumption mode, input the normally-on clock signal outputted from the output terminal of the clock gating unit to the clock input terminal of the data forwarding unit.

[0086] S105 . Based on the second power consumption mode, input the first signal or the second signal to a first input terminal of the clock gating unit.

[0087] When the first power consumption mode fails, the second power consumption mode may be used; or, when the second power consumption mode fails, the first power consumption mode may be used.

[0088] In this embodiment, different power consumption modes can be configured as needed. In the first power consumption mode, the normally-open clock signal output from the output end of the clock gating unit is input to the clock input end of the data forwarding unit, that is, regardless of whether there is valid data to be forwarded, the clock input end of the data forwarding unit inputs the normally-open clock signal. In the second power consumption mode, the first signal or the second signal is input to the first input end of the clock gating unit, that is, in the second power consumption mode, based on the first signal or the second signal, the clock input end of the data forwarding unit inputs the normally-open clock signal or no normally-open clock signal is input. In this way, when one of the power consumption modes fails, another power consumption mode can be used, thereby improving the reliability of forwarding valid data. In addition, the power consumption of the data forwarding unit in the first power consumption mode is greater than the power consumption of the data forwarding unit in the second power consumption mode. In this way, it is easy to reduce the power consumption of the data forwarding unit in forwarding valid data.

[0089] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0090] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0091] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An integrated circuit device, characterized in that: include: A data forwarding unit, the data forwarding unit is connected to an upstream unit that sends or forwards data, and is connected to a downstream unit that receives or forwards data; A clock gating unit, wherein a first input terminal of the clock gating unit is connected to a normally-on clock, and a second input terminal is used to input a clock control signal; The output end of the clock gating unit is connected to the clock input end of the data forwarding unit to control the clock input end of the data forwarding unit to have a normally open clock signal input or no normally open clock signal input according to the clock control signal input from the second input end of the clock gating unit.

2. The integrated circuit device according to claim 1, characterized in that It also includes a data valid signal sending unit, which is used to send a data valid signal; The data valid signal sending unit is connected to the second input end of the clock gating unit to input the data valid signal as the clock control signal into the second input end of the clock gating unit.

3. The integrated circuit device according to claim 1, characterized in that: Also includes: A clock selection configuration circuit; the input end of the clock selection configuration circuit is connected to the output end of the data valid signal sending unit, and the output end is connected to the second input end of the clock gating unit; Based on the first configuration information, the clock selection configuration circuit outputs a first enable signal to control the output end of the clock gating unit to output a normally-on clock signal; Based on the second configuration information, the clock selection configuration circuit outputs a second enable signal to control the output end of the clock gating unit to output a normally-on clock signal or not output a normally-on clock signal.

4. The integrated circuit device according to claim 3, characterized in that The clock selection configuration circuit includes: a register and a logic operation circuit; The first input end of the logic operation circuit is connected to the output end of the register, the second input end is connected to the output end of the data valid signal sending unit, and the output end of the logic operation circuit is connected to the second input end of the clock gating unit.

5. The integrated circuit device according to claim 4, characterized in that The logic operation circuit includes a NOT gate and an OR gate; the input end of the NOT gate is connected to the output end of the register, and the output end is connected to the first input end of the OR gate; the second input end of the OR gate is connected to the data valid signal sending unit, and the output end of the OR gate is connected to the second input end of the clock gating unit.

6. The integrated circuit device according to claim 3, characterized in that Also included is an enable signal forwarding unit; The first input end of the enable signal forwarding unit is connected to the output end of the clock selection configuration circuit and to the second input end of the clock gating unit; the second input end of the enable signal forwarding unit is connected to a normally-on clock; the output end of the enable signal forwarding unit is connected to the second input end of the clock gating unit corresponding to the data forwarding unit connected to the data forwarding unit.

7. The integrated circuit device according to claim 2, characterized in that: Also includes a data valid signal forwarding unit; The first input end of the data valid signal forwarding unit is connected to the output end of the data valid signal sending unit, and the second input end is connected to the normally open clock; the output end of the data valid signal forwarding unit is connected to the second input end of the clock gating unit corresponding to the data forwarding unit connected to the data forwarding unit.

8. The integrated circuit device according to claim 2, characterized in that: The data forwarding unit and the data valid signal sending unit each include a D flip-flop.

9. A method for controlling data transmission within an integrated circuit device, characterized in that: include: In response to the input of the first signal, the clock input terminal of the data forwarding unit is controlled to input a normally open clock signal; wherein the first signal represents a signal for sending valid data to the data forwarding unit, In response to the input of a second signal, the clock input end of the data forwarding unit is controlled to have no normally-on clock signal input; wherein the second signal indicates a signal that no valid data is sent to the data forwarding unit.

10. The method for controlling data transmission within an integrated circuit device according to claim 9, wherein: The step of controlling the clock input terminal of the data forwarding unit to input a normally-on clock signal in response to the input of the first signal comprises: Inputting a first signal to a first input terminal of a clock gating unit, wherein an output terminal of the clock gating unit outputs a normally-on clock signal; Inputting the normally-on clock signal outputted from the output end of the clock gating unit into the clock input end of the data forwarding unit; The step of controlling the clock input terminal of the data forwarding unit to have no normally-on clock signal input in response to the input of the second signal comprises: The second signal is input to the first input end of the clock gating unit, and the output end of the clock gating unit has no normally-on clock signal output, so that the clock input end of the data forwarding unit has no normally-on clock signal input.

11. The method for controlling data transmission within an integrated circuit device according to claim 10, wherein: Also includes: Configure a power consumption mode, the power consumption mode including a first power consumption mode and a second power consumption mode; wherein the power consumption of the data forwarding unit in the first power consumption mode is greater than the power consumption of the data forwarding unit in the second power consumption mode; Based on the first power consumption mode, inputting a normally-on clock signal outputted from an output terminal of the clock gating unit into a clock input terminal of the data forwarding unit; Based on the second power consumption mode, the first signal or the second signal is input to a first input terminal of the clock gating unit.

Images