Converter control method and control device

Abstract

The invention provides a control method and a control device of a current converter, which are characterized in that injected zero sequence voltage is allowed to be injected into the current converter, the voltage of a bridge arm capacitor can be changed, discretization processing can be carried out on the voltage variation of the bridge arm capacitor, and the voltage of the bridge arm capacitor in the next sampling period is obtained. And carrying out balance control on the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period. According to the invention, the balance control of the bridge arm capacitor is realized, and the long-term reliable operation of the converter is ensured, namely, the operation reliability of the converter is improved. In addition, according to the invention, the output voltage range (a power frequency voltage range or a low frequency voltage range and the like) of the current converter can be enlarged, so that the current converter is suitable for a scene with a high requirement on the voltage range. In addition, the voltage variation of the bridge arm capacitor can be reduced, so that the cost of the sub-module is reduced, and the economical efficiency of the converter is improved.

Description

Technical Field

[0001] The present application relates to the field of power transmission technology, and in particular to a control method and a control device for a converter. Background Art

[0002] Flexible low-frequency AC transmission system can flexibly select frequencies below 50Hz with the help of frequency conversion and grid control technology of power electronic devices to improve AC transmission capacity, while retaining the characteristics of electromagnetic induction transformation and current zero-crossing interruption of AC transmission, which is a supplement to industrial frequency AC transmission and DC transmission. Converters such as inverters or rectifiers are the core part of flexible low-frequency AC transmission system, which can realize frequency conversion and perform flexible control of power grid such as power flow control and voltage regulation.

[0003] The converter usually includes multiple bridge arms, each of which may include a bridge arm capacitor. The related technology cannot achieve voltage balance control of the bridge arm capacitors in multiple bridge arms, resulting in the converter being unable to operate reliably for a long time, that is, the converter has low operating reliability. Summary of the invention

[0004] In order to solve the problem of long-term operation reliability of the converter in the prior art, the present application provides a control method of the converter, which may include:

[0005] The zero-sequence voltage allowed to be injected is injected into the converter.

[0006] The voltage variation of the bridge arm capacitor in the converter is discretized to obtain the voltage of the bridge arm capacitor in the next sampling period.

[0007] The bridge arm capacitor is balanced and controlled according to the voltage of the bridge arm capacitor in the next sampling period.

[0008] Furthermore, the control method also includes:

[0009] The zero-sequence voltage allowed to be injected is determined according to the maximum modulation ratio of the converter.

[0010] In some possible implementations, the injected zero-sequence voltage is allowed to satisfy:

[0011]

[0012] Among them, v Z1 Indicates the zero-sequence voltage allowed to be injected; max Indicates the maximum modulation ratio of the converter; V Crepresents the reference voltage of the submodule capacitor; sgn represents the sign function; u1 represents the voltage at the first end of the converter, satisfying u1=V1cos(ω1t), V1 represents the voltage amplitude at the first end of the converter, ω1 represents the angular frequency at the first end of the converter, and t represents time; u2 represents the voltage at the second end of the converter, satisfying u2=V2cos(ω2t+θ), V2 represents the voltage amplitude at the second end of the converter, ω2 represents the angular frequency at the second end of the converter, and θ represents the phase of u2 leading u1; u b1 represents the voltage of the first bridge arm in the converter, satisfying u b1 =sgn(u1)u1oru b1 =sgn(u1+v Z1 )(u1+v Z1 );u b2 represents the voltage of the second bridge arm in the converter, satisfying u b2 =sgn(u2)u2-sgn(u1)u1 or u b2 =sgn(u2+v Z1 )(u2+v Z1 )-sgn(u1+v Z1 )(u1+v Z1 ).

[0013] In some other possible implementations, the voltage change of the bridge arm capacitor satisfies:

[0014]

[0015] in, represents the voltage change of the bridge arm capacitor; N represents the number of submodules in the first bridge arm or the second bridge arm; C represents the capacitance of the submodule capacitor; u C represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm; p represents the power of the first bridge arm or the second bridge arm after the injection of the allowed zero-sequence voltage, satisfying p = u b1 i b1 or p=u b2 i b2 ,i b1 Represents the current of the first bridge arm, satisfying i b1 =sgn(u1)i1+sgn(u2)i2,i b2 Represents the current of the second bridge arm, satisfying i b2 =sgn(u2)i2, i1 represents the current at the first end of the converter, satisfying I1 represents the current amplitude at the first end of the converter, represents the power factor angle at the first end of the converter, i2 represents the current at the second end of the converter, satisfying I2 represents the current amplitude at the second end of the converter, represents the power factor angle at the second end of the converter.

[0016] In some other possible implementations, the voltage of the bridge arm capacitor in the next sampling period satisfies:

[0017]

[0018] Among them, u C (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the converter in the sampling period k+1, u C (k) represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k, p(k) represents the power of the first bridge arm or the second bridge arm in the sampling period k after the injection of the allowed zero-sequence voltage, T represents the sampling time, N represents the number of sub-modules of the first bridge arm or the second bridge arm; C represents the capacitance of the sub-module capacitor.

[0019] Optionally, balancing the bridge arm capacitor is controlled according to the voltage of the bridge arm capacitor in the next sampling period, including:

[0020] The cost function is constructed according to the voltage of the bridge arm capacitor in the next sampling period.

[0021] With the goal of minimizing the function value of the cost function, the zero-sequence voltage allowed to be injected is adjusted.

[0022] Among them, the cost function satisfies:

[0023] J(k+1)=||Δu C (k+1)|| p

[0024] Where J(k+1) represents the cost function within the sampling period k+1; ||·|| p represents the p-norm; Δu C (k+1) represents the error vector between the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k+1 and the reference voltage; Δu C (k+1) satisfies:

[0025] Δu C (k+1)=(u C1 (k+1)-U C0 ,u C2 (k+1)-U C0 ,…,u Cn (k+1)-U C0 ) T

[0026] u C1 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the first phase at sampling period k+1, u C2(k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the second phase at sampling period k+1, u Cn (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the nth phase in the sampling period k+1, U C0 represents the reference voltage of the bridge arm capacitance of the first bridge arm or the second bridge arm, and T represents transposition.

[0027] Exemplarily, the converter includes a first bridge arm, a second bridge arm, a first inversion unit, and a second inversion unit.

[0028] The first end of the first bridge arm, the second bridge arm and the first inversion unit are connected, the second end of the second bridge arm is connected to the first end of the second inversion unit, and the second ends of the first inversion unit, the first bridge arm and the second inversion unit are connected;

[0029] The first bridge arm is used to generate a voltage of the first bridge arm.

[0030] The second bridge arm is used to generate a voltage of the second bridge arm.

[0031] The first inversion unit is used to: invert the polarity of the voltage of the first bridge arm according to the first preset frequency and the first preset phase angle to generate a first terminal voltage that alternates between positive and negative; wherein the first terminal voltage is used to indicate the voltage of the first terminal in the converter.

[0032] The second inversion unit is used to: superimpose the voltage of the first bridge arm and the voltage of the second bridge arm, and reverse the polarity of the superimposed voltage according to the second preset frequency and the second preset phase angle to generate a second terminal voltage that alternates between positive and negative; wherein the second terminal voltage is used to indicate the voltage of the second terminal in the converter, and the superimposed voltage has the same polarity as the voltage of the first bridge arm.

[0033] In another aspect, the present application provides a control device for a converter, which may include:

[0034] The injection module is used to inject the zero-sequence voltage allowed to be injected into the converter.

[0035] The processing module is used to discretize the voltage variation of the bridge arm capacitor in the converter to obtain the voltage of the bridge arm capacitor in the next sampling period.

[0036] The control module is used to balance and control the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period.

[0037] Furthermore, the control device also includes a determination module.

[0038] The determination module is used to determine the zero-sequence voltage allowed to be injected according to the maximum modulation ratio of the converter.

[0039] In some possible implementations, the injection module determines the zero-sequence voltage allowed to be injected according to the following formula:

[0040]

[0041] Among them, v Z1 Indicates the zero-sequence voltage allowed to be injected; max Indicates the maximum modulation ratio of the converter; V C represents the reference voltage of the submodule capacitor; sgn represents the sign function; u1 represents the voltage at the first end of the converter, satisfying u1=V1cos(ω1t), V1 represents the voltage amplitude at the first end of the converter, ω1 represents the angular frequency at the first end of the converter, and t represents time; u2 represents the voltage at the second end of the converter, satisfying u2=V2cos(ω2t+θ), V2 represents the voltage amplitude at the second end of the converter, ω2 represents the angular frequency at the second end of the converter, and θ represents the phase of u2 leading u1; u b1 represents the voltage of the first bridge arm in the converter, satisfying u b1 =sgn(u1)u1oru b1 =sgn(u1+v Z1 )(u1+v Z1 );u b2 represents the voltage of the second bridge arm in the converter, satisfying u b2 =sgn(u2)u2-sgn(u1)u1 or u b2 =sgn(u2+v Z1 )(u2+v Z1 )-sgn(u1+v Z1 )(u1+v Z1 ).

[0042] In some other possible implementations, the processing module determines the voltage change of the bridge arm capacitor according to the following formula:

[0043]

[0044] in, represents the voltage change of the bridge arm capacitor; N represents the number of submodules in the first bridge arm or the second bridge arm; C represents the capacitance of the submodule capacitor; u C represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm; p represents the power of the first bridge arm or the second bridge arm after the injection of the allowed zero-sequence voltage, satisfying p = u b1 i b1 or p=u b2 i b2 ,i b1 Represents the current of the first bridge arm, satisfying i b1 =sgn(u1)i1+sgn(u2)i2,i b2Represents the current of the second bridge arm, satisfying i b2 =sgn(u2)i2, i1 represents the current at the first end of the converter, satisfying I1 represents the current amplitude at the first end of the converter, represents the power factor angle at the first end of the converter, i2 represents the current at the second end of the converter, satisfying I2 represents the current amplitude at the second end of the converter, represents the power factor angle at the second end of the converter.

[0045] In some other possible implementations, the processing module determines the voltage of the bridge arm capacitor in the next sampling period according to the following formula:

[0046]

[0047] Among them, u C (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the converter in the sampling period k+1, u C (k) represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k, p(k) represents the power of the first bridge arm or the second bridge arm in the sampling period k after the injection of the allowed zero-sequence voltage, T represents the sampling time, N represents the number of sub-modules of the first bridge arm or the second bridge arm; C represents the capacitance of the sub-module capacitor.

[0048] Optionally, the control module is used to:

[0049] The cost function is constructed according to the voltage of the bridge arm capacitor in the next sampling period.

[0050] With the goal of minimizing the function value of the cost function, the zero-sequence voltage allowed to be injected is adjusted.

[0051] Exemplarily, the control module determines the cost function as follows:

[0052] J(k+1)=||Δu C (k+1)|| p

[0053] Where J(k+1) represents the cost function within the sampling period k+1; ||·|| p represents the p-norm; Δu C (k+1) represents the error vector between the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k+1 and the reference voltage; Δu C (k+1) satisfies:

[0054] Δu C (k+1)=(u C1 (k+1)-U C0 ,uC2 (k+1)-U C0 ,…,u Cn (k+1)-U C0 ) T

[0055] Among them, u C1 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the first phase at sampling period k+1, u C2 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the second phase at sampling period k+1, u Cn (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the nth phase in the sampling period k+1, U C0 represents the reference voltage of the bridge arm capacitance of the first bridge arm or the second bridge arm, and T represents transposition.

[0056] Optionally, the converter includes a first bridge arm, a second bridge arm, a first inversion unit and a second inversion unit.

[0057] The first ends of the first bridge arm, the second bridge arm and the first inversion unit are connected, the second end of the second bridge arm is connected to the first end of the second inversion unit, and the second ends of the first inversion unit, the first bridge arm and the second inversion unit are connected.

[0058] The first bridge arm is used to generate a voltage of the first bridge arm.

[0059] The second bridge arm is used to generate a voltage of the second bridge arm.

[0060] The first inversion unit is used to: invert the polarity of the voltage of the first bridge arm according to the first preset frequency and the first preset phase angle to generate a first terminal voltage that alternates between positive and negative; wherein the first terminal voltage is used to indicate the voltage of the first terminal in the converter.

[0061] The second inversion unit is used to: superimpose the voltage of the first bridge arm and the voltage of the second bridge arm, and reverse the polarity of the superimposed voltage according to the second preset frequency and the second preset phase angle to generate a second terminal voltage that alternates between positive and negative; wherein the second terminal voltage is used to indicate the voltage of the second terminal in the converter, and the superimposed voltage has the same polarity as the voltage of the first bridge arm.

[0062] On the other hand, the present application also provides a computer device, including: one or more processors.

[0063] A processor is used to execute one or more programs.

[0064] When one or more programs are executed by one or more processors, the control method as described above is implemented.

[0065] In another aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed, the control method described above is implemented.

[0066] Compared with the prior art, the beneficial effects of this application are:

[0067] In the control method of the converter provided by the present application, the injected zero-sequence voltage is allowed to be injected into the converter, and the voltage of the bridge arm capacitor will change. The voltage change of the bridge arm capacitor can be discretized to obtain the voltage of the bridge arm capacitor in the next sampling period. And the bridge arm capacitor is balanced and controlled according to the voltage of the bridge arm capacitor in the next sampling period. The present application realizes the balanced control of the bridge arm capacitor, ensures the long-term reliable operation of the converter, that is, improves the operating reliability of the converter.

[0068] On the basis of ensuring the long-term reliable operation of the converter, the present application can also increase the voltage range of the converter output (which can be an industrial frequency voltage range or a low-frequency voltage range, etc.), so that the converter is suitable for scenarios with higher requirements on the voltage range.

[0069] The present application can reduce the voltage variation of the bridge arm capacitor, thereby reducing the cost of the submodule and improving the economy of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0071] Figure 1 A schematic flow chart of a method for controlling a converter in an embodiment of the present application;

[0072] Figure 2 is a schematic structural diagram of a converter in an embodiment of the present application;

[0073] Figure 3 is another schematic structural diagram of a converter in an embodiment of the present application;

[0074] Figure 4a 1 is a schematic structural diagram of a half-bridge submodule HBSM in an embodiment of the present application;

[0075] Figure 4b A schematic structural diagram of a full-bridge submodule FBSM in an embodiment of the present application;

[0076] Figure 5A schematic structural diagram of a control device for a converter in an embodiment of the present application. DETAILED DESCRIPTION

[0077] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0078] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0079] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0080] Embodiment 1:

[0081] The present application provides a control method for a converter, such as Figure 1 The control method may include the following steps:

[0082] Step S1: injecting the zero-sequence voltage allowed to be injected into the converter.

[0083] Step S2: discretize the voltage variation of the bridge arm capacitor in the converter (may be forward Euler discretization, etc.) to obtain the voltage of the bridge arm capacitor in the next sampling period.

[0084] Step S3: balance control is performed on the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period.

[0085] Furthermore, the control method provided in the embodiment of the present application also includes: determining the zero-sequence voltage allowed to be injected according to the maximum modulation ratio of the converter.

[0086] like Figure 2 and Figure 3 As shown, the converter in the embodiment of the present application includes a first bridge arm 1, a second bridge arm 2, a first inversion unit 3 and a second inversion unit 4.

[0087] The first ends of the first bridge arm 1, the second bridge arm 2 and the first inversion unit 3 are connected, the second end of the second bridge arm 2 is connected to the first end of the second inversion unit 4, and the second ends of the first inversion unit 3, the first bridge arm 1 and the second inversion unit 4 are connected.

[0088] The first bridge arm 1 is used to generate a voltage u of the first bridge arm. b1 The voltage of the first bridge arm may be a half-wave voltage.

[0089] The second bridge arm 2 is used to generate a voltage u of the second bridge arm. b2 The voltage of the second bridge arm may also be two half-wave voltages.

[0090] The first inversion unit 3 is used to: according to the first preset frequency and the first preset phase angle, the voltage u of the first bridge arm b1 The polarity is reversed to generate a first terminal voltage u1 which is alternating between positive and negative. The first terminal voltage u1 is used to indicate the voltage at the first terminal of the converter.

[0091] The second inversion unit 4 is used to convert the voltage u of the first bridge arm b1 and the voltage u of the second bridge arm b2 The voltage obtained by superposition is reversed in polarity according to the second preset frequency and the second preset phase angle to generate a second terminal voltage u2 that alternates between positive and negative. The second terminal voltage u2 is used to indicate the voltage of the second terminal in the converter, and the voltage obtained by superposition has the same polarity as the voltage of the first bridge arm.

[0092] Furthermore, the converter provided in the embodiment of the present application may also include a bridge arm inductor L arm , bridge arm inductance L arm It can be connected between the first bridge arm 1 and the second bridge arm 2.

[0093] Optionally, the first bridge arm 1 and the second bridge arm 2 each include a plurality of sub-modules SM connected in series. In the embodiment of the present application, the first bridge arm 1 may adopt a half-bridge sub-module HBSM, such as Figure 4a The second bridge arm 2 can use a full bridge submodule FBSM, such as Figure 4b shown.

[0094] Requirements for determining the zero-sequence voltage range allowed for injection include: no overmodulation occurs in the first bridge arm 1 and the second bridge arm 2, and the preset frequency and preset phase angle of polarity reversal in the first reversal unit 3 and the second reversal unit 4 remain unchanged.

[0095] In some possible implementations, the zero-sequence voltage allowed to be injected in the above step S1 satisfies:

[0096]

[0097] Among them, v Z1 Indicates the zero-sequence voltage allowed to be injected; max Indicates the maximum modulation ratio of the converter; V C represents the reference voltage of the submodule capacitor; sgn represents the sign function; u1 represents the voltage at the first end of the converter, satisfying u1=V1cos(ω1t), V1 represents the voltage amplitude at the first end of the converter, ω1 represents the angular frequency at the first end of the converter, and t represents time; u2 represents the voltage at the second end of the converter, satisfying u2=V2cos(ω2t+θ), V2 represents the voltage amplitude at the second end of the converter, ω2 represents the angular frequency at the second end of the converter, and θ represents the phase of u2 leading u1; u b1 represents the voltage of the first bridge arm in the converter, satisfying u b1 =sgn(u1)u1oru b1 =sgn(u1+v Z1 )(u1+v Z1 );u b2 Represents the voltage of the second bridge arm in the converter, satisfying: u b2 =sgn(u2)u2-sgn(u1)u1 or u b2 =sgn(u2+v Z1 )(u2+v Z1 )-sgn(u1+v Z1 )(u1+v Z1 )

[0098] In some other possible implementations, the voltage change of the bridge arm capacitor in the above step S2 satisfies:

[0099]

[0100] in, represents the voltage change of the bridge arm capacitor; N represents the number of submodules in the first bridge arm or the second bridge arm; C represents the capacitance of the submodule capacitor; u C represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm; p represents the power of the first bridge arm or the second bridge arm after the injection of the allowed zero-sequence voltage, satisfying p = u b1 i b1 or p=u b2 i b2 ,i b1 Represents the current of the first bridge arm, satisfying i b1=sgn(u1)i1+sgn(u2)i2,i b2 Represents the current of the second bridge arm, satisfying i b2 =sgn(u2)i2, i1 represents the current at the first end of the converter, satisfying I1 represents the current amplitude at the first end of the converter, represents the power factor angle at the first end of the converter, i2 represents the current at the second end of the converter, satisfying I2 represents the current amplitude at the second end of the converter, represents the power factor angle at the second end of the converter.

[0101] In the embodiment of the present application, the power p of the first bridge arm or the second bridge arm after the injection of the zero-sequence voltage allowed to be injected can satisfy:

[0102] p=u b2 i b2

[0103] =[sgn(u2)u2-sgn(u1+v Z1 )(u1+v Z1 )]sgn(u2)i2

[0104] =u2i2-sgn(u1+v Z1 )(u1+v Z1 )sgn(u2)i2

[0105] Voltage change of bridge arm capacitor satisfy:

[0106]

[0107] Since there exists sgn(u1)=sgn(u1+v Z1 ), the voltage change of the bridge arm capacitor And it can satisfy:

[0108]

[0109] In some other possible implementations, the voltage of the bridge arm capacitor in the above step S2 in the next sampling period satisfies:

[0110]

[0111] Among them, u C (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the converter in the sampling period k+1, u C(k) represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k, p(k) represents the power of the first bridge arm or the second bridge arm in the sampling period k after the injection of the allowed zero-sequence voltage, T represents the sampling time, N represents the number of sub-modules of the first bridge arm or the second bridge arm; C represents the capacitance of the sub-module capacitor.

[0112] In the embodiment of the present application, the voltage change of the bridge arm capacitor in the converter is processed by forward Euler discretization, and the voltage u of the bridge arm capacitor in the next sampling period is obtained. C (k+1) can satisfy:

[0113]

[0114] Optionally, in the above step S3, balancing and controlling the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period may specifically include:

[0115] The cost function is constructed according to the voltage of the bridge arm capacitor in the next sampling period.

[0116] With the goal of minimizing the function value of the cost function, the zero-sequence voltage allowed to be injected is adjusted.

[0117] Different zero-sequence voltages will affect the bridge arm power, and thus produce different bridge arm capacitor voltages during the sampling period. There will be different errors between the bridge arm capacitor voltage during the sampling period and the reference voltage of the bridge arm capacitor. Therefore, in order to maintain the bridge arm capacitor voltage balance, the constructed cost function can satisfy:

[0118] J(k+1)=||Δu C (k+1)|| p

[0119] Where J(k+1) represents the cost function within the sampling period k+1; ||·|| p represents the p-norm; Δu C (k+1) represents the error vector between the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k+1 and the reference voltage; Δu C (k+1) satisfies:

[0120] Δu C (k+1)=(u C1 (k+1)-U C0 ,u C2 (k+1)-U C0 ,…,u C n(k+1)-U C0 ) T ,u C1 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the first phase at sampling period k+1, uC2 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the second phase at sampling period k+1, u Cn (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the nth phase in the sampling period k+1, U C0 represents the reference voltage of the bridge arm capacitance of the first bridge arm or the second bridge arm, and T represents transposition.

[0121] The embodiment of the present application takes a three-phase converter (ie, n=3) and the p-norm as the Euclidean norm as an example, so the cost function can satisfy:

[0122]

[0123] Embodiment 2:

[0124] Based on the same inventive concept, the embodiment of the present application also provides a control device for a converter, such as Figure 5 As shown, this may include:

[0125] The injection module 21 is used to inject the zero-sequence voltage allowed to be injected into the converter.

[0126] The processing module 22 is used to discretize the voltage variation of the bridge arm capacitor in the converter to obtain the voltage of the bridge arm capacitor in the next sampling period.

[0127] The control module 23 is used to balance and control the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period.

[0128] For the specific structure of the inverter, please refer to Figure 2 and Figure 3 As well as the related introduction in the previous text, the embodiments of the present application will not be repeated here.

[0129] Furthermore, the control device also includes a determination module 24 .

[0130] The determination module 24 is used to determine the zero-sequence voltage allowed to be injected according to the maximum modulation ratio of the converter.

[0131] In some possible implementations, the injection module 21 determines the zero-sequence voltage allowed to be injected according to the following formula:

[0132]

[0133] Among them, v Z1 Indicates the zero-sequence voltage allowed to be injected; max Indicates the maximum modulation ratio of the converter; V Crepresents the reference voltage of the submodule capacitor; sgn represents the sign function; u1 represents the voltage at the first end of the converter, satisfying u1=V1cos(ω1t), V1 represents the voltage amplitude at the first end of the converter, ω1 represents the angular frequency at the first end of the converter, and t represents time; u2 represents the voltage at the second end of the converter, satisfying u2=V2cos(ω2t+θ), V2 represents the voltage amplitude at the second end of the converter, ω2 represents the angular frequency at the second end of the converter, and θ represents the phase of u2 leading u1; u b1 represents the voltage of the first bridge arm in the converter, satisfying u b1 =sgn(u1)u1oru b1 =sgn(u1+v Z1 )(u1+v Z1 );u b2 Represents the voltage of the second bridge arm in the converter, satisfying: u b2 =sgn(u2)u2-sgn(u1)u1 or u b2 =sgn(u2+v Z1 )(u2+v Z1 )-sgn(u1+v Z1 )(u1+v Z1 ).

[0134] In some other possible implementations, the processing module 22 determines the voltage change of the bridge arm capacitor according to the following formula:

[0135]

[0136] in, represents the voltage change of the bridge arm capacitor; N represents the number of submodules in the first bridge arm or the second bridge arm; C represents the capacitance of the submodule capacitor; u C represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm; p represents the power of the first bridge arm or the second bridge arm after the injection of the allowed zero-sequence voltage, satisfying p = u b1 i b1 or p=u b2 i b2 ,i b1 Represents the current of the first bridge arm, satisfying i b1 =sgn(u1)i1+sgn(u2)i2,i b2 Represents the current of the second bridge arm, satisfying i b2 =sgn(u2)i2, i1 represents the current at the first end of the converter, satisfying I1 represents the current amplitude at the first end of the converter, represents the power factor angle at the first end of the converter, i2 represents the current at the second end of the converter, satisfying I2 represents the current amplitude at the second end of the converter, represents the power factor angle at the second end of the converter.

[0137] In some other possible implementations, the processing module 22 determines the voltage of the bridge arm capacitor in the next sampling period according to the following formula:

[0138]

[0139] Among them, u C (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the converter in the sampling period k+1, u C (k) represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k, p(k) represents the power of the first bridge arm or the second bridge arm in the sampling period k after the injection of the allowed zero-sequence voltage, T represents the sampling time, N represents the number of sub-modules of the first bridge arm or the second bridge arm; C represents the capacitance of the sub-module capacitor.

[0140] Optionally, the control module 23 is used for:

[0141] The cost function is constructed according to the voltage of the bridge arm capacitor in the next sampling period.

[0142] With the goal of minimizing the function value of the cost function, the zero-sequence voltage allowed to be injected is adjusted.

[0143] Exemplarily, the control module 23 determines the cost function according to the following formula:

[0144] J(k+1)=||Δu C (k+1)|| p

[0145] Where J(k+1) represents the cost function within the sampling period k+1; ||·|| p represents the p-norm; Δu C (k+1) represents the error vector between the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the sampling period k+1 and the reference voltage; Δu C (k+1) satisfies:

[0146] Δu C (k+1)=(u C1 (k+1)-U C0 ,u C2 (k+1)-U C0 ,…,u Cn (k+1)-U C0 ) T

[0147] u C1 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the first phase at sampling period k+1, uC2 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the second phase at sampling period k+1, u Cn (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the nth phase in the sampling period k+1, U C0 represents the reference voltage of the bridge arm capacitance of the first bridge arm or the second bridge arm, and T represents transposition.

[0148] Embodiment 3:

[0149] Based on the same inventive concept, the embodiment of the present application also provides a computer device, which includes a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., which are the computing core and control core of the terminal, which are suitable for implementing one or more instructions, and are specifically suitable for loading and executing one or more instructions in the computer storage medium to implement the corresponding method flow or corresponding functions, so as to implement the steps of the control method provided in the above embodiment.

[0150] Embodiment 4:

[0151] Based on the same inventive concept, the embodiment of the present application also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device for storing programs and data. It is understandable that the computer-readable storage medium here can include both built-in storage media in a computer device and, of course, an extended storage medium supported by the computer device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by a processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the steps of the control method provided in the above embodiment.

[0152] Those skilled in the art will appreciate that the embodiments of the application may be provided as methods, systems, or computer program products. Therefore, the application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0153] The application is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0154] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1A function specified in one or more boxes.

[0155] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0156] The above are merely embodiments of the application and are not intended to limit the application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the application are included in the scope of the claims of the pending application.

Claims

1. A method for controlling a converter, characterized in that: include: injecting a zero-sequence voltage allowed to be injected into the converter; Discretize the voltage variation of the bridge arm capacitor in the converter to obtain the voltage of the bridge arm capacitor in the next sampling period; The bridge arm capacitor is balanced and controlled according to the voltage of the bridge arm capacitor in the next sampling period.

2. The control method according to claim 1, characterized in that: The control method further comprises: The zero-sequence voltage allowed to be injected is determined according to the maximum modulation ratio of the converter.

3. The control method according to claim 1, characterized in that: The zero-sequence voltage allowed to be injected satisfies: Among them, v Z1 represents the zero-sequence voltage allowed to be injected; max represents the maximum modulation ratio of the converter; V C represents the reference voltage of the submodule capacitor in the converter; sgn represents the sign function; u1 represents the voltage at the first end of the converter, satisfying u1=V1cos(ω1t), V1 represents the voltage amplitude at the first end of the converter, ω1 represents the angular frequency at the first end of the converter, and t represents time; u2 represents the voltage at the second end of the converter, satisfying u2=V2cos(ω2t+θ), V2 represents the voltage amplitude at the second end of the converter, ω2 represents the angular frequency at the second end of the converter, and θ represents the phase of u2 leading u1; u b1 represents the voltage of the first bridge arm in the converter, satisfying u b1 =sgn(u1)u1oru b1 =sgn(u1+v Z1 )(u1+v Z1 );ub2 represents the voltage of the second bridge arm in the converter, satisfying u b2 =sgn(u2)u2-sgn(u1)u1 or u b2 =sgn(u2+v Z1 )(u2+v Z1 )-sgn(u1+v Z1 )(u1+v Z1 ).

4. The control method according to claim 3, characterized in that: The voltage variation of the bridge arm capacitor satisfies: in, represents the voltage change of the bridge arm capacitor; N represents the number of submodules of the first bridge arm or the second bridge arm; C represents the capacitance of the submodule capacitor; u C represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm; p represents the power of the first bridge arm or the second bridge arm after the injection of the zero-sequence voltage allowed to be injected, satisfying p=u b1 i b1 or p=u b2 i b2 ,i b1 represents the current of the first bridge arm, satisfying i b1 =sgn(u1)i1+sgn(u2)i2,i b2 represents the current of the second bridge arm, satisfying i b2 =sgn(u2)i2, i1 represents the current at the first end of the converter, satisfying I1 represents the current amplitude at the first end of the converter, represents the power factor angle of the first end of the converter, i2 represents the current of the second end of the converter, and satisfies I2 represents the current amplitude at the second end of the converter, represents the power factor angle of the second end of the converter.

5. The control method according to claim 1, characterized in that: The voltage of the bridge arm capacitor in the next sampling period satisfies: Among them, u C (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the converter in the sampling period k+1, u C (k) represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in sampling period k, p(k) represents the power of the first bridge arm or the second bridge arm in sampling period k after the zero-sequence voltage allowed to be injected is injected, T represents the sampling time, N represents the number of sub-modules of the first bridge arm or the second bridge arm; C represents the capacitance of the sub-module capacitor.

6. The control method according to claim 1, characterized in that: The balancing control of the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period includes: Constructing a cost function according to the voltage of the bridge arm capacitor in the next sampling period; The zero-sequence voltage allowed to be injected is adjusted with the goal of minimizing the function value of the cost function.

7. The control method according to claim 6, characterized in that: The cost function satisfies: J(k+1)=||Δu C (k+1)|| p Where J(k+1) represents the cost function within the sampling period k+1; ||·|| p represents the p-norm; Δu C (k+1) represents the error vector between the actual voltage of the bridge arm capacitor of the first bridge arm in the converter or the second bridge arm in the converter in the sampling period k+1 and the reference voltage; Δu C (k+1) satisfies: Δu C (k+1)=(u C1 (k+1)-U C0 ,u C2 (k+1)-U C0 ,…,u Cn (k+1)-U C0 ) T u C1 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the first phase at sampling period k+1, u C2 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the second phase at sampling period k+1, u Cn (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the nth phase in the sampling period k+1, U C0 represents the reference voltage of the bridge arm capacitance of the first bridge arm or the second bridge arm, and T represents transposition.

8. The control method according to any one of claims 1 to 7, characterized in that: The converter comprises a first bridge arm, a second bridge arm, a first inversion unit and a second inversion unit; The first ends of the first bridge arm, the second bridge arm and the first inversion unit are connected, the second end of the second bridge arm is connected to the first end of the second inversion unit, and the second ends of the first inversion unit, the first bridge arm and the second inversion unit are connected; The first bridge arm is used to: generate a voltage of the first bridge arm; The second bridge arm is used to: generate a voltage of the second bridge arm; The first inversion unit is used to: invert the polarity of the voltage of the first bridge arm according to a first preset frequency and a first preset phase angle to generate a first terminal voltage that alternates between positive and negative; wherein the first terminal voltage is used to indicate the voltage of the first terminal in the converter; The second inversion unit is used to: superimpose the voltage of the first bridge arm and the voltage of the second bridge arm, and reverse the polarity of the superimposed voltage according to a second preset frequency and a second preset phase angle to generate a second terminal voltage that alternates between positive and negative; wherein the second terminal voltage is used to indicate the voltage of the second terminal in the converter, and the superimposed voltage has the same polarity as the voltage of the first bridge arm.

9. A control device for an inverter, characterized in that: include: An injection module, used for injecting a zero-sequence voltage allowed to be injected into the converter; A processing module, used for discretizing the voltage variation of the bridge arm capacitor in the converter to obtain the voltage of the bridge arm capacitor in the next sampling period; The control module is used to balance and control the bridge arm capacitor according to the voltage of the bridge arm capacitor in the next sampling period.

10. The control device according to claim 9, characterized in that: The control device also includes a determination module; The determination module is used to determine the zero-sequence voltage allowed to be injected according to the maximum modulation ratio of the converter.

11. The control device according to claim 9, characterized in that: The injection module determines the zero-sequence voltage allowed to be injected according to the following formula: Among them, v Z1 represents the zero-sequence voltage allowed to be injected; max represents the maximum modulation ratio of the converter; V C represents the reference voltage of the submodule capacitor in the converter; sgn represents the sign function; u1 represents the voltage at the first end of the converter, satisfying u1=V1cos(ω1t), V1 represents the voltage amplitude at the first end of the converter, ω1 represents the angular frequency at the first end of the converter, and t represents time; u2 represents the voltage at the second end of the converter, satisfying u2=V2cos(ω2t+θ), V2 represents the voltage amplitude at the second end of the converter, ω2 represents the angular frequency at the second end of the converter, and θ represents the phase of u2 leading u1; u b1 represents the voltage of the first bridge arm in the converter, satisfying u b1 =sgn(u1)u1oru b1 =sgn(u1+v Z1 )(u1+v Z1 );ub2 represents the voltage of the second bridge arm in the converter, satisfying u b2 =sgn(u2)u2-sgn(u1)u1 or u b2 =sgn(u2+v Z1 )(u2+v Z1 )-sgn(u1+v Z1 )(u1+v Z1 ).

12. The control device according to claim 11, characterized in that: The processing module determines the voltage change of the bridge arm capacitor according to the following formula: in, represents the voltage change of the bridge arm capacitor; N represents the number of submodules of the first bridge arm or the second bridge arm; C represents the capacitance of the submodule capacitor; u C represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm; p represents the power of the first bridge arm or the second bridge arm after the injection of the zero-sequence voltage allowed to be injected, satisfying p=u b1 i b1 or p=u b2 i b2 ,i b1 represents the current of the first bridge arm, satisfying i b1 =sgn(u1)i1+sgn(u2)i2,i b2 represents the current of the second bridge arm, satisfying i b2 =sgn(u2)i2, i1 represents the current at the first end of the converter, satisfying I1 represents the current amplitude at the first end of the converter, represents the power factor angle of the first end of the converter, i2 represents the current of the second end of the converter, and satisfies I2 represents the current amplitude at the second end of the converter, represents the power factor angle of the second end of the converter.

13. The control device according to claim 9, characterized in that: The processing module determines the voltage of the bridge arm capacitor in the next sampling period according to the following formula: Among them, u C (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the converter in the sampling period k+1, u C (k) represents the actual voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in sampling period k, p(k) represents the power of the first bridge arm or the second bridge arm in sampling period k after the zero-sequence voltage allowed to be injected is injected, T represents the sampling time, N represents the number of sub-modules of the first bridge arm or the second bridge arm; C represents the capacitance of the sub-module capacitor.

14. The control device according to claim 9, characterized in that: The control module is used for: Constructing a cost function according to the voltage of the bridge arm capacitor in the next sampling period; The zero-sequence voltage allowed to be injected is adjusted with the goal of minimizing the function value of the cost function.

15. The control device according to claim 14, characterized in that: The control module determines the cost function as follows: J(k+1)=||Δu C (k+1)|| p Where J(k+1) represents the cost function within the sampling period k+1; ||·|| p represents the p-norm; Δu C (k+1) represents the error vector between the actual voltage of the bridge arm capacitor of the first bridge arm in the converter or the second bridge arm in the converter in the sampling period k+1 and the reference voltage; Δu C (k+1) satisfies: Δu C (k+1)=(u C1 (k+1)-U C0 ,u C2 (k+1)-U C0 ,…,u Cn (k+1)-U C0 ) T u C1 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the first phase at sampling period k+1, u C2 (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the second phase at sampling period k+1, u Cn (k+1) represents the voltage of the bridge arm capacitor of the first bridge arm or the second bridge arm in the nth phase in the sampling period k+1, U C0 represents the reference voltage of the bridge arm capacitance of the first bridge arm or the second bridge arm, and T represents transposition.

16. The control device according to any one of claims 9 to 15, characterized in that: The converter comprises a first bridge arm, a second bridge arm, a first inversion unit and a second inversion unit; The first ends of the first bridge arm, the second bridge arm and the first inversion unit are connected, the second end of the second bridge arm is connected to the first end of the second inversion unit, and the second ends of the first inversion unit, the first bridge arm and the second inversion unit are connected; The first bridge arm is used to: generate a voltage of the first bridge arm; The second bridge arm is used to: generate a voltage of the second bridge arm; The first inversion unit is used to: invert the polarity of the voltage of the first bridge arm according to a first preset frequency and a first preset phase angle to generate a first terminal voltage that alternates between positive and negative; wherein the first terminal voltage is used to indicate the voltage of the first terminal in the converter; The second inversion unit is used to: superimpose the voltage of the first bridge arm and the voltage of the second bridge arm, and reverse the polarity of the superimposed voltage according to a second preset frequency and a second preset phase angle to generate a second terminal voltage that alternates between positive and negative; wherein the second terminal voltage is used to indicate the voltage of the second terminal in the converter, and the superimposed voltage has the same polarity as the voltage of the first bridge arm.

17. A computer device, characterized in that: include: one or more processors; The processor is used to store one or more programs; When the one or more programs are executed by the one or more processors, the control method according to any one of claims 1 to 8 is implemented.

18. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed, the control method according to any one of claims 1 to 8 is implemented.

Images