Novel super-junction groove MOS power device and preparation method thereof

Abstract

The invention discloses a novel super-junction trench MOS power device and a preparation method thereof, and relates to the technical field of semiconductor devices. The base layer region is arranged on the upper surface of the substrate; the first P-type column and the second P-type column are arranged in the base layer area and are not adjacent to each other; the P-type layer is arranged on the upper surfaces of the first P-type column and the second P-type column; the first groove and the second groove penetrate through the P-type layer and are correspondingly arranged in the first P-type column and the second P-type column; the dielectric layer is arranged on the upper surfaces of the first groove and the second groove; the first contact hole, the second contact hole and the third contact hole penetrate through the dielectric layer and are correspondingly formed in one side of the first groove, one side of the second groove and the P-type layer between the two grooves; and the metal region is arranged in the first contact hole, the second contact hole, the third contact hole and the upper surface of the dielectric layer. The conduction and switching loss of the MOS power device can be reduced, and the impact resistance can be improved at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly to a novel super junction trench MOS power device and a preparation method thereof. Background Art

[0002] The third generation of semiconductor SiC MOS power devices has a very broad application space and has been applied to energy storage, charging piles, on-board chargers and main drive inverters of new energy vehicles. Since the physical properties of SiC materials are more suitable for manufacturing high-voltage and high-power power devices than Si, the current forefront of the development and design of new high-voltage and high-power power devices is semiconductor power devices using SiC materials.

[0003] However, the important factor limiting the application of existing SiC MOS power devices is how to further reduce the cost of devices and improve device performance, such as reducing the conduction and switching losses of devices and improving the impact resistance of devices to harsh environments. With the increase of unit cell density and current density, the chip area with the same on-resistance will become smaller and smaller, and the durability of power devices, such as avalanche resistance, will further deteriorate, which poses a great challenge to actual promotion and application.

[0004] Therefore, how to reduce the conduction and switching losses of MOS power devices and improve their impact resistance is an urgent problem that technicians in this field need to solve. Summary of the invention

[0005] In view of this, the present invention provides a novel super junction trench MOS power device and a preparation method thereof, which can reduce the conduction and switching losses of the MOS power device and improve the impact resistance.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] A novel super junction trench MOS power device, comprising:

[0008] substrate;

[0009] A base layer region disposed on the upper surface of the substrate;

[0010] A first P-type column and a second P-type column that are non-adjacent to each other and are disposed in the base layer region;

[0011] A P-type layer disposed on the upper surfaces of the first P-type column and the second P-type column;

[0012] A first groove and a second groove are formed in the first P-type column and the second P-type column respectively through the P-type layer;

[0013] A dielectric layer disposed on the upper surface of the first trench and the second trench;

[0014] A first contact hole, a second contact hole and a third contact hole are formed in the P-type layer at one side of the first trench, at one side of the second trench and between the two trenches through the dielectric layer;

[0015] A metal area is disposed in the first contact hole, the second contact hole, the third contact hole and on the upper surface of the dielectric layer.

[0016] Preferably, the base layer region includes a drift layer and a buffer layer in order from top to bottom;

[0017] The thickness of the drift layer is greater than the thickness of the buffer layer.

[0018] Preferably, the P-type layer includes: a source layer, a first P+ layer, a second P+ layer and a third P+ layer;

[0019] The source layer is located above the third P+ layer;

[0020] The first P+ layer, the second P+ layer and the third P+ layer are located at the bottom of the second contact hole, the first contact hole and the third contact hole respectively.

[0021] Preferably, a first gate oxide layer and a second gate oxide layer are formed on inner surfaces of the first trench and the second trench respectively;

[0022] The first gate oxide layer and the second gate oxide layer are both filled with polysilicon to form a first gate region and a second gate region respectively;

[0023] The first alloy layer, the second alloy layer and the third alloy layer are formed on the inner surfaces of the first contact hole, the second contact hole and the third contact hole respectively.

[0024] Preferably, the metal area includes, from top to bottom, a first metal layer, a second metal layer and a third metal layer;

[0025] A back metal layer is formed on the lower surface of the substrate as a drain region.

[0026] A novel method for preparing a super junction trench MOS power device, comprising:

[0027] forming a substrate, and forming a base layer region on an upper surface of the substrate;

[0028] forming a non-adjacent first P-type column and a second P-type column in the base layer region;

[0029] forming a P-type layer on upper surfaces of the first P-type column and the second P-type column;

[0030] Passing through the P-type layer, forming a first groove and a second groove in the first P-type column and the second P-type column respectively;

[0031] forming a dielectric layer on upper surfaces of the first trench and the second trench;

[0032] Passing through the dielectric layer, a first contact hole, a second contact hole and a third contact hole are formed in the P-type layer on one side of the first trench, on one side of the second trench and between the two trenches, respectively;

[0033] A metal region is formed in the first contact hole, in the second contact hole, in the third contact hole and on the upper surface of the dielectric layer.

[0034] Preferably, forming the base layer area specifically includes:

[0035] forming a buffer layer on the upper surface of the substrate;

[0036] forming a drift layer on an upper surface of the buffer layer;

[0037] The thickness of the drift layer is greater than the thickness of the buffer layer;

[0038] The buffer layer and the drift layer together constitute the base layer region.

[0039] Preferably, N-type doping ions are injected into corresponding positions in the P-type layer to form a source layer; P-type doping ions are injected into corresponding positions in the P-type layer to form a first P+ layer, a second P+ layer and a third P+ layer;

[0040] The source layer is located above the third P+ layer;

[0041] The first P+ layer, the second P+ layer and the third P+ layer are in direct contact with the bottoms of the second contact hole, the first contact hole and the third contact hole respectively.

[0042] Preferably, a first gate oxide layer and a second gate oxide layer are formed on the inner surfaces of the first trench and the second trench respectively;

[0043] Filling polysilicon inside the first gate oxide layer and the second gate oxide layer to form a first gate region and a second gate region respectively;

[0044] A first alloy layer, a second alloy layer and a third alloy layer are formed on inner surfaces of the first contact hole, the second contact hole and the third contact hole respectively.

[0045] Preferably, forming the metal region specifically includes:

[0046] forming a first metal layer in the first alloy layer, in the second alloy layer, in the third alloy layer and on the upper surface of the dielectric layer;

[0047] forming a second metal layer on an upper surface of the first metal layer;

[0048] forming a third metal layer on the upper surface of the second metal layer;

[0049] The method also includes: forming a back metal layer on the lower surface of the substrate as a drain region.

[0050] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a novel super junction trench MOS power device and a preparation method thereof. By adopting a vertical trench MOS structure, the unit cell size can be smaller than that of a planar MOS, and the unit cell density per unit area can be increased, thereby improving the current density. By integrating the advantages of the trench MOS and the super junction structure, the current density of the device can be significantly improved, and the on-resistance per unit area can be reduced. By adopting a unique dual contact hole design concept, the two source contact methods can improve the durability of the device against the stress of the unclamped inductive load switching process (UIS), thereby significantly improving the device's avalanche resistance, making the device's on-resistance smaller and the switching loss lower. At the same time, the device has better limit resistance and is more rugged and durable. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0052] Figure 1 A schematic diagram of the structure of a novel super junction trench MOS power device provided in Example 2 of the present invention.

[0053] Figure 2 A schematic diagram of the connection of two unit cell structures provided in Example 2 of the present invention.

[0054] Figure 3 A flow chart of a novel method for preparing a super junction trench MOS power device provided in Example 3 of the present invention.

[0055] Figure 4 A schematic diagram of the structure of forming a base layer area, a first P-type column and a second P-type column provided in Example 4 of the present invention.

[0056] Figure 5 A schematic diagram of the structure of forming a P-type layer, a source layer, a first P+ layer, a second P+ layer and a third P+ layer provided in Embodiment 4 of the present invention.

[0057] Figure 6A schematic diagram of the structure for forming the first groove and the second groove provided in Example 4 of the present invention.

[0058] Figure 7 A schematic diagram of the structure of forming a first gate region, a second gate region and a dielectric layer provided in Embodiment 4 of the present invention.

[0059] Figure 8 A schematic diagram of the structure of forming a first contact hole, a second contact hole and a third contact hole provided in Embodiment 4 of the present invention.

[0060] Fig. 9 A schematic diagram of the structure for forming a metal region and a drain region provided in Example 4 of the present invention.

[0061] Figure numerals: 1—substrate, 2—base region, 21—drift layer, 22—buffer layer, 3—first P-type column, 4—second P-type column, 5—P-type layer, 51—source layer, 52—first P+ layer, 53—second P+ layer, 54—third P+ layer, 6—first trench, 61—first gate oxide layer, 62—first gate region, 7—second trench, 71—second gate oxide layer, 72—second gate region, 8—dielectric layer, 9—first contact hole, 91—first alloy layer, 10—second contact hole, 92—second alloy layer, 11—third contact hole, 93—third alloy layer, 12—metal region, 13—back metal layer, 131—fourth metal layer, 132—fifth metal layer, 14—passivation layer, 141—silicon nitride layer, 142—polyimide layer. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] Example 1

[0064] The embodiment of the present invention discloses a novel super junction trench MOS power device, comprising:

[0065] Substrate 1;

[0066] A base layer region 2 is provided on the upper surface of the substrate 1;

[0067] A first P-type column 3 and a second P-type column 4 are disposed in the base layer region 2 and are not adjacent to each other;

[0068] A P-type layer 5 disposed on the upper surface of the first P-type column 3 and the second P-type column 4;

[0069] Passing through the P-type layer 5, corresponding to the first groove 6 and the second groove 7 provided in the first P-type column 3 and the second P-type column 4;

[0070] A dielectric layer 8 disposed on the upper surfaces of the first trench 6 and the second trench 7;

[0071] Through the dielectric layer 8, a first contact hole 9, a second contact hole 10 and a third contact hole 11 are correspondingly arranged in the P-type layer 5 on one side of the first trench 6, on one side of the second trench 7 and between the two trenches;

[0072] The metal region 12 is disposed in the first contact hole 9 , the second contact hole 10 , the third contact hole 11 and on the upper surface of the dielectric layer 8 .

[0073] Example 2

[0074] like Figure 1 As shown, the embodiment of the present invention discloses a novel super junction trench MOS power device, including:

[0075] Substrate 1.

[0076] Preferably, in this embodiment, the substrate 1 is an N-type doped SiC substrate of type 4H SiC, with a resistivity between 0.015-0.025 Ohm / cm, and the surface of the substrate 1 is a silicon surface.

[0077] Preferably, the substrate 1 in this embodiment has the first type of conductivity (N-type conductivity).

[0078] A base layer region 2 is provided on the upper surface of the substrate 1 .

[0079] Preferably, the base layer 2 includes a drift layer 21 and a buffer layer 22 from top to bottom;

[0080] The thickness of the drift layer 21 is greater than the thickness of the buffer layer 22 .

[0081] Preferably, in this embodiment, the buffer layer 22 has a thickness of 10% of the thickness of the drift layer 21 , and a resistivity between that of the substrate 1 and the device drift layer 21 .

[0082] Preferably, in this embodiment, the buffer layer 22 is made of N-type doped SiC, the doping substance is nitrogen (N), and the doping concentration is 1×10 18 cm −3 .

[0083] Preferably, the drift layer 21 is an N-type doped SIC epitaxial layer, and the doping material is N. The doping concentration and thickness of the drift layer 21 are determined by various factors such as the withstand voltage and typical size of the device according to the charge compensation principle.

[0084] Preferably, in this embodiment, the drift layer 21 and the buffer layer 22 are formed by high temperature chemical vapor deposition (HTCVD).

[0085] The first P-type column 3 and the second P-type column 4 are disposed in the base layer area 2 and are not adjacent to each other.

[0086] Preferably, the first P-type column 3 and the second P-type column 4 both have second-type conductivity, the area between the first P-type column 3 and the second P-type column 4 is an N-type column, and the first P-type column 3 and the second P-type column 4 and the N-type column form a super junction structure based on the charge compensation principle.

[0087] Preferably, the first P-type column 3 and the second P-type column 4 have the same size, depth and conductivity and follow the charge compensation principle.

[0088] Preferably, the first P-type column 3 and the second P-type column 4 are formed by injecting P-type ions (such as aluminum ions or boron ions), and aluminum ions are used in this embodiment.

[0089] A P-type layer 5 is disposed on the first P-type pillar 3 and the second P-type pillar 4 .

[0090] Preferably, the P-type layer 5 includes: a source layer 51, a first P+ layer 52, a second P+ layer 53 and a third P+ layer 54;

[0091] The source layer 51 is located above the third P+ layer 54;

[0092] The first P+ layer 52 , the second P+ layer 53 and the third P+ layer 54 are located at the bottom of the second contact hole 10 , the first contact hole 9 and the third contact hole 11 respectively.

[0093] The first trench 6 and the second trench 7 are formed in the first P-type column 3 and the second P-type column 4 respectively through the P-type layer 5 .

[0094] Preferably, a first gate oxide layer 61 and a second gate oxide layer 71 are formed on the inner surfaces of the first trench 6 and the second trench 7 respectively;

[0095] The first gate oxide layer 61 and the second gate oxide layer 71 are filled with polysilicon to form a first gate region 62 and a second gate region 72 respectively;

[0096] A first alloy layer 91 , a second alloy layer 92 , and a third alloy layer 93 are formed on the inner surfaces of the first contact hole 9 , the second contact hole 10 , and the third contact hole 11 , respectively.

[0097] Preferably, the first gate oxide layer 61 and the second gate oxide layer 62 are both made of SiO 2 .

[0098] Preferably, the first gate region 62 and the second gate region 72 together constitute a gate region.

[0099] Preferably, this two-source contact method can improve the device's durability against the stress of the un-clamped inductive load switching process (UIS). In fact, since the holes generated during the avalanche caused by UIS are mainly collected by the contact holes connected by the P-type columns, rather than by the contact holes connecting the source layer 51 and the P-type layer 5, the parasitic NPN of the device is more difficult to latch.

[0100] Preferably, in this embodiment, N-type heavily doped polysilicon is filled, and the doping material is phosphorus.

[0101] A dielectric layer 8 is disposed on the upper surfaces of the first trench 6 and the second trench 7 .

[0102] Preferably, the dielectric layer 8 of this embodiment is a combination of undoped silicate glass (USG) and boron-phosphorus silicate glass (BPSG):

[0103] First, a layer of USG is deposited as a base insulating layer, and then BPSG is deposited thereon to form a dielectric layer 8 together.

[0104] The dielectric layer 8 is penetrated to form a first contact hole 9 , a second contact hole 10 and a third contact hole 11 in the P-type layer 5 at one side of the first trench 6 , at one side of the second trench 7 and between the two trenches.

[0105] Preferably, Figure 2 As shown, since the trench MOS power device of the present invention is composed of a plurality of trench MOS device cells repeatedly arranged in parallel, the present invention only shows the structure of each cell. In the figure, the width of the first contact hole 9 and the second contact hole 10 are the same, that is, the first contact hole 9 and the second contact hole 10 are both half holes, so the first contact hole 9 and the second contact hole 10 together constitute a complete contact hole, that is, the first complete contact hole; the third contact hole 11 serves as the second complete contact hole.

[0106] Similarly, the first P+ layer 52 and the second P+ layer 53 together constitute a complete P+ layer, namely, the first complete P+ layer; and the third P+ layer 54 serves as the second complete P+ layer.

[0107] The first alloy layer 91 and the second alloy layer 92 together form a complete alloy layer, namely, a first complete alloy layer; the third alloy layer 93 serves as a second complete alloy layer.

[0108] A metal region 12 is disposed in the first contact hole 9 , the second contact hole 10 , the third contact hole 11 and on the upper surface of the dielectric layer 8 .

[0109] Preferably, a first alloy layer 91 , a second alloy layer 92 , and a third alloy layer 93 are formed on the inner surfaces of the first contact hole 9 , the second contact hole 10 , and the third contact hole 11 , respectively.

[0110] Preferably, the first alloy layer 91 , the second alloy layer 92 and the third alloy layer 93 are all nickel silicide.

[0111] Preferably, the metal region 12 includes, from top to bottom, a first metal layer, a second metal layer and a third metal layer; the first contact hole 9, the second contact hole 10 and the third contact hole 11 and the first metal layer, the second metal layer and the third metal layer connecting these contact holes together constitute the source region.

[0112] Preferably, in this embodiment, the first metal layer is an aluminum-copper alloy layer; the second metal layer is a titanium nitride layer; the third metal layer is a titanium metal layer; and the thickness of the first metal layer is greater than the thickness of the second metal layer and the third metal layer.

[0113] Preferably, a back metal layer 13 is formed on the lower surface of the substrate 1 as a drain region.

[0114] Preferably, the back metal layer 13 includes, from top to bottom, a fourth metal layer 131 and a fifth metal layer 132 .

[0115] Preferably, in this embodiment, the fourth metal layer 131 is a nickel silicide layer for better forming ohmic contact and reducing contact resistance; the fifth metal layer 132 is a titanium-nickel-silver alloy layer.

[0116] Example 3

[0117] like Figure 3 As shown, a novel method for preparing a super junction trench MOS power device comprises:

[0118] A substrate 1 is formed, and a base layer region 2 is formed on an upper surface of the substrate 1;

[0119] Forming a non-adjacent first P-type column 3 and a second P-type column 4 in the base layer region 2;

[0120] Forming a P-type layer 5 on the upper surfaces of the first P-type column 3 and the second P-type column 4;

[0121] Passing through the P-type layer 5, a first trench 6 and a second trench 7 are formed in the first P-type column 3 and the second P-type column 4 respectively;

[0122] forming a dielectric layer 8 on the upper surfaces of the first trench 6 and the second trench 7;

[0123] A first contact hole 9, a second contact hole 10 and a third contact hole 11 are formed through the dielectric layer 8, and in the P-type layer 5 on one side of the first trench 6, on one side of the second trench 7 and between the two trenches;

[0124] A metal region 12 is formed in the first contact hole 9 , in the second contact hole 10 , in the third contact hole 11 and on the upper surface of the dielectric layer 8 .

[0125] Example 4

[0126] A novel method for preparing a super junction trench MOS power device, comprising:

[0127] like Figure 4 As shown, a substrate 1 is formed, and a base layer region 2 is formed on the upper surface of the substrate 1 .

[0128] Preferably, N-type doped SiC is used to form the substrate 1. In this embodiment, the substrate 1 is 4H SiC with a resistivity between 0.015-0.025 Ohm / cm. The surface of the substrate 1 is a silicon surface.

[0129] Preferably, forming the base layer area 2 specifically includes:

[0130] forming a buffer layer 22 on the upper surface of the substrate 1;

[0131] forming a drift layer 21 on the upper surface of the buffer layer 22;

[0132] The thickness of the drift layer 21 is greater than the thickness of the buffer layer 22;

[0133] The buffer layer 22 and the drift layer 21 together constitute a base layer region.

[0134] Preferably, in this embodiment, the buffer layer 22 has a thickness of 10% of the thickness of the drift layer 21 , and a resistivity between that of the substrate 1 and the device drift layer 21 .

[0135] Preferably, the buffer layer 22 is an N-type doped SiC epitaxial layer, the doping material is nitrogen, and the doping concentration is 1×10 18 cm −3 ; The buffer layer 22 can avoid bipolar degradation caused by the operation of the device.

[0136] Preferably, the drift layer 21 is an N-type doped SiC epitaxial layer, and the doping material is N. The doping concentration and thickness of the drift layer 21 are determined by various factors such as the withstand voltage and typical size of the device according to the charge compensation principle.

[0137] Preferably, in this embodiment, the drift layer 21 and the buffer layer 22 are formed by high temperature chemical vapor deposition (HTCVD).

[0138] A first P-type column 3 and a second P-type column 4 that are not adjacent to each other are formed in the base layer region 2 .

[0139] Preferably, by injecting P-type doping ions (such as Al ions) multiple times at corresponding positions in the drift layer 21, a first P-type column 3 and a second P-type column 4 are correspondingly formed;

[0140] Alternatively, a corresponding groove is formed in the drift layer 21 where the P-type column is to be formed by photolithography, and a P-type doped P-type column is epitaxially grown in the groove to form a first P-type column 3 and a second P-type column 4;

[0141] Alternatively, the MI2 technology is used to directly inject P-type doping ions (such as AI ions) into the target area in the drift layer 21 at a high energy to form the first P-type column 3 and the second P-type column 4 accordingly.

[0142] Preferably, in the drift layer 21, the region between the first P-type column 3 and the second P-type column 4 is an N-type column, and the width and thickness of the first P-type column 3, the second P-type column 4 and the N-type column are related to the withstand voltage and doping concentration of the device.

[0143] like Figure 5 As shown, a P-type layer 5 is formed on the upper surfaces of the first P-type column 3 and the second P-type column 4 .

[0144] Preferably, generating the P-type layer 5 specifically includes:

[0145] Tetraethoxysilane is used for CVD growth to form a hard mask on the upper surface of the first P-type column 3 and the second P-type column 4;

[0146] Performing photolithography pattern preparation of a P-type layer on the hard mask;

[0147] Based on the photolithography pattern of the P-type layer, the corresponding hard mask is removed by etching to obtain a first ion implantation region;

[0148] Al ion implantation is performed based on the first ion implantation region to form a P-type layer 5 .

[0149] Preferably, in another embodiment, a P-type doped epitaxial layer is grown on the upper surfaces of the first P-type column 3 and the second P-type column 4 to serve as the P-type layer 5 .

[0150] Preferably, N-type doping ions are implanted at corresponding positions in the P-type layer 5 to form a source layer 51; P-type doping ions (such as Al ions) are implanted at corresponding positions in the P-type layer 5 to form a first P+ layer 52, a second P+ layer 53 and a third P+ layer 54;

[0151] The source layer 51 is located above the third P+ layer 54;

[0152] The first P+ layer 52 , the second P+ layer 53 and the third P+ layer 54 are in direct contact with the bottoms of the second contact hole 10 , the first contact hole 9 and the third contact hole 11 , respectively.

[0153] Preferably, forming the source layer 51 specifically includes:

[0154] Tetraethoxysilane is used for CVD growth to form a hard mask on the upper surface of the P-type layer, and source photolithography pattern preparation is performed on the hard mask;

[0155] Based on the source photolithography pattern, the corresponding hard mask is removed by etching to obtain a second ion implantation region;

[0156] N-type doping ions are implanted based on the second ion implantation region to form a source layer 51 .

[0157] Preferably, forming the first P+ layer 52, the second P+ layer 53 and the third P+ layer 54 specifically includes:

[0158] Tetraethoxysilane is used for CVD growth to form a hard mask on the upper surface of the P-type layer, and a P+ photolithography pattern is prepared on the hard mask;

[0159] Based on the P+ photolithography pattern, the corresponding hard mask is removed by etching to obtain a third ion implantation region, a fourth ion implantation region, and a fifth ion implantation region;

[0160] Based on the third ion implantation region, the fourth ion implantation region and the fifth ion implantation region, P-type doping ions are implanted to form a first P+ layer 52 , a second P+ layer 53 and a third P+ layer 54 .

[0161] Preferably, after forming the P-type layer 5, the source layer 51, the first P+ layer 52, the second P+ layer 53 and the third P+ layer 54, the hard mask is removed, and a new layer of photoresist is deposited on the upper surface of the P-type layer 5, and then the entire wafer is annealed at 1700 degrees Celsius.

[0162] like Figure 6 As shown, a first trench 6 and a second trench 7 are formed in the first P-type column 3 and the second P-type column 4 through the P-type layer 5 .

[0163] Preferably, the photoresist is removed after annealing to form a hard mask on the upper surface of the P-type layer 5;

[0164] A first trench 6 and a second trench 7 are formed in the first P-type column 3 and the second P-type column 4 respectively by dry etching;

[0165] After the trenches are prepared, annealing is performed in hydrogen.

[0166] like Figure 7 As shown, a dielectric layer 8 is formed on the upper surfaces of the first trench 6 and the second trench 7 .

[0167] Preferably, a first gate oxide layer 61 and a second gate oxide layer 71 are formed on the inner surfaces of the first trench 6 and the second trench 7 respectively;

[0168] Polysilicon is filled inside the first gate oxide layer 61 and the second gate oxide layer 71 to form a first gate region 62 and a second gate region 72 correspondingly.

[0169] Preferably, chemical mechanical polishing is performed after filling the polysilicon, and then a dielectric layer 8 is formed on the upper surfaces of the first gate region 62 and the second gate region 72 , and finally a high temperature annealing operation is performed.

[0170] Preferably, the dielectric layer 8 of this embodiment is a combination of undoped silicate glass (USG) and boron-phosphorus silicate glass (BPSG):

[0171] First, a layer of USG is deposited as a base insulating layer, and then BPSG is deposited thereon to form a dielectric layer 8 together.

[0172] like Figure 8 As shown, a first contact hole 9, a second contact hole 10 and a third contact hole 11 are formed through the dielectric layer 8, and correspondingly in the P-type layer 5 on one side of the first trench 6, on one side of the second trench 7 and between the two trenches.

[0173] Preferably, contact hole photolithography pattern preparation and contact hole etching are performed on the upper surface of the dielectric layer 8 using standard processes to form the first contact hole 9 , the second contact hole 10 and the third contact hole 11 .

[0174] like Fig. 9 As shown, a metal region 12 is formed in the first contact hole 9 , in the second contact hole 10 , in the third contact hole 11 and on the upper surface of the dielectric layer 8 .

[0175] Preferably, after growing a layer of Ni, a first alloy layer 91, a second alloy layer 92 and a third alloy layer 93 are correspondingly formed on the inner surfaces of the first contact hole 9, the second contact hole 10 and the third contact hole 11 by high temperature annealing, and then the Ni residue is removed by standard process.

[0176] Preferably, the first alloy layer 91 , the second alloy layer 92 and the third alloy layer 93 are all nickel silicide.

[0177] Preferably, forming the metal region specifically includes:

[0178] A first metal layer is formed in the first alloy layer 91, in the second alloy layer 92, in the third alloy layer 93 and on the upper surface of the dielectric layer 8;

[0179] forming a second metal layer on an upper surface of the first metal layer;

[0180] A third metal layer is formed on an upper surface of the second metal layer.

[0181] Preferably, a third metal layer, a second metal layer and a first metal layer are formed in sequence from bottom to top in the first alloy layer 91, the second alloy layer 92 and the third alloy layer 93 and on the upper surface of the dielectric layer 8; the first contact hole 9, the second contact hole 10 and the third contact hole 11 and the first metal layer, the second metal layer and the third metal layer connecting these contact holes together constitute the source region.

[0182] Preferably, in this embodiment, the first metal layer is an aluminum-copper alloy layer; the second metal layer is a titanium nitride layer; the third metal layer is a titanium metal layer; and the thickness of the first metal layer is greater than the thickness of the second metal layer and the third metal layer.

[0183] Preferably, a metal photolithography layer pattern is prepared on the upper surface of the first metal layer and metal etching is performed, and the third metal layer, the second metal layer and the first metal layer are removed in areas where these three metals are not needed, so that the metal connected to the gate and the metal connected to the source are separated, thereby forming a source and a gate respectively.

[0184] Preferably, after metal etching is performed on the upper surface of the first metal layer, a silicon nitride layer 141 and a polyimide layer 142 are sequentially deposited to form a passivation layer 14; corresponding passivation layer etching pattern preparation (passivation layer potomasking) is performed on the passivation layer and the passivation layer is etched, and the passivation layer is removed in the chip area where the silicon nitride layer 141 and the polyimide layer 142 are not needed. The passivation layer etching pattern is related to the specific chip layout.

[0185] Preferably, the method further comprises: forming a back metal layer 13 on the lower surface of the substrate 1 as a drain region.

[0186] Preferably, the back metal layer 13 includes, from top to bottom, a fourth metal layer 131 and a fifth metal layer 132 .

[0187] Preferably, in this embodiment, the fourth metal layer 131 is a nickel silicide layer for better forming ohmic contact and reducing contact resistance; the fifth metal layer 132 is a titanium-nickel-silver alloy layer.

[0188] Preferably, the manufacturing of the device back side process is completed by wafer thinning, back side Ni deposition, back side laser annealing and Ti—Ni—Ag deposition.

[0189] Through the above technical solutions, it can be known that the present invention discloses a novel super junction trench MOS power device and a preparation method thereof. By adopting a vertical trench MOS structure, the size of the primitive cell can be smaller than that of a planar MOS, and the primitive cell density per unit area can be increased, thereby improving the current density; by integrating the advantages of the trench MOS and the super junction structure, the current density of the device can be significantly improved, and the on-resistance per unit area can be reduced; by adopting a unique dual contact hole design concept, the two source contact methods can improve the durability of the device against the stress of the unclamped inductive load switching process (UIS), and thus can significantly improve the device's avalanche resistance, making the device's on-resistance smaller and the switching loss lower, while the device has better limit resistance and is more rugged and durable.

[0190] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0191] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A novel super junction trench MOS power device, characterized in that: include: substrate; A base layer region disposed on the upper surface of the substrate; A first P-type column and a second P-type column that are non-adjacent to each other and are disposed in the base layer region; A P-type layer disposed on the upper surfaces of the first P-type column and the second P-type column; A first groove and a second groove are formed in the first P-type column and the second P-type column respectively through the P-type layer; A dielectric layer disposed on the upper surface of the first trench and the second trench; A first contact hole, a second contact hole and a third contact hole are formed in the P-type layer at one side of the first trench, at one side of the second trench and between the two trenches through the dielectric layer; A metal area is disposed in the first contact hole, the second contact hole, the third contact hole and on the upper surface of the dielectric layer.

2. A novel super junction trench MOS power device according to claim 1, characterized in that: The base layer region includes a drift layer and a buffer layer in order from top to bottom; The thickness of the drift layer is greater than the thickness of the buffer layer.

3. A novel super junction trench MOS power device according to claim 1, characterized in that: The P-type layer includes: a source layer, a first P+ layer, a second P+ layer and a third P+ layer; The source layer is located above the third P+ layer; The first P+ layer, the second P+ layer and the third P+ layer are located at the bottom of the second contact hole, the first contact hole and the third contact hole respectively.

4. A novel super junction trench MOS power device according to claim 1, characterized in that: A first gate oxide layer and a second gate oxide layer are formed on inner surfaces of the first trench and the second trench respectively; The first gate oxide layer and the second gate oxide layer are both filled with polysilicon to form a first gate region and a second gate region respectively; The first alloy layer, the second alloy layer and the third alloy layer are formed on the inner surfaces of the first contact hole, the second contact hole and the third contact hole respectively.

5. A novel super junction trench MOS power device according to claim 1, characterized in that: The metal area includes, from top to bottom, a first metal layer, a second metal layer and a third metal layer; A back metal layer is formed on the lower surface of the substrate as a drain region.

6. A novel method for preparing a super junction trench MOS power device, applied to a novel super junction trench MOS power device as claimed in any one of claims 1 to 5, characterized in that: include: forming a substrate, and forming a base layer region on an upper surface of the substrate; forming a non-adjacent first P-type column and a second P-type column in the base layer region; forming a P-type layer on upper surfaces of the first P-type column and the second P-type column; Passing through the P-type layer, forming a first groove and a second groove in the first P-type column and the second P-type column respectively; forming a dielectric layer on upper surfaces of the first trench and the second trench; Passing through the dielectric layer, a first contact hole, a second contact hole and a third contact hole are formed in the P-type layer on one side of the first trench, on one side of the second trench and between the two trenches, respectively; A metal region is formed in the first contact hole, in the second contact hole, in the third contact hole and on the upper surface of the dielectric layer.

7. A novel method for preparing a super junction trench MOS power device according to claim 6, characterized in that: Forming a grass-roots area, specifically including: forming a buffer layer on the upper surface of the substrate; forming a drift layer on an upper surface of the buffer layer; The thickness of the drift layer is greater than the thickness of the buffer layer; The buffer layer and the drift layer together constitute the base layer region.

8. The method for preparing a novel super junction trench MOS power device according to claim 6, characterized in that: Implanting N-type doping ions at corresponding positions in the P-type layer to form a source layer; Injecting P-type doping ions into corresponding positions in the P-type layer to form a first P+ layer, a second P+ layer and a third P+ layer; The source layer is located above the third P+ layer; The first P+ layer, the second P+ layer and the third P+ layer are in direct contact with the bottoms of the second contact hole, the first contact hole and the third contact hole respectively.

9. A novel method for preparing a super junction trench MOS power device according to claim 6, characterized in that: Generating a first gate oxide layer and a second gate oxide layer on the inner surfaces of the first trench and the second trench respectively; Filling polysilicon inside the first gate oxide layer and the second gate oxide layer to form a first gate region and a second gate region respectively; A first alloy layer, a second alloy layer and a third alloy layer are formed on inner surfaces of the first contact hole, the second contact hole and the third contact hole respectively.

10. The method for preparing a novel super junction trench MOS power device according to claim 9, characterized in that: Forming a metal area, specifically including: forming a first metal layer in the first alloy layer, in the second alloy layer, in the third alloy layer and on the upper surface of the dielectric layer; forming a second metal layer on an upper surface of the first metal layer; forming a third metal layer on the upper surface of the second metal layer; The method also includes: forming a back metal layer on the lower surface of the substrate as a drain region.

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