Capacitor, manufacturing method thereof and memory
By using transition metal nitride as the transition layer and metals such as platinum, ruthenium, iridium as electrode materials in DRAM capacitors, the problems of electrode film continuity and flatness are solved, leakage is reduced, and the performance of the capacitor is improved.
Patent Information
- Application Number
- CN202310868994.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-14
- Publication Date
- 2025-01-14
AI Technical Summary
In dynamic random memory DRAM, with the microscopic trend, the decrease in the thickness of the electrode material leads to a decrease in the continuity of the electrode film and the surface flatness, affecting the device performance. In addition, when using oxygen in the atomic layer deposition method, the silicon substrate will be oxide, affecting the electrode layer. quality.
Transition metal nitride is used as the transition layer material and metals such as platinum, ruthenium, iridium and other metals as electrode materials. The transition layer is formed on the substrate surface by atomic layer deposition method to shorten the nucleation period, improve the surface flatness of the electrode layer, and not Reduce leakage when increasing the device size or dielectric layer thickness.
Significantly reduce the surface roughness of the metal electrode layer, enhance the interface contact of the dielectric layer, reduce leakage, and improve the data storage capability and device performance of the capacitor.
Smart Images
Figure CN119317350A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a capacitor and a manufacturing method thereof, and a memory. Background Art
[0002] In a memory device such as a dynamic random access memory (DRAM), each memory cell may include a transistor and a capacitor, and the capacitor may have a high capacitance. As DRAM is miniaturized, challenges are posed to its capacitance: the requirements of high capacitance and low leakage need to be met at the same time. The electrodes in the capacitor are an important factor affecting the storage capacity of the capacitor. Summary of the invention
[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0004] In one aspect, an exemplary embodiment of the present application provides a capacitor, comprising:
[0005] substrate;
[0006] A transition layer located on the surface of the substrate;
[0007] A lower electrode, which is located on the surface of the transition layer;
[0008] a dielectric layer, which is located on the surface of the lower electrode; and
[0009] an upper electrode, which is located on the surface of the dielectric layer,
[0010] The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
[0011] In an exemplary embodiment, the material for the transition layer includes transition metal nitride.
[0012] In an exemplary embodiment, the transition metal nitride is selected from the group consisting of cobalt nitride, nickel nitride, manganese nitride, titanium nitride, aluminum nitride, and tantalum nitride.
[0013] In an exemplary embodiment, the material for the lower electrode and / or the upper electrode is selected from the group consisting of platinum, ruthenium, and iridium.
[0014] In an exemplary embodiment, the material for the substrate is selected from the group consisting of single crystal silicon, polycrystalline silicon, and n-type doped silicon.
[0015] In an exemplary embodiment, the material for the dielectric layer includes doped strontium titanate, and the doping atoms in the strontium titanate are selected from the group consisting of Si, Hf, Y, Al, Zr, and Gd.
[0016] In an exemplary embodiment, the thickness of the transition layer is in the range of 1 nm to 5 nm, the thickness of the lower electrode and / or the upper electrode is in the range of 1 nm-50 nm, and the thickness of the dielectric layer is in the range of 5 nm-15 nm.
[0017] In another aspect, an exemplary embodiment of the present application provides a capacitor, comprising:
[0018] substrate;
[0019] a transition layer, which is columnar and surrounds the surface of the substrate;
[0020] a lower electrode surrounding the surface of the transition layer;
[0021] a dielectric layer surrounding a surface of the lower electrode; and
[0022] an upper electrode, which surrounds the surface of the dielectric layer,
[0023] The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
[0024] In yet another aspect, an exemplary embodiment of the present application provides a method for manufacturing a capacitor, comprising:
[0025] providing a substrate;
[0026] Depositing a transition layer thin film on the top, sidewalls and bottom of the substrate by atomic layer deposition to form a transition layer covering the surface of the substrate;
[0027] forming a lower electrode covering a surface of the transition layer;
[0028] forming a dielectric layer covering a surface of the lower electrode; and
[0029] forming an upper electrode covering the surface of the dielectric layer,
[0030] The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
[0031] In yet another aspect, an exemplary embodiment of the present application provides a memory, comprising:
[0032] a plurality of transistors; and
[0033] Multiple capacitors, one capacitor connected horizontally or vertically to one transistor;
[0034] Each of said capacitors comprises:
[0035] substrate;
[0036] a transition layer, which is columnar and surrounds the surface of the substrate;
[0037] a lower electrode surrounding the surface of the transition layer;
[0038] a dielectric layer surrounding a surface of the lower electrode; and
[0039] an upper electrode, which surrounds the surface of the dielectric layer,
[0040] The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
[0041] In an exemplary embodiment, the memory may be a dynamic random access memory DRAM.
[0042] On the other hand, an exemplary embodiment of the present application provides an electronic device including the above-mentioned dynamic random access memory.
[0043] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.
[0044] The present application sets a transition layer between the lower electrode layer and the substrate, and the lattice mismatch between the material of the transition layer and the material of the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1. By selecting this specific material, the present application can significantly shorten the nucleation period of the electrode material (such as metal) of the electrode layer on the transition layer material (such as titanium nitride), thereby reducing the surface roughness of the metal electrode layer and improving the surface flatness of the electrode layer, and enhancing the interface contact with the subsequently grown dielectric layer (such as strontium titanate STO), thereby reducing leakage and improving the data storage capacity of the capacitor.
[0045] The present application reduces leakage as much as possible without increasing the horizontal size of the device or the thickness of the dielectric layer of the capacitor, thereby improving the device performance.
[0046] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0048] Figure 1A A longitudinal cross-sectional schematic diagram of a capacitor provided for an exemplary embodiment of the present application;
[0049] Figure 1B A three-dimensional schematic diagram of a capacitor provided for an exemplary embodiment of the present application;
[0050] Figure 1C and Figure 1D A micrograph of a lower electrode layer and a transition layer of a capacitor provided for an exemplary embodiment of the present application;
[0051] Figure 2 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a substrate is provided for an exemplary embodiment of the present application;
[0052] Figure 3 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a transition layer provided in an exemplary embodiment of the present application;
[0053] Figure 4 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a lower electrode provided for an exemplary embodiment of the present application; and
[0054] Figure 5 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a dielectric layer is provided according to an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0055] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.
[0056] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.
[0057] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values shown in the drawings.
[0058] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.
[0059] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0060] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.
[0061] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.
[0062] At present, electrode materials such as metal ruthenium (having a high work function of 4.7eV and a low resistivity) with high work function, low resistivity and lattice compatibility with dielectric materials of high dielectric constant have broad application prospects in the capacitor structure of random dynamic memory. However, under the requirement of continuous miniaturization of devices, the applicant found that when the thickness of the electrode material continues to decrease (such as <10nm), due to the slow film formation speed of the electrode material on the substrate surface, the continuity and surface flatness quality of the electrode film will deteriorate, which will seriously affect the performance of the device. In addition, in order to improve the precise control of the film thickness, if the atomic layer deposition process is adopted, the quality of the electrode film layer will be affected due to the oxidation of the silicon substrate by the reaction gas oxygen used, resulting in a decrease in device performance.
[0063] Therefore, an exemplary embodiment of the present application provides a capacitor, comprising: a substrate; a transition layer located on the surface of the substrate; a lower electrode located on the surface of the transition layer; a dielectric layer located on the surface of the lower electrode; and an upper electrode located on the surface of the dielectric layer; the lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond level is greater than or equal to 1.
[0064] In an exemplary embodiment, the material for the transition layer includes transition metal nitride.
[0065] In an exemplary embodiment, the transition metal nitride is selected from the group consisting of cobalt nitride, nickel nitride, manganese nitride, titanium nitride, aluminum nitride, and tantalum nitride.
[0066] In an exemplary embodiment, the lower electrode and / or the upper electrode includes at least one metal of platinum, ruthenium, and iridium.
[0067] Figure 1A A schematic longitudinal cross-sectional view of a capacitor provided for an exemplary embodiment of the present application. Figure 1A As shown, the capacitor may include a substrate 10; a transition layer 20 located on the surface of the substrate 10; a lower electrode 30 located on the surface of the transition layer 20; a dielectric layer 40 located on the surface of the lower electrode 30; and an upper electrode 50 located on the surface of the dielectric layer 40.
[0068] The present application specifically selects matching materials for the transition layer and the lower electrode, that is, the lattice mismatch between the material for the transition layer 20 and the material for the lower electrode 30 is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
[0069] In an exemplary embodiment, the material for the transition layer 20 may include transition metal nitrides, including but not limited to cobalt nitride, nickel nitride, manganese nitride, titanium nitride, aluminum nitride, and tantalum nitride.
[0070] In an exemplary embodiment, the lower electrode 30 and / or the upper electrode 50 may include at least one metal of platinum, ruthenium, and iridium.
[0071] The material for the lower electrode 30 and the material for the upper electrode 50 may be the same or different.
[0072] In an exemplary embodiment, the lower electrode 30 may have a three-dimensional structure such as a cylindrical shape (eg, a hollow cylindrical shape) or a columnar, cup-shaped shape. The capacitance of the capacitor may be determined by the surface area of the lower electrode 30, and the lower electrode 30 may have various modified structures for increasing the capacitance.
[0073] In an exemplary embodiment, the dielectric layer 40 may include doped strontium titanate, wherein the doping atoms in the strontium titanate are selected from the group consisting of Si, Hf, Y, Al, Zr, and Gd, and the thickness of the dielectric layer may be in the range of 5-15 nm.
[0074] In an exemplary embodiment, the thickness of the transition layer 20 may be in the range of 1 nm to 5 nm. In an exemplary embodiment, the thickness of the lower electrode 30 and / or the upper electrode 50 may be in the range of 1-50 nm. The present application may adjust the thickness ratio of the lower electrode, such as a metal electrode, to the transition layer according to the capacitance requirements. For example, the thickness of the transition layer may be 10%-50% of the thickness of the lower electrode, such as 10%.
[0075] Figure 1B A three-dimensional schematic diagram of a capacitor provided according to an exemplary embodiment of the present application. Figure 1B A capacitor array consisting of six capacitors 1 is shown, wherein one capacitor 1 is electrically connected to a transistor in the horizontal direction; in the horizontal direction, two capacitors 1 are arranged adjacently and spaced in parallel; in the vertical direction, three capacitors 1 are stacked vertically; and each capacitor 1 may be in the shape of a square column. However, in other exemplary embodiments, for a capacitor array consisting of a plurality of capacitors, a capacitor may be electrically connected to a transistor in the vertical direction; and in the horizontal direction, a plurality of capacitors may be arranged adjacently and spaced in parallel.
[0076] Continue to refer Figure 1A Each capacitor 1 may include a substrate 10; a transition layer 20, which is columnar and surrounds the surface of the substrate 10; a lower electrode 30, which surrounds the surface of the transition layer 20; a dielectric layer 40, which surrounds the surface of the lower electrode 30; and an upper electrode 50, which surrounds the surface of the dielectric layer 40.
[0077] Here, “surrounding” can be understood as the transition layer 20 completely surrounding the substrate 10 and covering and wrapping the top, sidewalls and bottom of the substrate 10 .
[0078] In an exemplary embodiment, the transition layer 20 may be in a columnar shape and completely surround the entire surface of the substrate 10 .
[0079] The capacitor structure of the present application is particularly suitable for a capacitor array structure in which a plurality of columnar capacitors are vertically stacked in a longitudinal direction.
[0080] In the present application, the term "columnar" includes but is not limited to shapes such as cylindrical, square column, strip, cuboid, cube, etc.
[0081] Figure 1C and Figure 1DThe micrographs show that there is no obvious interface layer between the ruthenium lower electrode layer and the TiN transition layer (on the contrary, Ru is difficult to grow on the Si and SiO2 surfaces, and the nucleation period is long, while the nucleation period on the TiN surface is almost 0), and the surface roughness is below 3nm.
[0082] The present application introduces a specific transition layer (such as transition metal nitride) between the electrode layer and the substrate, which can significantly shorten the nucleation period of the metal electrode, reduce the surface roughness of the metal electrode layer, improve the surface flatness of the electrode layer, and enhance the interface contact with the subsequently grown dielectric layer (such as STO), thereby reducing leakage.
[0083] The manufacturing process of the capacitor of the present application is described below by taking a columnar capacitor as an example; however, the capacitor of the present application is not limited to the columnar shape.
[0084] In an exemplary embodiment, the manufacturing process of a capacitor may include the following steps:
[0085] S100: Provide a substrate 10, such as Figure 2 As shown. Among them, Figure 2 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a substrate is provided for an exemplary embodiment of the present application;
[0086] In an exemplary implementation method, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. In an exemplary implementation method, the substrate 10 may be polysilicon, n-type doped silicon, or the like.
[0087] In an exemplary implementation, the substrate 10 may include a semiconductor element (not shown) and / or a metal wire or the like that may be electrically connected to the semiconductor element.
[0088] In an exemplary implementation method, the substrate 10 may be in a shape of a column, a bar, a cuboid, etc., and thus may have a top, a sidewall, and a bottom.
[0089] S200: Depositing a transition layer thin film on the top, sidewalls and bottom of the substrate 10 by atomic layer deposition to form a transition layer 20 covering the substrate 10, that is, the transition layer 20 completely surrounds and wraps the substrate 10, such as Figure 3 As shown. Among them, Figure 3 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a transition layer is provided for an exemplary embodiment of the present application.
[0090] In an exemplary embodiment, the transition layer 20 may be a nitride of a transition metal, including but not limited to cobalt nitride, nickel nitride, manganese nitride, titanium nitride, aluminum nitride, and tantalum nitride, all of which are conductive metal compounds. In an exemplary embodiment, the thickness of the transition layer 20 may be in the range of 1-5 nm.
[0091] In the present application, for a multi-layer stacked capacitor device structure, a transition layer material can be grown on the surface of a silicon substrate by an atomic layer deposition (ALD) process, so that a transition layer film can be deposited on the top, sidewalls, and bottom of the columnar substrate. In contrast, although a conventional chemical vapor deposition (CVD) process can deposit a transition layer film on the top and sidewalls of a silicon substrate, it is difficult to fill a transition layer film at the bottom of the silicon substrate.
[0092] For the ALD process, when using the reactive gas oxygen, since the additional transition layer provided in the present application can completely cover the silicon substrate layer, it is possible to completely avoid oxidation of the silicon substrate by hot oxygen, thereby avoiding affecting the growth quality of the subsequent electrode layer, reducing the contact resistance, and improving the device performance of the capacitor.
[0093] S300: growing a lower electrode layer. The specific steps may include using a thermal atomic layer deposition or a plasma atomic layer deposition process to form a lower electrode layer 30 covering the transition layer 20, such as Figure 4 As shown. Among them, Figure 4 A schematic longitudinal cross-sectional view of a method for manufacturing a capacitor after forming a lower electrode according to an exemplary embodiment of the present application is provided.
[0094] In an exemplary embodiment, the lower electrode layer 30 may use at least one metal of platinum, ruthenium, and iridium.
[0095] In an exemplary embodiment, the precursor for forming the electrode layer may be a ruthenium compound with a valence of 0, +2, or +4, including but not limited to Ru(DER), EBECHRu, and RuO4.
[0096] In an exemplary embodiment, the thickness of the lower electrode layer 30 may be in the range of 1 nm to 50 nm.
[0097] S400: growing a dielectric layer. The specific steps may include forming a dielectric layer 40 covering the lower electrode layer 30 by chemical vapor deposition (CVD), such as metal organic CVD (MOCVD) or ALD or magnetron sputtering. Figure 5 As shown. Among them, Figure 5 A longitudinal cross-sectional schematic diagram of a method for manufacturing a capacitor after forming a dielectric layer is provided according to an exemplary embodiment of the present application.
[0098] The dielectric layer 40 may be made of doped strontium titanate SrTiO3, referred to as STO. The doping atoms in the doped strontium titanate film may include but are not limited to at least one of Si, Hf, Y, Al, Zr, and Gd.
[0099] In an exemplary implementation method, the dielectric layer 40 may be made of at least one material selected from the group consisting of BSTO, STO, SBT, and any other high dielectric constant material.
[0100] In an exemplary implementation, the thickness of dielectric layer 40 may be in the range of 5-15 nm.
[0101] S500: growing an upper electrode. Specifically, the steps may include forming an upper electrode layer 50 covering the dielectric layer 40 by a sputtering process or an atomic layer deposition process.
[0102] In an exemplary implementation, the upper electrode layer 50 may be made of at least one metal selected from the group consisting of platinum, ruthenium, and iridium.
[0103] In an exemplary implementation, the lower electrode layer 30 and the upper electrode layer 50 may be made of different metal materials.
[0104] After the capacitor of the present application is formed, it can be operably coupled to a memory cell of a DRAM memory device. The memory cell can be a DRAM memory cell, which can include a source region, a drain region and a channel region and can read and / or write the charge stored in the DRAM capacitor.
[0105] In an exemplary implementation, the capacitor is typically electrically coupled to the source of the transistor cell of the memory.
[0106] The exemplary embodiment of the present application also provides a method for manufacturing a capacitor, comprising the following steps:
[0107] S1100: providing a substrate;
[0108] S1200: depositing a transition layer thin film on the top, sidewalls and bottom of the substrate by atomic layer deposition to form a transition layer covering the surface of the substrate;
[0109] S1300: forming a lower electrode covering the surface of the transition layer;
[0110] S1400: forming a dielectric layer covering the surface of the lower electrode; and
[0111] S1500: forming an upper electrode covering the surface of the dielectric layer,
[0112] The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
[0113] An exemplary embodiment of the present application provides a memory, comprising a plurality of transistors; and a plurality of capacitors, one capacitor being horizontally connected or vertically connected to one transistor; wherein each of the capacitors comprises: a substrate; a transition layer, which is columnar and surrounds the surface of the substrate; a lower electrode, which surrounds the surface of the transition layer; a dielectric layer, which surrounds the surface of the lower electrode; and an upper electrode, which surrounds the surface of the dielectric layer; the lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond level is greater than or equal to 1.
[0114] An exemplary embodiment of the present application further provides an electronic device, comprising the memory provided by the exemplary embodiment of the present application as above.
[0115] In an exemplary embodiment, the memory may be DRAM memory.
[0116] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.
[0117] Although the embodiments disclosed in this application are as above, the contents are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.
Claims
1. A capacitor, characterized in that: include: substrate; a transition layer located on the surface of the substrate; A lower electrode, which is located on the surface of the transition layer; a dielectric layer, which is located on the surface of the lower electrode; as well as an upper electrode, which is located on the surface of the dielectric layer; The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
2. The capacitor according to claim 1, wherein: Materials for the transition layer include transition metal nitrides.
3. The capacitor according to claim 2, characterized in that The transition metal nitride is selected from the group consisting of cobalt nitride, nickel nitride, manganese nitride, titanium nitride, aluminum nitride and tantalum nitride.
4. The capacitor according to claim 1, wherein The material for the lower electrode and / or the upper electrode is selected from the group consisting of platinum, ruthenium and iridium.
5. The capacitor according to claim 1, wherein: The material for the substrate is selected from the group consisting of single crystal silicon, polycrystalline silicon, and n-type doped silicon.
6. The capacitor according to claim 1, wherein: The material used for the dielectric layer includes doped strontium titanate, and the doping atoms in the strontium titanate are selected from the group consisting of Si, Hf, Y, Al, Zr, and Gd.
7. The capacitor according to claim 1, wherein: The thickness of the transition layer is in the range of 1 nm to 5 nm, the thickness of the lower electrode and / or the upper electrode is in the range of 1 nm-50 nm, and the thickness of the dielectric layer is in the range of 5 nm-15 nm.
8. A capacitor, characterized in that: include: substrate; a transition layer, which is columnar and surrounds the surface of the substrate; a lower electrode surrounding the surface of the transition layer; a dielectric layer surrounding a surface of the lower electrode; and an upper electrode, which surrounds the surface of the dielectric layer, The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
9. A method for manufacturing a capacitor, characterized in that: include: providing a substrate; Depositing a transition layer thin film on the top, sidewalls and bottom of the substrate by atomic layer deposition to form a transition layer covering the surface of the substrate; forming a lower electrode covering a surface of the transition layer; forming a dielectric layer covering the surface of the lower electrode; as well as forming an upper electrode covering the surface of the dielectric layer, The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.
10. A memory, characterized in that: include: Multiple transistors; as well as Multiple capacitors, one capacitor connected horizontally or vertically to one transistor; Each of said capacitors comprises: substrate; a transition layer, which is columnar and surrounds the surface of the substrate; a lower electrode surrounding the surface of the transition layer; a dielectric layer surrounding a surface of the lower electrode; and an upper electrode, which surrounds the surface of the dielectric layer, The lattice mismatch between the material used for the transition layer and the material used for the lower electrode is less than or equal to 5% and the Mayer bond order is greater than or equal to 1.