Topological optimization circuit and method of power electronic conversion circuit based on potential circuit analysis

Abstract

The invention provides a topological optimization circuit and method for a power electronic conversion circuit based on potential circuit analysis, and the output end of a power circuit is connected with the input end of a main switch parasitic parameter circuit, the first input end of an auxiliary switch parasitic parameter circuit, and the first input end of a buffer network circuit. The first output end of the main switch parasitic parameter circuit is connected with the input end of the driving parasitic parameter circuit, the first output end of the driving parasitic parameter circuit is connected with the second input end of the auxiliary switch parasitic parameter circuit, and the first output end of the auxiliary switch parasitic parameter circuit is connected with the second input end of the buffer network circuit. The output end of the buffer network circuit, the second output end of the auxiliary switch parasitic parameter circuit, the second output end of the driving parasitic parameter circuit and the second output end of the main switch parasitic parameter circuit are jointly connected with the input end of the power supply circuit. According to the method, the influence of parasitic parameters on the circuit is considered, and the circuit topology structure and the circuit topology screening operation are simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a topology optimization circuit and method for a power electronic conversion circuit based on potential circuit analysis. Background Art

[0002] Power electronic converters are indispensable key devices in modern power systems, and the construction and optimization of their topological structures is a complex and critical process. However, for a long time, the creation process of many new power electronic converter topologies has mainly relied on the inspiration and experience of designers, and there is no strict and followable logic and model, which makes it difficult to innovate and optimize the power electronic converter topology. Therefore, the research on the topological optimization circuit of power electronic converters is of great significance.

[0003] On the basis of comprehensive evaluation and comparison of current power electronic conversion circuit technology, the existing disclosed power electronic conversion circuit based on potential circuit analysis mainly has the following problems: First, with the development of high frequency of power electronic conversion circuit, parasitic parameters have a significant impact on the working performance of power electronic conversion circuit, but the existing power electronic conversion circuit is not designed close to the actual situation, and no parasitic parameter model is established to consider the influence of all parasitic parameters of the circuit; Second, the topological structure of power electronic converter is diverse, and each topology has its own characteristics and scope of application. The main method of realizing the construction and optimization of power electronic conversion circuit topology in the existing technology is usually to refer to and learn from the existing power electronic circuit topology, and make modifications and adjustments on this basis, including combining power circuits with the same or different functions. Sub-circuit modules are cascaded and combined to construct a new or optimized topology structure to achieve performance optimization. This method can improve the flexibility and scalability of designing power electronic circuit topology circuits, and facilitate the realization of complex functions and system integration. However, the circuit topology is usually complex, the functions are redundant, and it mainly relies on the experience and inspiration of the designer, and is greatly affected by subjective factors; thirdly, the main methods for realizing the topology construction and optimization of power electronic conversion circuits in the existing technology also include using random topology generation, heuristic topology generation, knowledge-based topology generation and other algorithms to automatically generate a large number of potential topological structures through computer programs, and then screen out topologies that meet certain conditions and requirements for further analysis and evaluation, but the number of generated topologies is large, and the process of screening one by one is complicated, that is, the circuit topology screening is cumbersome. Summary of the invention

[0004] In order to solve the problems in the above-mentioned prior art that the circuit does not consider the influence of parasitic parameters, the circuit topology structure is complex, and the circuit topology screening is cumbersome, the present invention proposes a topology optimization circuit and method for a power electronic conversion circuit based on potential circuit analysis, which takes into account the influence of parasitic parameters on the circuit and simplifies the circuit topology structure and circuit topology screening operations.

[0005] In order to achieve the above technical effects, the technical solution of the present invention is as follows: A topology optimization circuit for a power electronic conversion circuit based on potential circuit analysis, comprising: a power supply circuit, a main switch parasitic parameter circuit, a drive parasitic parameter circuit, an auxiliary switch parasitic parameter circuit and a buffer network circuit; The output end of the power supply circuit is respectively connected to the input end of the main switch parasitic parameter circuit, the first input end of the auxiliary switch parasitic parameter circuit and the first input end of the buffer network circuit, the first output end of the main switch parasitic parameter circuit is connected to the input end of the driving parasitic parameter circuit, the first output end of the driving parasitic parameter circuit is connected to the second input end of the auxiliary switch parasitic parameter circuit, the first output end of the auxiliary switch parasitic parameter circuit is connected to the second input end of the buffer network circuit, and the output end of the buffer network circuit, the second output end of the auxiliary switch parasitic parameter circuit, the second output end of the driving parasitic parameter circuit and the second output end of the main switch parasitic parameter circuit are commonly connected to the input end of the power supply circuit.

[0006] Preferably, the main switch parasitic parameter circuit includes a main switch first parasitic inductance circuit, a main switch S1, and a main switch second parasitic inductance circuit; the output end of the power supply circuit is connected to the input end of the main switch first parasitic inductance circuit; the output end of the main switch first parasitic inductance circuit is connected to the drain of the main switch S1; the gate of the main switch S1 is connected to the input end of the driving parasitic parameter circuit; the source of the main switch S1 is connected to the input end of the main switch second parasitic inductance circuit; and the output end of the main switch second parasitic inductance circuit is connected to the input end of the power supply circuit.

[0007] Preferably, the first parasitic inductance circuit of the main switch includes first parasitic inductances connected in series L d_ex1 and the second parasitic inductance L d_in1 The second parasitic inductance circuit of the main switch includes third parasitic inductances connected in series with each other. L s_in1 and the fourth parasitic inductance L d_ex1 , the output end of the power supply circuit is connected to the first parasitic inductor L d_ex1 One end of the first parasitic inductance L d_ex1 The other end of the second parasitic inductor is connected L d_in1 One end of the second parasitic inductance L d_in1 The other end is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input end of the driving parasitic parameter circuit, and the source of the main switch S1 is connected to the third parasitic inductor Ls_in1 One end of the third parasitic inductance L s_in1 The other end of the fourth parasitic inductor is connected L d_ex1 One end of the fourth parasitic inductance L d_ex1 The other end is connected to the input end of the power supply circuit.

[0008] Preferably, the driving parasitic parameter circuit includes a first parasitic resistor R g1 , drive circuit and second parasitic resistance R g2 , the gate of the main switch S1 is connected to the first parasitic resistor R g1 One end of the first parasitic resistance R g1 The other end is connected to the input end of the driving circuit, and the first output end of the driving circuit is connected to the second parasitic resistor R g2 One end of the second parasitic resistance R g2 The other end of is connected to the second input end of the auxiliary switch parasitic parameter circuit, and the second output end of the driving circuit is connected to the input end of the power supply circuit.

[0009] Preferably, the auxiliary switch parasitic parameter circuit includes an auxiliary switch first parasitic inductance circuit, an auxiliary switch S2, and an auxiliary switch second parasitic inductance circuit. The output end of the driving parasitic parameter circuit is connected to the gate of the auxiliary switch S2, the drain of the auxiliary switch S2 is connected to the first input end of the auxiliary switch first parasitic inductance circuit, the second input end of the auxiliary switch first parasitic inductance circuit is connected to the output end of the power supply circuit, the output end of the first parasitic inductance circuit is connected to the input end of the buffer network circuit, and the output end of the buffer network circuit is connected to the input end of the power supply circuit.

[0010] Preferably, the auxiliary switch parasitic capacitance circuit includes a fifth parasitic inductor connected in series L r , Sixth parasitic inductance L d_ex2 and seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductance circuit includes a ninth parasitic inductance connected in series L s_in2 and the tenth parasitic inductance L s_ex2 The output end of the driving parasitic parameter circuit is connected to the gate of the auxiliary switch S2, and the drain of the auxiliary switch S2 is connected to the seventh parasitic inductor L d_in2 One end of the seventh parasitic inductance Ld_in2 The other end of the sixth parasitic inductor is connected L d_ex2 One end of the sixth parasitic inductance L d_ex2 The other end is connected to the input end of the buffer network circuit and the fifth parasitic inductor L r One end of the fifth parasitic inductance L r The other end is connected to the output end of the power supply circuit, and the source of the auxiliary switch S2 is connected to the ninth parasitic inductor L s_in2 One end of the ninth parasitic inductance L s_in2 The other end of the tenth parasitic inductor is connected L s_ex2 One end of the tenth parasitic inductance L s_ex2 The other end is connected to the input end of the power supply circuit.

[0011] Preferably, the buffer network circuit includes a first buffer parameter circuit, a second buffer parameter circuit, a feedback capacitor C o and snubber resistor R o , the first buffer parameter circuit includes a first buffer capacitor connected in parallel C D1 and the first diode D 1. The second buffer parameter circuit includes a second buffer capacitor connected in parallel C D2 and the second diode D 2. The first buffer capacitor C D1 One end and the first diode D 1 are connected to the output terminal of the power supply circuit, and the first buffer capacitor C D1 The other end of the first diode is connected D 1, the negative terminal of the second buffer capacitor C D2 One end of the second diode D 2 are connected to the fifth parasitic inductor L r and the sixth parasitic inductance L d_ex2 One end of the second buffer capacitor C D2 The other end of the second diode is connected D 2, the cathode of the first diode D The cathode of 1 and the second diode D 2 are connected to the negative poles of the feedback capacitorsC o and snubber resistor R o One end of the feedback capacitor C o and snubber resistor R o The other ends are connected together to the input end of the power supply circuit.

[0012] Preferably, the buffer network circuit includes a first buffer parameter circuit, a second buffer parameter circuit, a third diode D 3. The third buffer capacitor C 3. Feedback capacitor C o and snubber resistor R o , the first buffer parameter circuit includes a first buffer capacitor connected in parallel C D1 and the first diode D 1. The second buffer parameter circuit includes a second buffer capacitor connected in parallel C D2 and the second diode D 2. The first buffer capacitor C D1 One end of the first diode D 1 and the positive terminal of the third buffer capacitor C 3 are connected to the output end of the power supply circuit, and the first buffer capacitor C D1 The other end of the first diode is connected D 1, the negative terminal of the second buffer capacitor C D2 One end of the second diode D 2 and the positive terminal of the third buffer capacitor C The other end of 3 is connected to the third diode D 3, the negative terminal of the third diode D The positive terminals of 3 are connected to the fifth parasitic inductor L r and the sixth parasitic inductance L d_ex2 One end of the second buffer capacitor C D2 The other end of the second diode is connected D 2, the cathode of the first diode D The cathode of 1 and the second diode D 2 are connected to the negative poles of the feedback capacitors C o and snubber resistor R o One end of the feedback capacitor Co and snubber resistor R o The other ends are connected together to the input end of the power supply circuit.

[0013] Preferably, the power supply circuit comprises a power supply U I , resistor element R L and inductor components L , the power supply U I , resistor element R L and inductor components L Connect in series.

[0014] The present invention also proposes a topology optimization method for a power electronic conversion circuit based on potential circuit analysis, comprising the following steps: S1. Establish a topology optimization circuit for power electronic conversion circuit based on potential circuit analysis; S2. performing modal analysis on the topology optimization circuit to obtain modal analysis results; S3, performing circuit characteristic analysis on the topology optimization circuit, and outputting the influence of potential working modes on the topology optimization circuit; S4, analyzing the potential working modes that have an impact on the topology optimization circuit, obtaining the conditions under which the potential working modes that have an impact on the topology optimization circuit appear, and using the appearing conditions as the excitation conditions of the potential working modes; S5. If the impact of the potential working mode on the topology optimization circuit is positive, the excitation condition is enabled through parameter design and topology improvement; if the impact of the potential working mode on the topology optimization circuit is negative, the satisfaction of the excitation condition is suppressed through parameter design and topology improvement to obtain the topology optimization circuit, and the topology optimization ends.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The present invention proposes a topology optimization circuit and method for a power electronic conversion circuit based on potential circuit analysis. Firstly, by integrating the main switch parasitic parameter circuit, the driving parasitic parameter circuit, the auxiliary switch parasitic parameter circuit and the buffer network circuit, a topology optimization circuit is formed as a parasitic parameter model of the power electronic conversion circuit, which effectively reduces the influence of the parasitic parameters on the topology optimization circuit and provides an analysis basis for topology optimization. Secondly, the power supply circuit provides a working power supply for the topology optimization circuit. The driving parasitic parameter circuit is intended to work by driving the main switch parasitic parameter circuit and the auxiliary switch parasitic parameter circuit. The main switch parasitic parameter circuit is used to simulate the influence of the parasitic parameters of the main switch on the circuit. The auxiliary switch parasitic parameter circuit is used to simulate the influence of the parasitic parameters of the main switch on the circuit. The parasitic parameter circuit receives the signal from the driving parasitic parameter circuit and simulates the influence of the parasitic parameters of the auxiliary switch on the signal. Then the buffer network circuit receives the signal from the auxiliary switch parasitic parameter circuit to reduce the voltage and current stress in the auxiliary switch process. The output of the buffer network circuit is connected to the power input terminal together with the outputs of the main switch parasitic parameter circuit, the driving parasitic parameter circuit, and the auxiliary switch parasitic parameter circuit to form a closed-loop system, which effectively simplifies the complex circuit topology structure and makes the circuit topology screening simple. Furthermore, the topology optimization circuit of the present invention performs potential circuit analysis by considering the influence of parasitic parameters, providing a theoretical basis for the topology research and application of power electronic conversion circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural block diagram showing a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention; Figure 2 A flowchart showing the principle of potential circuit analysis proposed in an embodiment of the present invention; Figure 3 Another structural block diagram showing a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention; Figure 4 A topology optimization circuit connection diagram of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention is shown; Figure 5 A working waveform diagram showing a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention; Figure 6 A switching process diagram showing a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention; Figure 7 Another connection diagram showing a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention; Figure 8A topology optimization diagram showing a topology optimization circuit proposed in an embodiment of the present invention; Fig. 9 Another working waveform diagram showing a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention; Fig.10 Another switching process diagram of a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention is shown.

[0017] Fig.11 A flowchart showing a topology optimization method for a power electronic conversion circuit based on potential circuit analysis proposed in an embodiment of the present invention.

[0018] 1. Power supply circuit; 2. Main switch parasitic parameter circuit; 21. Main switch first parasitic inductance circuit; 22. Main switch second parasitic inductance circuit; 3. Driving parasitic parameter circuit; 4. Auxiliary switch parasitic parameter circuit; 41. Auxiliary switch first parasitic inductance circuit; 42. Auxiliary switch second parasitic inductance circuit; 5. Buffer network circuit; 51. First buffer parameter circuit; 52. First buffer parameter circuit. DETAILED DESCRIPTION

[0019] The drawings are for illustrative purposes only and should not be construed as limiting the present patent; It is understandable to those skilled in the art that some well-known contents may be omitted in the drawings; The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0020] Example 1 like Figure 1 As shown, this embodiment proposes a topology optimization circuit of a power electronic conversion circuit based on potential circuit analysis, including: a power supply circuit 1, a main switch parasitic parameter circuit 2, a driving parasitic parameter circuit 3, an auxiliary switch parasitic parameter circuit 4 and a buffer network circuit 5; The output end of the power supply circuit 1 is respectively connected to the input end of the main switch parasitic parameter circuit 2, the first input end of the auxiliary switch parasitic parameter circuit 4 and the first input end of the buffer network circuit 5, the first output end of the main switch parasitic parameter circuit 2 is connected to the input end of the driving parasitic parameter circuit 3, the first output end of the driving parasitic parameter circuit 3 is connected to the second input end of the auxiliary switch parasitic parameter circuit 4, the first output end of the auxiliary switch parasitic parameter circuit 4 is connected to the second input end of the buffer network circuit 5, and the output end of the buffer network circuit 5, the second output end of the auxiliary switch parasitic parameter circuit 4, the second output end of the driving parasitic parameter circuit 3 and the second output end of the main switch parasitic parameter circuit 2 are commonly connected to the input end of the power supply circuit 1.

[0021] This embodiment proposes a topology optimization circuit for a power electronic conversion circuit based on potential circuit analysis. First, by integrating the main switch parasitic parameter circuit, the driving parasitic parameter circuit, the auxiliary switch parasitic parameter circuit and the buffer network circuit, a topology optimization circuit is formed as a parasitic parameter model of the power electronic conversion circuit, which effectively reduces the influence of the parasitic parameters on the topology optimization circuit and provides an analysis basis for topology optimization. Secondly, the power supply circuit provides working power for the topology optimization circuit. The driving parasitic parameter circuit is intended to work by driving the main switch parasitic parameter circuit and the auxiliary switch parasitic parameter circuit. The main switch parasitic parameter circuit is used to simulate the influence of the parasitic parameters of the main switch on the circuit. The auxiliary switch parasitic parameter circuit receives the signal from the driving parasitic parameter circuit and simulates the parasitic parameters of the auxiliary switch. The influence of the parasitic parameters on the signal is taken into consideration, and then the buffer network circuit receives the signal from the auxiliary switch parasitic parameter circuit to reduce the voltage and current stress in the auxiliary switch process. The output of the buffer network circuit is connected to the power input terminal together with the outputs of the main switch parasitic parameter circuit, the driving parasitic parameter circuit, and the auxiliary switch parasitic parameter circuit to form a closed-loop system, which effectively simplifies the complexity of the circuit topology structure and makes the circuit topology screening simple. Furthermore, the topology optimization circuit of the present invention performs potential circuit analysis by considering the influence of parasitic parameters, which provides a theoretical basis for the topology research and application of power electronic conversion circuits. The temperature compensated RC oscillator circuit of the present invention is set on an application chip, which is suitable for various power electronic conversion systems with requirements for high efficiency, low loss and fast dynamic response.

[0022] See also Figure 2 , wherein the potential circuit analysis principle process of the topology optimization circuit proposed in this embodiment is as follows: Firstly, a topology optimization circuit as a parasitic parameter model of a power electronic conversion circuit is established by integrating the main switch parasitic parameter circuit, the driving parasitic parameter circuit, the auxiliary switch parasitic parameter circuit and the buffer network circuit; secondly, a modal analysis is performed on the topology optimization circuit as a parasitic parameter model of a power electronic conversion circuit to obtain a modal analysis result; the modal analysis result is compared with the normal working modal threshold in the traditional circuit analysis result to identify the modal analysis result different from the normal working modal threshold, and the identified modal analysis result is defined as a potential working mode; then, the output characteristics, switching characteristics, efficiency, etc. of the topology optimization circuit are analyzed. The characteristics are analyzed to obtain the influence of the potential working mode on the topology optimization circuit; then, the potential working mode that affects the topology optimization circuit is used for analysis to obtain the conditions for the occurrence of the potential working mode that affects the topology optimization circuit, and the conditions for the occurrence are used as the excitation conditions of the potential working mode; finally, if the influence of the potential working mode on the topology optimization circuit is positive, the excitation conditions are enabled through parameter design and topology improvement; if the influence of the potential working mode on the topology optimization circuit is negative, the satisfaction of the excitation conditions is suppressed through parameter design and topology improvement, the topology optimization circuit is obtained, and the topology optimization is ended.

[0023] Example 2 See also Figure 3 and Figure 4 The power supply circuit 1 includes a power supply U I , resistor element R L and inductor components L , the power supply U I , resistor element R L and inductor components L are connected in series, the power U I The output terminal of the resistor element is connected R L The input terminal, the resistor element R L The output end of the inductor is connected to L The input terminal of the inductor L The output end of is respectively connected to the input end of the main switch parasitic parameter circuit 2, the first input end of the auxiliary switch parasitic parameter circuit 4 and the first input end of the buffer network circuit 5, the output end of the buffer network circuit 5, the second output end of the auxiliary switch parasitic parameter circuit 4, the second output end of the driving parasitic parameter circuit 3 and the second output end of the main switch parasitic parameter circuit 2 are commonly connected to the input end of the power supply circuit 1; using the resistor element R L and inductor components L Power SupplyU I Preprocessing the output helps to smooth power supply fluctuations and limit startup current shocks. It also enhances the stability and reliability of the overall circuit through interaction with the main switch parasitic parameter circuit, the auxiliary switch parasitic parameter circuit 4 and the buffer network circuit 5, providing a more stable and controllable power supply environment for the entire topology optimization circuit.

[0024] The main switch parasitic parameter circuit 2 includes a main switch first parasitic inductance circuit 21, a main switch S1, and a main switch second parasitic inductance circuit 22. The output end of the power supply circuit 1 is connected to the input end of the main switch first parasitic inductance circuit 21, the output end of the main switch first parasitic inductance circuit 21 is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input end of the driving parasitic parameter circuit 3, the source of the main switch S1 is connected to the input end of the main switch second parasitic inductance circuit 22, and the output end of the main switch second parasitic inductance circuit 22 is connected to the input end of the power supply circuit 1.

[0025] The first parasitic inductance circuit 21 of the main switch includes first parasitic inductances connected in series. L d_ex1 and the second parasitic inductance L d_in1 The second parasitic inductance circuit 22 of the main switch includes third parasitic inductances connected in series with each other. L s_in1 and the fourth parasitic inductance L d_ex1 The output end of the power supply circuit 1 is connected to the first parasitic inductor L d_ex1 One end of the first parasitic inductance L d_ex1 The other end of the second parasitic inductor is connected L d_in1 One end of the second parasitic inductance L d_in1 The other end of is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input end of the parasitic parameter driving circuit 3, and the source of the main switch S1 is connected to the third parasitic inductor L s_in1 One end of the third parasitic inductance L s_in1 The other end of the fourth parasitic inductor is connected L d_ex1 One end of the fourth parasitic inductance L d_ex1 The other end of is connected to the input end of the power supply circuit 1. The main switch S1 is provided with a first inter-electrode parasitic capacitor C ds1 , the second inter-electrode parasitic capacitance C gd1 And the third inter-electrode parasitic capacitance C gs1 , the second inter-electrode parasitic capacitance Cgd1 And the third inter-electrode parasitic capacitance C gs1 After being connected in series with the first inter-electrode parasitic capacitance C ds1 In parallel; here, by accurately modeling the main switch parasitic parameter circuit of the main switch S1, including the first parasitic inductance L d_ex1 , the second parasitic inductance L d_in1 , the third parasitic inductance L s_in1 and the fourth parasitic inductance L d_ex1 And the first inter-electrode parasitic capacitance C inside the main switch S1 ds1 , the second inter-electrode parasitic capacitance C gd1 And the third inter-electrode parasitic capacitance C gs1 , realizing a comprehensive consideration of the parasitic parameters of the main switch in the power electronic conversion circuit. The establishment of the main switch parasitic parameter circuit not only helps to accurately predict and analyze the voltage and current waveforms and their dynamic behaviors in the circuit, but also effectively evaluates the actual impact of the main switch S1 parasitic parameters on the overall circuit performance (such as switching speed, energy loss and stability). By optimizing the above parasitic parameters in the main switch parasitic parameter circuit, the overall efficiency of the main switch S1 circuit can be significantly improved, unnecessary energy loss can be reduced, and the main switch S1 circuit can be ensured to operate stably under various working conditions, thereby meeting the design requirements of high-performance power electronic conversion systems.

[0026] The driving parasitic parameter circuit 3 includes a first parasitic resistor R g1 , drive circuit and second parasitic resistance R g2 , the gate of the main switch S1 is connected to the first parasitic resistor R g1 One end of the first parasitic resistance R g1 The other end is connected to the input end of the driving circuit, and the first output end of the driving circuit is connected to the second parasitic resistor R g2 One end of the second parasitic resistance R g2 The other end of the driving circuit is connected to the second input end of the auxiliary switch parasitic parameter circuit 4, and the second output end of the driving circuit is connected to the input end of the power supply circuit 1; here, the driving parasitic parameter circuit 3 receives the signal from the main switch parasitic parameter circuit 2, amplifies or converts the signal through the internal driving circuit, and then transmits the processed signal to the auxiliary switch parasitic parameter circuit 4 to control the switching state of the auxiliary switch. At the same time, the driving parasitic parameter circuit 3 also forms a loop with the power supply circuit 1 through its second output end to ensure the driving energy supply of the circuit and the stability of signal transmission; the auxiliary switch S2 is provided with a fourth inter-electrode parasitic capacitor Cds2 、The fifth inter-electrode parasitic capacitance C gd2 and the sixth inter-electrode parasitic capacitance C gs2 , the fifth inter-electrode parasitic capacitance C gd2 and the sixth inter-electrode parasitic capacitance C gs2 After series connection, the parasitic capacitance C between the fourth pole ds2 in parallel; The auxiliary switch parasitic parameter circuit 4 includes an auxiliary switch first parasitic inductance circuit 41, an auxiliary switch S2, and an auxiliary switch second parasitic inductance circuit 42. The output end of the driving parasitic parameter circuit 3 is connected to the gate of the auxiliary switch S2, the drain of the auxiliary switch S2 is connected to the first input end of the auxiliary switch first parasitic inductance circuit 41, the second input end of the auxiliary switch first parasitic inductance circuit 41 is connected to the output end of the power supply circuit 1, the output end of the first parasitic inductance circuit 41 is connected to the input end of the buffer network circuit 9, and the output end of the buffer network circuit 9 is connected to the input end of the power supply circuit 1; The auxiliary switch parasitic capacitance circuit 41 includes a fifth parasitic inductor connected in series L r , Sixth parasitic inductance L d_ex2 and seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductance circuit 42 includes a ninth parasitic inductance connected in series. L s_in2 and the tenth parasitic inductance L s_ex2 The output end of the driving parasitic parameter circuit 3 is connected to the gate of the auxiliary switch S2, and the drain of the auxiliary switch S2 is connected to the seventh parasitic inductor L d_in2 One end of the seventh parasitic inductance L d_in2 The other end of the sixth parasitic inductor is connected L d_ex2 One end of the sixth parasitic inductance L d_ex2 The other end is connected to the input end of the buffer network circuit 9 and the fifth parasitic inductor L r One end of the fifth parasitic inductance L r The other end of the auxiliary switch S2 is connected to the output end of the power supply circuit 1, and the source of the auxiliary switch S2 is connected to the ninth parasitic inductor L s_in2 One end of the ninth parasitic inductance L s_in2 The other end of the tenth parasitic inductor is connected L s_ex2 One end of the tenth parasitic inductance L s_ex2The other end of the auxiliary switch parasitic parameter circuit 4 is connected to the input end of the power supply circuit 1. Here, the auxiliary switch parasitic parameter circuit 4 includes an auxiliary switch first parasitic inductance circuit and an auxiliary switch second parasitic inductance circuit. The auxiliary switch first parasitic inductance circuit is composed of a fifth parasitic inductance L r , Sixth parasitic inductance L d_ex2 and seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductance circuit is composed of the ninth parasitic inductance L s_in2 and the tenth parasitic inductance L s_ex2 The auxiliary switch S2 is composed of two series circuits, and the complex parasitic effects of the auxiliary switch S2 in the actual power electronic conversion are accurately simulated through the parasitic inductance in the auxiliary switch parasitic parameter circuit 4. This design not only improves the accuracy of the auxiliary switch parasitic parameter circuit 4, but also effectively manages the voltage and current changes in the switching process of the auxiliary switch S2 through the fine configuration of the parasitic inductance, thereby reducing the switching loss and electromagnetic interference; further, by combining the parasitic inductance with the buffer network circuit, the transient response and energy recovery mechanism of the circuit are optimized, thereby significantly improving the efficiency and stability of the entire power electronic conversion circuit.

[0027] The buffer network circuit 5 includes a first buffer parameter circuit 51, a second buffer parameter circuit 52, a feedback capacitor C o and snubber resistor R o The first buffer parameter circuit 51 includes a first buffer capacitor connected in parallel C D1 and the first diode D 1, the second buffer parameter circuit 52 includes a second buffer capacitor connected in parallel C D2 and the second diode D 2. The first buffer capacitor C D1 One end and the first diode D 1 are connected to the output terminal of the power supply circuit 1, and the first buffer capacitor C D1 The other end of the first diode is connected D 1, the negative terminal of the second buffer capacitor C D2 One end of the second diode D 2 are connected to the fifth parasitic inductor L r and the sixth parasitic inductance L d_ex2 One end of the second buffer capacitor C D2The other end of the second diode is connected D 2, the cathode of the first diode D The cathode of 1 and the second diode D 2 are connected to the negative poles of the feedback capacitors C o and snubber resistor R o One end of the feedback capacitor C o and snubber resistor R o The other ends are commonly connected to the input end of the power supply circuit 1.

[0028] The main switch S 1 and auxiliary switch S 2 Both use MOSFET tubes, the main switch S 1 and auxiliary switch S 2 Considering the inter-electrode parasitic capacitance ( C ds , C gs , C gd )、parasitic inductance( L d , L s )、Drive parasitic resistance( R g ) and anti-parallel diode and other parasitic parameters, among which the main switch S The parasitic parameters of 1 are prefixed with 1, auxiliary switch S The parasitic parameters of 2 are all prefixed with 2; the first buffer capacitor C D1 and the second buffer capacitor C D2 Respectively D 1 and D 2 parallel connection. D 1 and D The parasitic inductance of 2 can be concentrated into the stray inductance at the drain end of the MOSFET L d1 and L d2 Second parasitic resistance R g2 , the auxiliary switch parasitic capacitance circuit 41, the second buffer parameter circuit 52 and the first inter-electrode parasitic capacitance C ds1 A low-loss snubber is formed to provide a soft switching environment for the main switch S1.

[0029] right Figure 4 The topology optimization circuit shown in the figure is subjected to modal analysis, and it is found that the topology optimization circuit has 10 working modes in one cycle as follows: Figure 5As shown, modes 4, 6 and 9 are working modes different from the normal working modes, that is, potential working modes. Figure 6 for Figure 5 The switching process in the inductor. It can be seen that the inductor current i Lr exist t 5- t 8 flows through D2 and C D2 , resulting in serious waveform distortion, increased circulating current loss, and reduced converter efficiency. Although the main switch S1 implements a soft switching process, the auxiliary switch S2 is turned on under high voltage conditions and turned off under high current conditions, and there is still a large switching loss, which seriously affects the system's operating performance.

[0030] Example 3 This embodiment proposes to further optimize the snubber network circuit 5 proposed in the above embodiment, in order to improve the inductor current i Lr Waveform distortion and auxiliary switching S 2 switching environment to improve the overall performance of the circuit. The specific steps are as follows: Figure 4 In the working process of the topology optimization circuit shown in FIG. 1 , the existing potential working modes 4 and 5 are introduced, and at the same time, the buffer network circuit 5 of the topology optimization circuit is improved as shown in FIG. Figure 7 , that is, in D 1 and D Connect the positive poles of 2 C 3; D 2 Anode and L r A third diode is connected in series between D 3. D 3 is a fast recovery diode.

[0031] More specifically, the buffer network circuit 5 includes a first buffer parameter circuit 51, a second buffer parameter circuit 52, a third diode D 3. The third buffer capacitor C 3. Feedback capacitor C o and snubber resistor R o The first buffer parameter circuit 51 includes a first buffer capacitor connected in parallel C D1 and the first diode D 1, the second buffer parameter circuit 52 includes a second buffer capacitor connected in parallel C D2 and the second diode D 2. The first buffer capacitor C D1 One end of the first diodeD 1 and the positive terminal of the third buffer capacitor C 3 are connected to the output end of the power supply circuit 1, and the first buffer capacitor C D1 The other end of the first diode is connected D 1, the negative terminal of the second buffer capacitor C D2 One end of the second diode D 2 and the positive terminal of the third buffer capacitor C The other end of 3 is connected to the third diode D 3, the negative terminal of the third diode D The positive terminals of 3 are connected to the fifth parasitic inductor L r and the sixth parasitic inductance L d_ex2 One end of the second buffer capacitor C D2 The other end of the second diode is connected D 2, the cathode of the first diode D The cathode of 1 and the second diode D 2 are connected to the negative poles of the feedback capacitors C o and snubber resistor R o One end of the feedback capacitor C o and snubber resistor R o The other ends are commonly connected to the input end of the power supply circuit 1.

[0032] The optimized topology is analyzed as follows: C 3>> C D2 , C 3>> C D3 , C D3 for D The junction capacitance of 3. The working process of the improved topology optimization circuit and the switching states of each mode are shown in Table 1.

[0033] Table 1 Working modes and switching states of the improved topology optimization circuit

[0034] See also Figure 8 , in the auxiliary switch S 2 Shutdown moment, u Cds2 Start charging, C 1, C D2 ,C D3 The snubber capacitor network and auxiliary switch S 2. The parasitic capacitance of the C e2 Under the action of S 2 to achieve zero voltage shutdown. t Before time 4, the voltage at node A is not high enough to D 2 conduction, during which time L r The energy through D 3 branch directions C 3. Transfer. Set L r The inductance value is large enough, when the auxiliary switch S2 is turned off, L r Energy storage enables C Voltage on 3 u C3 reaches the output voltage. u C3 After reaching the output voltage, L r The remaining energy is D 2 is transferred to the output end until it is completely released, and its current remains zero until the next cycle when the auxiliary switch S2 is turned on. At this time, the original mode 6 is similar to the structure of the switch tube conduction stage of the ordinary Boost circuit, and its duration depends on the switch tube S 1 switch control. t 7. Always off S 1, then enter the next stage: under the action of input, C ds1 Being charged, C 1 discharge. In this mode, all switches and diodes are in the off state. The simulation waveform of the improved topology optimization circuit is as follows: Fig. 9 and Fig.10 Inductor current i Lr Waveform distortion is improved and auxiliary switching S 2's switching environment has been improved.

[0035] Example 4 See also Fig.11 This embodiment also proposes a topology optimization method for a power electronic conversion circuit based on potential circuit analysis, comprising the following steps: S1. Establish a topology optimization circuit for power electronic conversion circuit based on potential circuit analysis; see Figure 1, the topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis includes: a power supply circuit 1, a main switch parasitic parameter circuit 2, a driving parasitic parameter circuit 3, an auxiliary switch parasitic parameter circuit 4 and a buffer network circuit 5; The output end of the power supply circuit 1 is respectively connected to the input end of the main switch parasitic parameter circuit 2, the first input end of the auxiliary switch parasitic parameter circuit 4 and the first input end of the buffer network circuit 5, the first output end of the main switch parasitic parameter circuit 2 is connected to the input end of the driving parasitic parameter circuit 3, the first output end of the driving parasitic parameter circuit 3 is connected to the second input end of the auxiliary switch parasitic parameter circuit 4, the first output end of the auxiliary switch parasitic parameter circuit 4 is connected to the second input end of the buffer network circuit 5, and the output end of the buffer network circuit 5, the second output end of the auxiliary switch parasitic parameter circuit 4, the second output end of the driving parasitic parameter circuit 3 and the second output end of the main switch parasitic parameter circuit 2 are commonly connected to the input end of the power supply circuit 1.

[0036] S2. performing modal analysis on the topology optimization circuit to obtain modal analysis results; S3, performing circuit characteristic analysis on the topology optimization circuit, and outputting the influence of potential working modes on the topology optimization circuit; S4, analyzing the potential working modes that have an impact on the topology optimization circuit, obtaining the conditions under which the potential working modes that have an impact on the topology optimization circuit appear, and using the appearing conditions as the excitation conditions of the potential working modes; S5. If the impact of the potential working mode on the topology optimization circuit is positive, the excitation condition is enabled through parameter design and topology improvement; if the impact of the potential working mode on the topology optimization circuit is negative, the satisfaction of the excitation condition is suppressed through parameter design and topology improvement to obtain the topology optimization circuit, and the topology optimization ends.

[0037] In this embodiment, firstly, by integrating the main switch parasitic parameter circuit, the driving parasitic parameter circuit, the auxiliary switch parasitic parameter circuit and the buffer network circuit, a topology optimization circuit as a parasitic parameter model of the power electronic conversion circuit is established; secondly, a modal analysis is performed on the topology optimization circuit as the parasitic parameter model of the power electronic conversion circuit to obtain a modal analysis result; the modal analysis result is compared with the normal working modal threshold in the traditional circuit analysis result, and the modal analysis result different from the normal working modal threshold is identified, and the identified modal analysis result is defined as a potential working mode; then, the output characteristics and switching characteristics of the topology optimization circuit are analyzed. , efficiency and other characteristics are analyzed to obtain the impact of the potential working mode on the topology optimization circuit; then, the potential working mode that affects the topology optimization circuit is used to analyze to obtain the conditions for the occurrence of the potential working mode that affects the topology optimization circuit, and the conditions for the occurrence are used as the excitation conditions of the potential working mode; finally, if the impact of the potential working mode on the topology optimization circuit is positive, the excitation conditions are enabled through parameter design and topology improvement; if the impact of the potential working mode on the topology optimization circuit is negative, the satisfaction of the excitation conditions is suppressed through parameter design and topology improvement, the topology optimization circuit is obtained, and the topology optimization is ended.

[0038] Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A topology optimization circuit for a power electronic conversion circuit based on potential circuit analysis, characterized in that: include: A power supply circuit (1), a main switch parasitic parameter circuit (2), a driving parasitic parameter circuit (3), an auxiliary switch parasitic parameter circuit (4) and a buffer network circuit (5); The output end of the power supply circuit (1) is respectively connected to the input end of the main switch parasitic parameter circuit (2), the first input end of the auxiliary switch parasitic parameter circuit (4) and the first input end of the buffer network circuit (5); the first output end of the main switch parasitic parameter circuit (2) is connected to the input end of the driving parasitic parameter circuit (3); the first output end of the driving parasitic parameter circuit (3) is connected to the second input end of the auxiliary switch parasitic parameter circuit (4); the first output end of the auxiliary switch parasitic parameter circuit (4) is connected to the second input end of the buffer network circuit (5); the output end of the buffer network circuit (5), the second output end of the auxiliary switch parasitic parameter circuit (4), the second output end of the driving parasitic parameter circuit (3) and the second output end of the main switch parasitic parameter circuit (2) are commonly connected to the input end of the power supply circuit (1).

2. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 1 is characterized in that: The main switch parasitic parameter circuit (2) comprises a main switch first parasitic inductance circuit (21), a main switch S1, and a main switch second parasitic inductance circuit (22); the output end of the power supply circuit (1) is connected to the input end of the main switch first parasitic inductance circuit (21); the output end of the main switch first parasitic inductance circuit (21) is connected to the drain of the main switch S1; the gate of the main switch S1 is connected to the input end of the driving parasitic parameter circuit (3); the source of the main switch S1 is connected to the input end of the main switch second parasitic inductance circuit (22); and the output end of the main switch second parasitic inductance circuit (22) is connected to the input end of the power supply circuit (1).

3. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 2 is characterized in that: The main switch first parasitic inductance circuit (21) comprises first parasitic inductances connected in series L d_ex1 and the second parasitic inductance L d_in1 The second parasitic inductance circuit (22) of the main switch includes third parasitic inductances connected in series with each other. L s_in1 and the fourth parasitic inductance L d_ex1 The output end of the power supply circuit (1) is connected to the first parasitic inductor L d_ex1 One end of the first parasitic inductance L d_ex1 The other end of the second parasitic inductor is connected L d_in1 One end of the second parasitic inductance L d_in1 The other end is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input of the driving parasitic parameter circuit (3), and the source of the main switch S1 is connected to the third parasitic inductor L s_in1 One end of the third parasitic inductance L s_in1 The other end of the fourth parasitic inductor is connected L d_ex1 One end of the fourth parasitic inductance L d_ex1 The other end is connected to the input end of the power supply circuit (1).

4. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 3 is characterized in that: The driving parasitic parameter circuit (3) comprises a first parasitic resistor R g1 , drive circuit and second parasitic resistance R g2 , the gate of the main switch S1 is connected to the first parasitic resistor R g1 One end of the first parasitic resistance R g1 The other end is connected to the input end of the driving circuit, and the first output end of the driving circuit is connected to the second parasitic resistor R g2 One end of the second parasitic resistance R g2 The other end is connected to the second input end of the auxiliary switch parasitic parameter circuit (4), and the second output end of the drive circuit is connected to the input end of the power supply circuit (1).

5. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 4 is characterized in that: The auxiliary switch parasitic parameter circuit (4) comprises an auxiliary switch first parasitic inductance circuit (41), an auxiliary switch S2, and an auxiliary switch second parasitic inductance circuit (42); the output end of the driving parasitic parameter circuit (3) is connected to the gate of the auxiliary switch S2; the drain of the auxiliary switch S2 is connected to the first input end of the auxiliary switch first parasitic inductance circuit (41); the second input end of the auxiliary switch first parasitic inductance circuit (41) is connected to the output end of the power supply circuit (1); the output end of the first parasitic inductance circuit (41) is connected to the input end of the buffer network circuit (5); and the output end of the buffer network circuit (5) is connected to the input end of the power supply circuit (1).

6. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 5 is characterized in that: The auxiliary switch parasitic capacitance circuit (41) comprises a fifth parasitic inductor connected in series L r , Sixth parasitic inductance L d_ex2 and seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductance circuit (42) includes a ninth parasitic inductance connected in series L s_in2 and the tenth parasitic inductance L s_ex2 The output end of the driving parasitic parameter circuit (3) is connected to the gate of the auxiliary switch S2, and the drain of the auxiliary switch S2 is connected to the seventh parasitic inductor L d_in2 One end of the seventh parasitic inductance L d_in2 The other end of the sixth parasitic inductor is connected L d_ex2 One end of the sixth parasitic inductance L d_ex2 The other end is connected to the input end of the buffer network circuit (5) and the fifth parasitic inductor L r One end of the fifth parasitic inductance L r The other end is connected to the output end of the power supply circuit (1), and the source of the auxiliary switch S2 is connected to the ninth parasitic inductor L s_in2 One end of the ninth parasitic inductance L s_in2 The other end of the tenth parasitic inductor is connected L s_ex2 One end, the tenth parasitic inductance L s_ex2 The other end is connected to the input end of the power supply circuit (1).

7. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 6 is characterized in that: The buffer network circuit (5) comprises a first buffer parameter circuit (51), a second buffer parameter circuit (52), a feedback capacitor C o and snubber resistor R o The first buffer parameter circuit (51) includes a first buffer capacitor connected in parallel C D1 and the first diode D 1. The second buffer parameter circuit (52) includes a second buffer capacitor connected in parallel C D2 and the second diode D 2. The first buffer capacitor C D1 One end and the first diode D 1 are connected to the output terminal of the power supply circuit (1), the first buffer capacitor C D1 The other end of the first diode is connected D 1, the negative terminal of the second buffer capacitor C D2 One end of the second diode D 2 are connected to the fifth parasitic inductor L r and the sixth parasitic inductance L d_ex2 One end of the second buffer capacitor C D2 The other end of the second diode is connected D 2, the cathode of the first diode D The cathode of 1 and the second diode D 2 are connected to the negative poles of the feedback capacitors C o and snubber resistor R o One end of the feedback capacitor C o and snubber resistor R o The other ends of the two terminals are connected together to the input end of the power supply circuit (1).

8. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 6 is characterized in that: The buffer network circuit (5) comprises a first buffer parameter circuit (51), a second buffer parameter circuit (52), a third diode D 3. The third buffer capacitor C 3. Feedback capacitor C o and snubber resistor R o The first buffer parameter circuit (51) includes a first buffer capacitor connected in parallel C D1 and the first diode D 1. The second buffer parameter circuit (52) includes a second buffer capacitor connected in parallel C D2 and the second diode D 2. The first buffer capacitor C D1 One end of the first diode D 1 and the positive terminal of the third buffer capacitor C 3 are connected to the output end of the power supply circuit (1), and the first buffer capacitor C D1 The other end of the first diode is connected D 1, the negative terminal of the second buffer capacitor C D2 One end of the second diode D 2 and the positive terminal of the third buffer capacitor C The other end of 3 is connected to the third diode D 3, the negative terminal of the third diode D The positive terminals of 3 are connected to the fifth parasitic inductor L r and the sixth parasitic inductance L d_ex2 One end of the second buffer capacitor C D2 The other end of the second diode is connected D 2, the cathode of the first diode D The cathode of 1 and the second diode D 2 are connected to the negative poles of the feedback capacitors C o and snubber resistor R o One end of the feedback capacitor C o and snubber resistor R o The other ends of the two terminals are connected together to the input end of the power supply circuit (1).

9. The topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis according to claim 1, characterized in that: The power supply circuit (1) comprises a power supply U I , resistor element R L and inductor components L , the power supply U I , resistor element R L and inductor components L Connect in series.

10. A topology optimization method for power electronic conversion circuit based on potential circuit analysis, characterized in that: The following steps are involved: S1. Establish a topology optimization circuit for power electronic conversion circuit based on potential circuit analysis; S2. performing modal analysis on the topology optimization circuit to obtain modal analysis results; S3, performing circuit characteristic analysis on the topology optimization circuit, and outputting the influence of potential working modes on the topology optimization circuit; S4, analyzing the potential working modes that have an impact on the topology optimization circuit, obtaining the conditions under which the potential working modes that have an impact on the topology optimization circuit appear, and using the appearing conditions as the excitation conditions of the potential working modes; S5. If the impact of the potential working mode on the topology optimization circuit is positive, enabling the excitation condition through parameter design and topology improvement; If the potential working mode has a negative impact on the topology optimization circuit, the excitation condition is suppressed through parameter design and topology improvement to obtain the topology optimization circuit, and the topology optimization ends.

Images