Cross-domain clock synchronization method in time sensitive network

Abstract

The invention relates to a cross-domain clock synchronization method in a time sensitive network, and belongs to the technical field of time synchronization. The method comprises the following steps: establishing a multi-domain clock synchronization network topology based on a transit clock; the transit clock obtains main clock time according to the main domain synchronization message, carries out link delay measurement message interaction with adjacent equipment, records a corresponding timestamp and obtains link delay; transmitting the acquired main clock time, each timestamp and link delay to a synchronization error compensation prediction module in the transfer clock, calculating a clock time offset result by the synchronization error compensation prediction module, and predicting error compensation; frequency and phase adjustment is carried out on a local clock according to the calculated error compensation predicted value, a slave domain synchronization message is sent to adjacent slave clock equipment, and forwarding of the slave domain synchronization message and clock correction are carried out in sequence. According to the invention, accumulated errors such as jitter, time delay change and network congestion can be eliminated as much as possible.

Description

Technical Field

[0001] The invention belongs to the technical field of time synchronization and relates to a cross-domain clock synchronization method in a time-sensitive network. Background Art

[0002] Time-Sensitive Networking (TSN) is a set of standards for real-time, deterministic communications in the fields of industry, power, etc. At present, with the expansion of the scale of power grids, the integration of new energy sources, and the development of ultra-high voltage transmission technology, power grids are becoming more and more complex and intelligent. In smart grids, although applications such as synchronous sampling, fault detection, event sequence recording, event location estimation, and coordination of work between devices are different in the process of various specific actions, they all have the common point that they all require accurate time synchronization capabilities to eliminate the differences between local clocks. Therefore, time synchronization in smart grids is of great significance to the safe and stable operation of each node. In response to this demand, the TSN protocol led by IEEE 802.1AS provides an accurate time synchronization solution, which greatly simplifies the previous redundant synchronization process and improves the efficiency and accuracy of time synchronization.

[0003] IEEE 802.1AS proposes a time-aware network consisting of multiple gPTP domains. Figure 1 An example of a time-aware network consisting of multiple gPTP domains is shown. Specifically, in this example, the network has two time domains, where domain 0 uses the PTP time scale and domain 1 uses the arbitrary (ARB) time scale. It is required that all PTP instances belonging to the same domain have a direct connection in their physical topology (e.g., time cannot be transferred from one PTP instance in domain 0 to another PTP instance in domain 0 via a time-aware system without domain 0 being active). Additionally, a time-aware system where both domains are active is represented by a slanted inner hatched line, representing two independent active PTP instances.

[0004] like Figure 2 The synchronization message format shown in the figure has a domianNumber field in it. The function of this field is to divide the synchronization domain. Only clocks in the same synchronization domain can perform clock synchronization related behaviors. The default value of domianNumber is 0.

[0005] In practical applications, such as Figure 3 As shown, due to the low precision of the crystal oscillator of the slave clock, the clock time will always drift. The clock frequency and phase of the slave clock will continue to shift after being corrected, resulting in the need for continuous correction of the slave clock. Moreover, due to the different crystal oscillator performances of different clocks, the offsets caused between synchronization cycles are different.

[0006] Currently, due to the continuous expansion of production scale, there are more and more network nodes, and the number of message transmission hops is also increasing. The accuracy of clock synchronization will gradually decrease with the increase of hops, which leads to a decrease in the synchronization accuracy of edge devices and a continuous decrease in the anti-interference ability during the synchronization process. Summary of the invention

[0007] In view of this, an object of the present invention is to provide a cross-domain clock synchronization method in a time-sensitive network.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A cross-domain clock synchronization method in a time-sensitive network comprises the following steps:

[0010] S1. Establish a multi-domain clock synchronization network topology based on transit clocks in a multi-clock domain environment of a time-sensitive network;

[0011] S2. The transit clock obtains the master clock time according to the master domain synchronization message, and exchanges link delay measurement messages with the adjacent device, records the corresponding timestamp and obtains the link delay;

[0012] S3, passing the acquired master clock time, each timestamp, and link delay to the synchronization error compensation prediction module in the transit clock, which then calculates the clock time offset result in combination with the adjacent clock frequency ratio and predicts the error compensation;

[0013] S4. The clock correction module in the transit clock adjusts the frequency and phase of the local clock according to the calculated error compensation prediction value, and then sends a slave domain synchronization message to the adjacent slave clock device, and forwards the slave domain synchronization message and corrects the clock in turn.

[0014] Further, in step S1, the master clock in the time-sensitive network and the set of synchronization devices directly connected to and synchronized with the master clock are set to B. m The clock domain is divided into the master clock domain, and the remaining set of synchronous devices close to the edge of the network is called the slave clock domain. There is a bridge between the master clock domain and the slave clock domain, namely device i, which is defined as the transit clock.

[0015] The transit clock is in both the master clock domain and the slave clock domain. In the master clock domain, the transit clock is a slave clock, which receives synchronization messages sent by the clock source and corrects its own time. In the slave clock domain, the transit clock serves as the master clock of the domain and sends synchronization messages. Other devices in the slave clock domain receive the synchronization messages sent by the transit clock and correct their own clocks. The transit clock can predict and correct synchronization errors based on the network environment.

[0016] Furthermore, a local clock module, a message receiving port, a message sending port, a timestamp generating module, a synchronization error compensation prediction module and a clock correction module are arranged inside the transit clock, wherein the local clock is configured as a free-running clock existing in the entity of the transit clock, providing a time t for the transit clock. l ; The timestamp generation module records the timestamp of the message receiving and sending time when the port exchanges messages. 1 ~t 6 The synchronization error compensation prediction module calculates the clock time offset result according to the received message content and timestamp, and predicts the synchronization error compensation value that needs to be compensated; the clock correction module adjusts the local clock by modifying the frequency and phase according to the calculation results.

[0017] Further, in step S2, the transit clock receiving port receives the Sync / Follow_Up message sent by the Grand Master, and parses the master clock time t in the message. M , and record and process timestamps as follows:

[0018] S21, the peer delay initiator sends Pdelay_Req to the peer delay responder and records the time t when the message is sent 1 ;

[0019] S22. The peer delay responder records the timestamp t when receiving Pdelay_Req. 2 ; After receiving Pdelay_Req, return the 2 The Pdelay_Resp message is sent to the peer delay requester, and the timestamp t of the time when the Pdelay_Resp message is sent is recorded. 3 ; followed by sending a 3 Pdelay_Resp_Follow_Up message;

[0020] S23, when the peer delay initiator receives the Pdelay_Resp message, it records the time t when the message is received 4 ;

[0021] S24, through the timestamp t recorded above 1 ,t 2 ,t 3 and t 4 , the initiator calculates the link delay d.

[0022] Further, in step S24, the link delay d is calculated as follows:

[0023]

[0024] Where gmRR is the frequency ratio between the master and slave clocks:

[0025]

[0026] gmRR is calculated based on historical data, where (t 3 ) N and (t 4 ) N are the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the Nth link delay measurement, (t 3 ) 0 and (t 4 ) 0 Indicates the time when the first delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message.

[0027] Further, in step S3, the synchronization error compensation prediction module predicts the clock time offset compensation value in the following manner:

[0028] S31, obtain synchronization timestamp and calculate synchronization error: obtain timestamp from master clock and slave clock to obtain master clock time vector T M , from the clock time vector T S and link delay time vector T D , and calculate the time error T E And synchronization error offset;

[0029] S32, collect the T M , T S , T D and T E The data is processed into a matrix form. The data set matrix includes input and target output. The Nk samples of the entire data set D = {(x 1 ,TE k+1 ),(x 2 ,TE k+2 )…,(x i ,TE k+i ),…,(x N-k ,TE N )}, where input x i =[(T M ) i ,(T s ) i ,(T D ) i ,(TE) i ], enter x i The form is:

[0030] (T M ) i =(t M(i) ,t M(i+1) ,...,t M(i+k-1) ) T

[0031] (T S ) i =(t S(i) ,t S(i+1) ,...,t S(i+k-1) ) T

[0032] (T D ) i =(t D(i) ,t D(i+1) ,...,t D(i+k-1) ) T

[0033] (TE) i =(TE i+1 ,TE i+2 ,…,TE i+k-1 ) T

[0034] S33, train the neural network based on the data set, adjust the training parameters according to the output, and output the prediction result offset pre ;

[0035] S34. Determine a threshold range according to the Gaussian distribution of the synchronization error, judge the factors affecting the synchronization error, and then determine the final deviation.

[0036] Further, in step S31, the master clock periodically sends Sync messages and Follow_Up messages, and after receiving the Sync message from the slave clock, it calculates:

[0037] t i =t GM +CF sync +d

[0038] Among them, t i Indicates the time when the transit clock is synchronized and corrected; t GM Indicates the time of the main clock; CF sync Indicates the correction value recorded in the Follow_Up message, including the residence time of each node from the Sync message and the link delay between nodes:

[0039]

[0040] Where x represents each synchronization node before the current node; ρx It is expressed as the residence time within the synchronization device;

[0041] When network fluctuations occur in the network, a delay of μ is generated on the link, and the transit clock time becomes:

[0042] t i =t GM +CF sync +d+μ

[0043] Further we get:

[0044]

[0045] where t′ x Indicates the timestamp when the delay request message is received from the clock when there is a link delay. d′ indicates the link delay caused by network fluctuations.

[0046] Then the offset is expressed as:

[0047]

[0048] Therefore, each time vector as input is expressed as:

[0049] T M =(t M1 ,t M2 ,…t MN ) T

[0050] T S =(t S1 ,t S2 ,…t SN ) T

[0051] T D =(t D1 ,t D2 ,…t DN ) T

[0052] T E =t S -t M

[0053] Among them, t M and t S Respectively represent the timestamps of the master clock and the slave clock during calculation.

[0054] Further, in step S34, the error of the synchronization clock conforms to the Gaussian distribution, that is:

[0055]

[0056] Where x is the clock error, μ is the mean, σ is the standard deviation, 2σ is used as the compensation judgment standard, and the error range is set to (θ 1 ,θ 2 ), set the threshold θ 1 =μ-2σ,θ 2 =μ+2μ;

[0057] If the error value of the synchronization clock is not within the error range (θ 1 ,θ 2 ), it is considered to be caused by network environment problems; if the error value of the synchronization clock is within (θ 1 ,θ 2 ), it is considered to be an error caused by frequency change:

[0058]

[0059] t cmp =|μ real -μ pre |

[0060] Where offset is the actual deviation of the clock, μ real represents the mean value of the actual synchronization error, μ pre represents the mean of the prediction error, t cmp The difference between the absolute values ​​of the two is the compensation value.

[0061] Further, in step S4, adjacent synchronization clocks forward synchronization messages and perform clock correction after link delay measurement. In the same clock domain, the steps of using synchronization messages to correct time are as follows:

[0062] S41. When the clock receives the Sync message, it records the timestamp of receiving the Sync message;

[0063] S42, the synchronization clock reads the timestamp t generated by the master device from the subsequent Follow_Up message 5 and the accumulated Correction_Field, which contains the residence time and link delay of all clock nodes;

[0064] S43, after receiving the synchronization message, synchronize the received t 5 and t 6 Calculate the synchronization error relative to the master clock;

[0065] S44, the synchronization clock adjusts the local clock according to the calculated synchronization error to keep it synchronized with the master clock;

[0066] S45. After the adjustment is completed, the synchronization clock will forward the Sync message to the downstream node and record the timestamp t′ of sending the Sync message. 5 , and includes the timestamp t′ in the subsequent Follow_Up message 5 ;

[0067] S46. Update the Correction_Field in the Follow_Up message, and add its own link delay and residence time to the original values ​​for subsequent clock synchronization.

[0068] The beneficial effects of the present invention are:

[0069] 1) In a multi-hop network, when synchronization messages pass through each hop, errors such as jitter, delay variation, and network congestion will accumulate. If we only rely on the time of the forwarding master clock, these errors will gradually amplify, resulting in a decrease in synchronization accuracy. These errors can be eliminated as much as possible through the transfer clock.

[0070] 2) The transit clock has the ability to predict synchronization errors and compensate for them, which can effectively reduce the accumulation of errors in the traditional multi-hop forwarding process. Through this prediction mechanism, high synchronization accuracy can be maintained at more distant clock nodes.

[0071] 3) Transit clocks can achieve more localized and adaptive synchronization management by dividing the network into two synchronization domains. Each synchronization domain can be optimized according to local network conditions, thereby reducing the synchronization error caused by delays and fluctuations in the entire network.

[0072] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0074] Figure 1 An example diagram of a time-aware network for multiple gPTP domains;

[0075] Figure 2 This is a schematic diagram of the synchronization message format;

[0076] Figure 3 Schematic diagram of clock deviation;

[0077] Figure 4A topological diagram of a multi-domain clock synchronization network based on a transit clock according to the present invention;

[0078] Figure 5 It is the internal framework diagram of the transfer clock of the present invention;

[0079] Figure 6 It is a schematic diagram of the interaction process of the transfer clock of the present invention;

[0080] Figure 7 It is a schematic diagram of the peer-to-peer delay measurement method of the present invention;

[0081] Figure 8 It is a schematic diagram of the structure of the time error prediction neural network of the present invention. DETAILED DESCRIPTION

[0082] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0083] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0084] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0085] See also Figures 4 to 8 , which is a cross-domain clock synchronization method in time-sensitive networks.

[0086] Example

[0087] This embodiment proposes a clock synchronization method based on multiple clock domains. The method defines a new clock role, namely, a transit clock, which can divide all synchronization nodes into two synchronization domains, and predicts and corrects the synchronization error value of the transit clock by performing synchronization error prediction according to a synchronization error model of a network environment. The method includes the following steps:

[0088] S1. Establish a multi-domain clock synchronization network topology based on transit clocks in a multi-clock domain environment of a time-sensitive network;

[0089] S2. The transit clock obtains the master clock time according to the master domain synchronization message, and exchanges link delay measurement messages with the adjacent device, records the corresponding timestamp and obtains the link delay;

[0090] S3, passing the acquired master clock time, each timestamp, and link delay to the synchronization error compensation prediction module in the transit clock, which then calculates the clock time offset result in combination with the adjacent clock frequency ratio and predicts the error compensation;

[0091] S4. The clock correction module in the transit clock adjusts the frequency and phase of the local clock according to the calculated error compensation prediction value, and then sends a slave domain synchronization message to the adjacent slave clock device, and forwards the slave domain synchronization message and corrects the clock in turn.

[0092] In step S1 of this embodiment, Figure 4 The multi-domain clock synchronization network topology diagram based on the transit clock shown in FIG. 1 includes a master clock and a set of synchronization devices that are directly connected to and synchronized with the master clock. m , m∈[1,i] is divided into the master clock domain (Master Domain); the remaining set of synchronous devices close to the edge of the network is called the slave clock domain (ServantDomain). There is a "bridge" between the master clock domain and the slave clock domain to communicate the two clock domains, namely the correspondence clock of device i. The correspondence clock is in both the master clock domain and the slave clock domain. In the master clock domain, the correspondence clock is a slave clock, which receives the synchronization message sent by the clock source and corrects its own time. In the slave clock domain, the correspondence clock is the master clock of the domain and sends synchronization messages. The rest of the devices in the slave clock domain receive the synchronization message sent by the correspondence clock and correct their own clocks. At the same time, in order to improve the synchronization accuracy of the synchronous devices in the slave clock domain, the correspondence clock predicts and corrects the synchronization error based on the network environment to improve the synchronization accuracy and stability of its own clock, thereby improving the stability of the devices in the slave clock domain.

[0093] like Figure 5The framework diagram of the transit clock shown in FIG. 1 shows the description of the synchronization function of the transit clock. The transit clock is provided with a clock signal by the local clock. The transit clock is provided with a local clock module, a message receiving port, a message sending port, a timestamp generation module, a synchronization error compensation prediction module, and a clock correction module. The local clock is configured as a free-running clock existing in the transit clock entity, providing the transit clock with a time t l ; The timestamp generation module records the timestamp of the message receiving and sending time when the port exchanges messages. 1 ~t 6 The synchronization error compensation prediction module calculates the clock time offset result according to the received message content and timestamp, and predicts the synchronization error compensation value that needs to be compensated; the clock correction module adjusts the local clock by modifying the frequency and phase according to the calculation results.

[0094] In step S2, the transit clock receiving port receives the Sync / Follow_Up message sent by the Grand Master and parses the master clock time t in the message. M . Send Pdelay_Req, Pdelay_resp, and Pdelay_Resp_Follow_Up messages to other adjacent devices, and record the time t when the delay measurement requester sends the Pdelay_Req message 1 , Delay measurement The time t when the corresponding party receives the Pdelay_Req message 2 , the time t when the delay measurement responder sends the Pdelay_Resp message 3 , the time t when the delay measurement initiator receives the Pdelay_Resp message 4 , and according to t 1 ,t 2 ,t 3 ,t 4 Calculate the link delay d. Specifically, if Figure 6 As shown, it includes the following processes:

[0095] S21. The peer delay initiator sends Pdelay_Req to the peer delay responder and records the time when the message is sent, which is recorded as t 1 .

[0096] S22. The peer delay responder records the timestamp t when receiving Pdelay_Req. 2 After receiving Pdelay_Req, it returns a message containing t 2The Pdelay_Resp message is sent to the peer delay requester, and the timestamp t of the time when the Pdelay_Resp message is sent is recorded. 3 . Then send a message containing t 3 Pdelay_Resp_Follow_Up message.

[0097] S23: When the peer delay initiator receives the Pdelay_Resp message, it records the timestamp of receiving the message, which is t 4 .

[0098] S24, through the timestamp t recorded above 1 ,t 2 ,t 3 and t 4 , the synchronization correction module of the initiator calculates the link delay d. Let the master clock time be t M , from the clock time t s , in an ideal situation, the offset η of the synchronous clock can be calculated:

[0099] η=t s -t M

[0100] Since the clock accuracy of the slave clock is lower than that of the master clock and there is a frequency change, let Δfη represent the time offset caused by the clock frequency change. After taking the time offset into account, the synchronization offset value η can be changed to:

[0101] ε=η-Δfη=t s -t M

[0102] Δfη=gmRR·(t cur -t fro )

[0103] t cur Indicates the local time corrected after the synchronization clock receives the synchronization message;

[0104] t fro Expressed as the time that has passed since the clock last received a Sync message.

[0105] Where gmRR represents the frequency ratio between the master and slave clocks:

[0106]

[0107] When the synchronous clock performs link delay measurement, it exchanges three delay measurement messages with the peer delay responder to obtain four timestamps t 1 ~t 4 , the process is as follows Figure 7As shown, the corresponding link delay is calculated again, and considering the impact of the change in the transit clock frequency, it can be obtained:

[0108] t 2 -t 1 =d+Δfη

[0109] t 4 -t 3 =d-Δfη

[0110] Where d is the link delay. Substituting it into the above formula, we get the modified link delay measurement formula:

[0111] t 2 -t 1 =d+gmRR·(t 1 -t fro )

[0112] t 4 -t 3 =d-gmRR·(t 4 -t fro )

[0113] Get the corrected link delay d:

[0114]

[0115] In step S3 of this embodiment, the prediction algorithm of the clock synchronization error of the synchronization error compensation prediction module uses a neural network to perform synchronization prediction. The input of the prediction algorithm is T S ,T M ,T D ,T E Vector, the output is the predicted value TE of the synchronization error pre , the synchronization error prediction algorithm framework is as follows Figure 8 As shown, the time error prediction compensation steps are as follows:

[0116] S31, obtain synchronization timestamp and calculate synchronization error: obtain timestamp from master clock and slave clock to obtain master clock time vector T M , from the clock time vector T S and link delay time vector T D , and calculate the time error T E And synchronization error offset;

[0117] When the Sync message passes through the transit clock, the transit clock receives the Sync message, corrects and predicts and compensates its own clock, and then sends a new Sync message marked with the slave domain identifier to the next clock.

[0118] Let the master clock time be tM , from the clock time t s , in an ideal situation, the offset η of the synchronous clock can be calculated:

[0119] η=t s -t M

[0120] Since the clock accuracy of the slave clock is lower than that of the master clock and there is a frequency change, let Δfη represent the time offset caused by the clock frequency change. After taking the time offset into account, the synchronization offset value η can be changed to:

[0121] ε=η-Δfη=t s -t M

[0122] Δfη=gmRR·(t cur -t fro )

[0123] t cur Indicates the local time corrected after the synchronization clock receives the synchronization message;

[0124] t fro Expressed as the time that has passed since the clock last received a Sync message.

[0125] Where gmRR represents the frequency ratio between the master and slave clocks:

[0126]

[0127] When the synchronous clock performs link delay measurement, it exchanges three delay measurement messages with the peer delay responder to obtain four timestamps. 1 ~t 4 The corresponding link delay is calculated by running the calculation, and considering the influence of the change of the transit clock frequency, it can be obtained:

[0128] t 2 -t 1 =d+Δfη

[0129] t 4 -t 3 =d-Δfη

[0130] Where d is the link delay. Substituting it into the above formula, we get the modified link delay measurement formula:

[0131] t 2 -t 1 =d+gmRR·(t 1 -t fro )

[0132] t 4 -t3 =d-gmRR·(t 4 -t fro )

[0133] Get the corrected link delay d:

[0134]

[0135] The master clock periodically sends Sync messages and Follow_Up messages. After the slave clock receives the Sync message, it calculates:

[0136] t i =t GM +CF sync +d

[0137] where t s Indicates the time when the transit clock has been synchronized and corrected;

[0138] t GM Indicates the time of the master clock;

[0139] CF sync Indicates the correction value recorded in the Follow_Up message, including the residence time of each node from the Sync message and the link delay between nodes:

[0140]

[0141] Where x represents each synchronization node before the current node;

[0142] ρ x Expressed as the dwell time within the synchronized device.

[0143] When network fluctuations occur in the network, a delay of μ is generated on the link, and the transit clock time becomes:

[0144] t i =t GM +CF sync +d+μ

[0145] Combined with the modified path measurement formula, we can get:

[0146]

[0147] where t′ x represents the timestamp when the delay request message is received from the clock when there is a link delay, and d′ represents the link delay caused by network environment problems (such as network congestion, etc.); then offset can be expressed as:

[0148]

[0149] The data in the above formula can be calculated by obtaining the timestamps contained in the synchronization messages exchanged between the master and slave clocks, so each timestamp can be used as the input of the prediction algorithm. gmRR is calculated based on historical data, and since the past timestamps with phase information can reflect the trend of clock frequency changes, the input times can be written as:

[0150] T M =(t M1 ,t M2 ,...t MN ) T

[0151] T S =(t S1 ,t S2 ,...t SN ) T

[0152] T D =(t D1 ,t D2 ,...t DN ) T

[0153] Where T M represents the master clock time vector, T S represents the slave clock time vector, T D Represents the link delay time vector. The link delay time is calculated from four timestamps.

[0154] The time difference between the master clock and the slave clock is defined as the time error T E .t M and t S Respectively represent the timestamps of the master clock and the slave clock during calculation:

[0155] T E =t S -t M

[0156] TE is the difference in timestamp value. According to the above formula, the T that needs to be compensated is E It is believed to be the result of clock time drift.

[0157] S32, Dataset Generation: Collect the T M , T S , T D and T E The data is processed into a matrix form for further processing. The data set matrix includes the input and target output, and the Nk samples of the entire data set D = {(x 1 ,TE k+1 ),(x2 ,TE k+2 )…,(x i ,TE k+i ),…,(x N-k ,TE N )}, where input x i For: x i =[(T M ) i ,(T s ) i ,(T D ) i ,(TE) i ] Enter x i The specific form is as follows:

[0158] (T M ) i =(t M(i) ,t M(i+1) ,...,t M(i+k-1) ) T

[0159] (T S ) i =(t S(i) ,t S(i+1) ,…,t S(i+k-1) ) T

[0160] (T D ) i =(t D(i) ,t D(i+1) ,...,t D(i+k-1) ) T

[0161] (TE) i =(TE i+1 ,TE i+2 ,…,TE i+k-1 ) T

[0162] S33, neural network prediction: Figure 8 As shown, the neural network is trained using the data set, and the training parameters are adjusted according to the output, and the prediction result offset is output. pre ;

[0163] Input layer: The LSTM input layer passes the input data sequence to the subsequent hidden layer, where the data is formatted to suit subsequent calculations;

[0164] Hidden layer: processes each timestamp value in the input layer, accumulates the dependencies between the input data through three gates, and then obtains the output value, i.e., the synchronization error value, through linear transformation and activation function;

[0165] Output layer: Outputs the synchronization error value for a period of time in the future.

[0166] S34, calculating the synchronization error, and determining the threshold range according to the Gaussian distribution of the synchronization error, and then determining the factors affecting the synchronization error; since the error of the synchronization clock roughly conforms to the Gaussian distribution, that is:

[0167]

[0168] Where x is the clock error, μ is the mean, σ is the standard deviation, and 2σ is used as the compensation judgment standard. About 95% of the data are in the interval (μ-2σ,μ+2σ), so the threshold is determined to be θ 1 =μ-2σ,θ 2 =μ+2σ.

[0169] If the error value of the synchronous clock is greater than or less than the set threshold, that is, offset < θ 1 or offset>θ 2 , it is considered that the error is caused by network environment problems such as link blocking, and since the frequency of the synchronous clock is relatively stable, it is considered that the offset is in (θ 1 ,θ 2 ) is caused by frequency variation.

[0170]

[0171] t cmp =|μ real -μ pre |

[0172] Where, offset is the actual deviation of the clock, μ real represents the mean value of the actual synchronization error, μ pre represents the mean of the prediction error, t cmp It represents the difference between the absolute values ​​of the two, that is, the compensation value.

[0173] In step S4 of this embodiment, adjacent synchronous clocks forward synchronization messages and perform clock correction after link delay measurement. In the same clock domain, the steps of using synchronization messages to correct time are as follows:

[0174] S41. When the clock receives the Sync message, it records the timestamp t 6 , indicating the time when the Sync message is received.

[0175] S42, the synchronization clock reads the timestamp t generated by the master device from the subsequent Follow_Up message 5And the accumulated Correction_Field (correction field, denoted as CFsync). This field contains the residence time and link delay of all clock nodes.

[0176] S43, after receiving the synchronization message, synchronize the received t 5 and t 6 Calculate the synchronization error relative to the master clock

[0177] S44. The synchronization clock adjusts the local clock according to the calculated synchronization error to keep it synchronized with the master clock.

[0178] S45. After the adjustment is completed, the synchronous clock will forward the Sync message to the downstream node. At this time, the timestamp t′ of the Sync message is recorded. 5 , and includes the timestamp in the subsequent Follow_Up message.

[0179] S46. In the Follow_Up message, the Correction_Field (CFsync) is updated, and its own link delay and residence time are added to the original CFsync value, ensuring that the correction value received by the downstream node is the cumulative delay on the entire path.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A cross-domain clock synchronization method in a time-sensitive network, characterized in that: It includes the following steps: S1. Establish a multi-domain clock synchronization network topology based on transit clocks in a multi-clock domain environment of a time-sensitive network; S2. The transit clock obtains the master clock time according to the master domain synchronization message, and exchanges link delay measurement messages with the adjacent device, records the corresponding timestamp and obtains the link delay; S3, passing the acquired master clock time, each timestamp, and link delay to the synchronization error compensation prediction module in the transit clock, which then calculates the clock time offset result in combination with the adjacent clock frequency ratio and predicts the error compensation; S4. The clock correction module in the transit clock adjusts the frequency and phase of the local clock according to the calculated error compensation prediction value, and then sends a slave domain synchronization message to the adjacent slave clock device, and forwards the slave domain synchronization message and corrects the clock in turn.

2. The method for cross-domain clock synchronization in a time-sensitive network according to claim 1, characterized in that: In step S1, a master clock in a time-sensitive network and a set of synchronization devices directly connected to and synchronized with the master clock are set to m The clock domain is divided into the master clock domain, and the remaining set of synchronous devices close to the edge of the network is called the slave clock domain. There is a bridge between the master clock domain and the slave clock domain, namely device i, which is defined as the transit clock. The transit clock is in both the master clock domain and the slave clock domain. In the master clock domain, the transit clock is a slave clock, which receives synchronization messages sent by the clock source and corrects its own time. In the slave clock domain, the transit clock serves as the master clock of the domain and sends synchronization messages. Other devices in the slave clock domain receive the synchronization messages sent by the transit clock and correct their own clocks. The transit clock can predict and correct synchronization errors based on the network environment.

3. The method for cross-domain clock synchronization in a time-sensitive network according to claim 2, characterized in that: The transit clock is internally provided with a local clock module, a message receiving port, a message sending port, a timestamp generating module, a synchronization error compensation prediction module and a clock correction module, wherein the local clock is configured as a free-running clock existing in the transit clock entity, providing the transit clock with a time t l ; The timestamp generation module records the timestamps t1~t6 of the message reception and sending times when the port interacts with each other; the synchronization error compensation prediction module calculates the clock time offset result according to the received message content and timestamp, and predicts the synchronization error compensation value that needs to be compensated; the clock correction module adjusts the local clock by modifying the frequency and phase according to the calculation results.

4. The method for cross-domain clock synchronization in a time-sensitive network according to claim 3, characterized in that: In step S2, the transit clock receiving port receives the Sync / Follow_Up message sent by the Grand Master and parses the master clock time t in the message. M , and record and process timestamps as follows: S21, the peer delay initiator sends Pdelay_Req to the peer delay responder and records the time t1 when the message is sent; S22, the peer delay responder records the timestamp t2 when receiving Pdelay_Req; after receiving Pdelay_Req, it returns a Pdelay_Resp message containing t2 to the peer delay requester, and records the timestamp t3 of the time when the Pdelay_Resp message is sent; and then immediately sends a Pdelay_Resp_Follow_Up message containing t3; S23, when the peer delay initiator receives the Pdelay_Resp message, it records the time t4 when the message is received; S24. The initiator calculates the link delay d using the timestamps t1, t2, t3 and t4 recorded above.

5. The method for cross-domain clock synchronization in a time-sensitive network according to claim 4, characterized in that: In step S24, the link delay d is calculated as follows: Where gmRR is the frequency ratio between the master and slave clocks: gmRR is calculated based on historical data, where (t3) N and (t4) N They are respectively the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the Nth link delay measurement. (t3)0 and (t4)0 represent the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the first delay measurement.

6. The method for cross-domain clock synchronization in a time-sensitive network according to claim 5, characterized in that: In step S3, the synchronization error compensation prediction module predicts the clock time offset compensation value in the following manner: S31, obtain synchronization timestamp and calculate synchronization error: obtain timestamp from master clock and slave clock to obtain master clock time vector T M , from the clock time vector T S and link delay time vector T D , and calculate the time error T E And synchronization error offset; S32, collect the T M 、T S 、T D and T E The data is processed into a matrix form. The data set matrix includes input and target output. The Nk samples of the entire data set D = {(x1,TE k+1 ),(x2,TE k+2 )…,(x i ,TE k+i ),…,(x N-k ,TE N )}, where input x i =[(T M ) i ,(T s ) i ,(T D ) i ,(TE) i ], enter x i The form is: (T M ) i =(t M(i) ,t M(i+1) ,…,t M(i+k-1) ) T (T S ) i =(t S(i) ,t S(i+1) ,...,t S(i+k-1) ) T (T D ) i =(t D(i) ,t D(i+1) ,...,t D(i+k-1) ) T (TE) i =(TE i+1 ,TE i+2 ,...,TE i+k-1 ) T S33, train the neural network based on the data set, adjust the training parameters according to the output, and output the prediction result offset pre ; S34. Determine a threshold range according to the Gaussian distribution of the synchronization error, judge the factors affecting the synchronization error, and then determine the final deviation.

7. The method for cross-domain clock synchronization in a time-sensitive network according to claim 6, characterized in that: In step S31, the master clock periodically sends Sync messages and Follow_Up messages. After receiving the Sync message, the slave clock calculates: t i =t GM +CF sync +d Among them, t i Indicates the time when the transit clock is synchronized and corrected; t GM Indicates the time of the main clock; CF sync Indicates the correction value recorded in the Follow_Up message, including the residence time of each node from the Sync message and the link delay between nodes: Where x represents each synchronization node before the current node; ρ x It is expressed as the residence time within the synchronization device; When network fluctuations occur in the network, a delay of μ is generated on the link, and the transit clock time becomes: t i =t GM +CF sync +d+μ Further we get: where t′ x Indicates the timestamp when the delay request message is received from the clock when there is a link delay. d′ indicates the link delay caused by network fluctuations. Then the offset is expressed as: Therefore, each time vector as input is expressed as: T M =(t M1 ,t M2 ,...t MN ) T T S =(t S1 ,t S2 ,...t SN ) T T D =(t D1 ,t D2 ,...t DN ) T T E =t S -t M Among them, t M and t S Respectively represent the timestamps of the master clock and the slave clock during calculation.

8. The method for cross-domain clock synchronization in a time-sensitive network according to claim 7, characterized in that: In step S34, the error of the synchronization clock conforms to the Gaussian distribution, that is: Where x is the clock error, μ is the mean, σ is the standard deviation, 2σ is used as the compensation judgment standard, the error range is set to (θ1, θ2), and the thresholds are set to θ1 = μ-2σ, θ2 = μ+2σ; If the error value of the synchronization clock is not within the error range (θ1, θ2), it is considered to be caused by network environment problems; if the error value of the synchronization clock is within (θ1, θ2), it is considered to be caused by frequency changes: t cmp =|μ real -m pre | Where, offset is the actual deviation of the clock, μ real represents the mean value of the actual synchronization error, μ pre represents the mean of the prediction error, t cmp It represents the difference between the absolute values ​​of the two, that is, the compensation value.

9. The method for cross-domain clock synchronization in a time-sensitive network according to claim 6, characterized in that: In step S4, adjacent synchronous clocks forward synchronization messages and perform clock correction after link delay measurement. In the same clock domain, the steps of using synchronization messages to correct time are as follows: S41. When the clock receives the Sync message, it records the timestamp of receiving the Sync message; S42, the synchronous clock reads the timestamp t5 generated by the master device and the accumulated Correction_Field from the subsequent Follow_Up message, where Correction_Field includes the residence time and link delay of all clock nodes; S43, after receiving the synchronization message, synchronously use the received t5 and t6 to calculate the synchronization error relative to the master clock; S44, the synchronization clock adjusts the local clock according to the calculated synchronization error to keep it synchronized with the master clock; S45. After the adjustment is completed, the synchronization clock will forward the Sync message to the downstream node, record the timestamp t′5 of sending the Sync message, and include the timestamp t′5 in the Follow_Up message sent subsequently; S46. Update the Correction_Field in the Follow_Up message, and add its own link delay and residence time to the original values ​​for subsequent clock synchronization.

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