Apparatus and method of manufacturing switched capacitor circuit

Abstract

Disclosed embodiments may include an apparatus including a first device layer including a first switch, a second device layer including a second switch, and a third device layer disposed between the first device layer and the second device layer. The third device layer includes a first capacitor. The first switch and the second switch are interconnected with the first capacitor to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the second switch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 364,569 filed on May 12, 2022 and U.S. Provisional Patent Application No. 63 / 364,674 filed on May 13, 2022, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to power electronics and more particularly to power converters. Background Art

[0004] Modern central processing units (CPUs) are evolving to provide higher computing performance, such as artificial intelligence (AI) processing and cloud computing applications, which results in a progressively increasing demand for power from power supplies. As a result, power converters in power supplies may occupy considerable space to meet the growing current requirements of the CPU. Therefore, designing compact and high-density power converters to reduce the required circuit area while meeting the increased current and space requirements has become a challenge in the art. Summary of the invention

[0005] Embodiments of the present disclosure provide a device. The device includes a first device layer, a second device layer, and a third device layer disposed between the first device layer and the second device layer, the first device layer including a first switch, the second device layer including a second switch. The third device layer includes a first capacitor. The first switch and the second switch are interconnected with the first capacitor to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the second switch.

[0006] Embodiments of the present disclosure provide a device. The device includes a cell and a phase device cell. Each cell in the cell includes a capacitor and a first switch. The phase device cell includes a second switch. The cell is stacked vertically on the phase device cell. The capacitor and the first switch in each cell are interconnected with the second switch to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the second switch in each cell.

[0007] An embodiment of the present disclosure provides a method for manufacturing a switched capacitor circuit. The method includes: providing a first device layer; disposing a third device layer on the first device layer; interconnecting a first capacitor in the third device layer with a first switch in the first device layer; disposing a second device layer on the third device layer; and interconnecting a second switch in the second device layer with the first capacitor.

[0008] Embodiments of the present disclosure provide a method for manufacturing a switched capacitor circuit. The method includes: providing a phase device unit, the phase device unit including a phase switch of the switched capacitor circuit; and vertically stacking units above the phase device unit, each unit in the unit including a capacitor and a stacked switch. The capacitor and stacked switch of each unit in the unit are interconnected with the phase switch.

[0009] Additional features and advantages of the disclosed embodiments will be partially described in the following description, and in part will become apparent from the description, or can be understood through the practice of the embodiments. The features and advantages of the disclosed embodiments can be realized and obtained through the elements and combinations set forth in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments and various aspects of the present disclosure are shown in the following detailed description and accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0011] Figure 1 is a diagram illustrating an exemplary power converter according to some embodiments of the present disclosure.

[0012] FIG. 2A to FIG. 2B is a diagram illustrating an exemplary switched capacitor circuit according to some embodiments of the present disclosure.

[0013] FIG. 3A to FIG. 3D is a diagram showing an exemplary structure according to some embodiments of the present disclosure.

[0014] FIG. 4A to FIG. 4C is a diagram illustrating an exemplary passive device layer according to some embodiments of the present disclosure.

[0015] Figure 4D is a diagram illustrating an exemplary active device layer with a molded interconnect substrate according to some embodiments of the present disclosure.

[0016] Figure 5 is a diagram illustrating an exemplary switched capacitor circuit according to some embodiments of the present disclosure.

[0017] Fig. 6A is a diagram showing an exemplary structure according to some embodiments of the present disclosure.

[0018] Figure 6B is a diagram showing an exemplary substructure according to some embodiments of the present disclosure.

[0019] Figure 7is a diagram showing an exemplary structure according to some embodiments of the present disclosure.

[0020] Fig. 8A and Figure 8B are diagrams respectively illustrating exemplary units according to some embodiments of the present disclosure.

[0021] Fig. 9 Some embodiments according to the present disclosure are shown in Fig. 8A FIG. 1 is a diagram of an exemplary structure of a unit.

[0022] Fig.10 is a diagram illustrating another exemplary unit according to some embodiments of the present disclosure.

[0023] Fig.11A A cross-sectional view of an exemplary portion of an LC network according to some embodiments of the present disclosure is shown.

[0024] Fig. 11B A cross-sectional view of an exemplary portion of another LC network is shown, according to some embodiments of the present disclosure.

[0025] Fig.12 is a diagram illustrating an exemplary power converter according to some embodiments of the present disclosure.

[0026] Fig.13 is a diagram illustrating an exemplary power converter package according to some embodiments of the present disclosure.

[0027] Fig.14 is a flow chart of a method of manufacturing a switched capacitor circuit according to some embodiments of the present disclosure.

[0028] Fig.15 is a flow chart of another method of manufacturing a switched capacitor circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] The following disclosure provides many different exemplary embodiments or examples for realizing the different features of the provided subject matter. Specific simplified examples of components and arrangements are described below to illustrate the present disclosure. Of course, these are merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0030] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any term discussed herein) is merely illustrative and in no way limits the scope and meaning of the disclosure or any exemplified term. Likewise, the disclosure is not limited to the various embodiments given in this specification.

[0031] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0032] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "above," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly accordingly.

[0033] In this document, the term “coupled” may also be referred to as “electrically coupled”, and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0034] Various embodiments of the present disclosure will be described with respect to a specific context, namely, implementation in a charge pump circuit. As used in the present disclosure, the term "charge pump" refers to a switched capacitor network configured to convert an input voltage to an output voltage. Examples of such charge pumps include cascade multiplier, Dickson, ladder, series-parallel, Fibonacci, and doubler switched capacitor networks, all of which can be configured as multiphase or single-phase networks.

[0035] However, the concepts in the present disclosure may also be applied to other types of power converters. A power converter that converts a higher input voltage power supply to a lower output voltage level is generally referred to as a buck or decompression converter because the converter "decompresses" the input voltage. A power converter that converts a lower input voltage power supply to a higher output voltage level is generally referred to as a boost or boost converter because the converter "boosts" the input voltage. In addition, some power converters (generally referred to as "decompression-boost converters") may be configured to convert an input voltage power supply to an output voltage with a wide range, wherein the output voltage may be higher or lower than the input voltage. In various embodiments, the power converter may be bidirectional, being a boost converter or a buck converter depending on the way the power supply is connected to the converter. In some embodiments, an AC-DC power converter may be constructed according to a DC-DC power converter by, for example, the following operations: first, the AC input voltage is rectified to a DC voltage, and then the DC voltage is applied to the DC-DC power converter.

[0036] High-density integrated switched capacitor power converters may be desirable in applications including, but not limited to, data centers or portable electronic devices such as tablets, cell phones or handheld computers and IoT (Internet of Things) devices. In particular, modern high-performance microprocessors may include billions of transistors that switch at several gigahertz and / or consume hundreds of amperes of current at relatively low voltages (e.g., less than 1.0V in some cases). In addition, as computing performance increases, the power consumption characteristics of modern microprocessors are also growing, leading to challenges for onboard point-of-load (PoL) type converters and / or data center power transmission facilities. PoL-type converters with high efficiency, high power density, and high bandwidth may be required to support the transmission of hundreds of amperes of current (e.g., greater than 50.0A in some cases) at relatively low voltages (e.g., less than 1.0V). Such PoL-type converters may operate at relatively high voltage conversion ratios (e.g., greater than 10:1) to support current and / or future high-performance microprocessors. In addition, due to increased server power consumption, the data center industry may be experiencing a transition from a 12V bus architecture to a 48V bus, which may allow for improved overall efficiency and / or lower costs. For example, transmitting power at 48V can also leverage the existing 48V telecom power ecosystem. A power converter that can provide a lower voltage output (e.g., less than 1.0V) regulated with a relatively high bandwidth while drawing energy from a relatively high wide range input voltage (e.g., between 40.0V and 60.0V) may be advantageous for supporting high performance microprocessors and / or for supporting telecom loads. The size, cost, and / or performance advantages provided via integration make it desirable to design modular and / or miniaturized dc-dc converters that can be relatively easily scaled in size and / or capacity for use in a variety of applications with different voltage and / or current needs.

[0037] Reference Figure 1 . Figure 1 is a diagram illustrating an exemplary power converter 100 according to some embodiments of the present disclosure. Figure 1 As shown, the power converter 100 may include a device 110a that provides a power module. As used herein, a power module may refer to a physical unit or device that contains power and electronic components of a power converter circuit. The device 110a includes a switched capacitor (SC) circuit 112 (also known as a charge pump circuit) and a controller circuit 114 configured to control the operation of the switched capacitor circuit 112. Specifically, the controller circuit 114 may include control circuit systems, timing circuit systems, protection circuit systems, and gate drivers, among other components, that are configured to operate switches, which in turn may change the electrical configuration of the capacitors of the switched capacitor circuit 112 between a first mode / state or a second mode / state.

[0038] exist Figure 1 In an embodiment, the power converter 100 is configured to receive energy from an input voltage source 102 at an input voltage V1 and deliver the energy to an output load 104 at an output voltage V2. In some embodiments, the input voltage V1 may be higher than the output voltage V2. The switched capacitor circuit 112 is configured to convert the input voltage V1 to an output voltage V2. In some embodiments, a plurality of power modules may be arranged in parallel in the power converter 100 to achieve a higher rated power based on low-cost and low-rated devices. Therefore, the modular design also provides flexibility and scalability of the power conversion circuit to meet different requirements for power supply systems in various applications.

[0039] In various embodiments, the controller circuit 114 in the device 110a can be an internal master controller or a slave controller configured to communicate with a master controller in the power system. In some other embodiments, the switch capacitor circuit 112 in the device 110a can also be controlled by an external master controller coupled to the device 110a. The controller circuit 114 can be manufactured on a semiconductor substrate such as silicon, gallium nitride (GaN), silicon on insulator (SOI), silicon on sapphire (SOS), silicon on glass (SOG), silicon on quartz (SOQ) and other substrates using semiconductor processing technology compatible with complementary metal oxide semiconductor (CMOS) manufacturing. The controller circuit 114 can be physically integrated with the switches in the switch capacitor circuit 112 on the same substrate (e.g., on-chip configuration) or as an off-chip component configured to operate the switches in the switch capacitor circuit 112.

[0040] like Figure 1 As shown, in some embodiments, the input terminals V1p and V1n are connected to the input voltage source 102 to receive the input voltage V1, and the output terminals V2p and V2n are connected to the output load 104 to output the output voltage V2. In addition, some input terminals of the controller circuit 114, such as the PG terminal for receiving the "power good" (PG) signal or the CLK terminal for receiving the clock signal, can be connected to other external circuit systems or devices to receive the PG signal and the clock signal. Similarly, the I / O pin IO of the device 110a in and IO out It may also be connected to a corresponding circuit system or device to facilitate circuit operation.In the present disclosure, the terms "node" and "terminal" may be used interchangeably.

[0041] Figure 2A is a diagram illustrating an exemplary switched capacitor circuit 200a according to some embodiments of the present disclosure. Figure 2AAs shown, in some embodiments, the switched capacitor circuit 200a can be a multi-phase switched capacitor circuit, such as a two-phase variant of a Dickson charge pump (also known as a cascade multiplier). Figure 2A The switched capacitor circuit 200a in FIG. Figure 1 The switched capacitor circuit 112 in the device 110a in FIG. 1 is a schematic diagram of a switching capacitor circuit 112 in FIG. 1 , but the present disclosure is not limited thereto. It should be understood that in various embodiments, the switched capacitor circuit may also be a single-phase or multi-phase circuit and may be designed based on a desired conversion ratio. Figure 2A In the embodiment of the present invention, a conversion ratio of 4:1 can be obtained. Generally, in the Dickson topology, different conversion ratios V1 / V2 (e.g., a conversion ratio of 3:1, a conversion ratio of 5:1, etc.) can be obtained by using different numbers of capacitors and different numbers of switches. As the size of the desired conversion ratio increases, the number of capacitors and switches used in the power converter may increase.

[0042] exist Figure 2A In an embodiment, the switched capacitor circuit 200a includes a stack switch 210 for a first phase, a stack switch 220 for a second phase, a phase switch 230 shared by two phases, a first capacitor group 240 including first capacitors C1A, C2A and C3A associated with the first phase and connected to the stack switch 210, and a second capacitor group 250 including second capacitors C1B, C2B and C3B associated with the second phase and connected to the stack switch 220. The stack switch 210 associated with the first phase includes switches S1A, S2A, S3A and S4A. The stack switch 220 associated with the second phase includes switches S1B, S2B, S3B and S4B. The phase switch 230 includes switches S5, S6, S7 and S8. Therefore, the switched capacitor circuit 200a provides the following switching network, which causes a transition between a first state and a second state depending on which of these switches are open and which are closed. The first switch configuration causes the switched capacitor network to transition from the first state to the second state. The second switch configuration transitions the switched capacitor network from the second state to the first state. As a result of the switches switching the switched capacitor network between these states, capacitors 240 and 250 are charged or discharged in a charge pump cycle to complete power conversion and transfer power from the source to the load.

[0043] exist Figure 2AIn the design shown in , the switching network includes two switch chains, i.e., switches connected in series. In particular, stacked switches S1A, S2A, S3A, and S4A form one switch chain associated with the first phase, while stacked switches S1B, S2B, S3B, and S4B form another switch chain associated with the second phase. Stacked switches S1A, S2A, S3A, and S4A are coupled to the positive terminals of first capacitors C1A, C2A, and C3A associated with the first phase, respectively, via corresponding dc nodes. Similarly, stacked switches S1B, S2B, S3B, and S4B are coupled to the positive terminals of second capacitors C1B, C2B, and C3B associated with the second phase, respectively, via corresponding dc nodes.

[0044] Phase switches S5 and S6 are connected to negative terminals of the first capacitor C2A and the second capacitors C1B and C3B via the first phase node P1, and phase switches S7 and S8 are connected to negative terminals of the first capacitors C1A and C3A and the second capacitor C2B via the second phase node P2. In other words, the first phase node P1 is coupled to the negative terminals of the first subset of the first capacitors (e.g., capacitor C2A) and the first subset of the second capacitors (e.g., capacitors C1B and C3B), and the second phase node P2 is coupled to the negative terminals of the second subset of the first capacitors (e.g., capacitors C1A and C3A) and the second subset of the second capacitors (e.g., capacitor C2B).

[0045] During operation, switches S1A, S2B, S3A, S4B, S6 and S7 (in Figure 2A 1) and switches S1B, S2A, S3B, S4A, S5, and S8 (in Figure 2A In the embodiment of the present invention, the first state is characterized in that the first state is characterized in that the first state is characterized in that the first state is characterized in that the second ...

[0046] Figure 2Bis a diagram illustrating another exemplary switched capacitor circuit 200b according to some embodiments of the present disclosure. Figure 2B As shown, in some embodiments, the switched capacitor circuit 200b may also include a first inductor group 260 associated with the first phase and connected between the corresponding capacitors C1A, C2A and C3A and the phase switch 230, including first inductors L1A, L2A and L3A, and a second inductor group 270 associated with the second phase and connected between the corresponding capacitors C1B, C2B and C3B and the phase switch 230, including second inductors L1B, L2B and L3B.

[0047] like Figure 2B As shown, various circuit topologies can be used in the present disclosure to form different types of power converters, such as hybrid converters, resonant switched capacitor converters, or multi-level power converters including transistors, capacitors, and one or more inductors as energy storage elements, or converters having LC filters coupled to a switched capacitor network to facilitate adiabatic charging or discharging. In particular, hybrid converters such as multi-level power converters or series capacitor step-down converters also include switched capacitor circuits combined with different topologies.

[0048] Figure 3A is a diagram showing an exemplary structure 300a according to some embodiments of the present disclosure. The structure 300a may be used to implement Figure 2A The switched capacitor circuit 200a shown in FIG. Figure 3A As shown, a plurality of layers 310 to 350 are stacked vertically to each other in the structure 300a, i.e., along the z direction perpendicular to the substrate. In particular, the structure 300a includes active device layers 310, 330, and 350 and passive device layers 320 and 340. The stacking configuration may include alternating active device layers 310, 330, and 350 and passive device layers 320 and 340 stacking, but the present disclosure is not limited thereto.

[0049] In some embodiments, the active device layers 310, 330, and 350 may include switching elements (eg, Figure 2A The stacked switches 210, 220, and 230 may be implemented by field effect transistors, bipolar junction transistors, diodes, or other electrical devices. In some embodiments, one or more of the active device layers 310, 330, and 350 may also include a control circuit system (e.g., Figure 1In some embodiments, the passive device layers 320 and 340 may include passive devices including capacitors (e.g., Figure 2A The substrate may include, but is not limited to, glass, quartz, silicon, SOI, SOS, SOG, SOQ, ceramic (aluminum oxide, aluminum nitride, sapphire) or composite materials and other substrate materials.

[0050] In structure 300a, passive device layer 320 is disposed between active device layer 310 and active device layer 330. Specifically, passive device layer 320 is stacked above active device layer 310, which may be a bottom layer. Active device layer 330 is stacked above passive device layer 320. In some embodiments, active device layer 310 includes a first switch (e.g., Figure 2A The passive device layer 320 includes a first capacitor (eg, Figure 2A The active device layer 330 includes a second switch (eg, a capacitor 240 associated with the first phase). Figure 2A The stack switch 210 in the active device layer 310 and the phase switch 230 in the active device layer 330 may be interconnected with the capacitor 240 in the passive device layer 320 by providing conductive features (e.g., contacts) to form a phase switch 230 shared by the first phase and the second phase. Figure 2A The switched capacitor circuit for the first phase is shown in FIG. Figure 2A As illustrated in FIG. 1 , the switched capacitor circuit transitions between at least two states in response to switching of the stack switch 210 and the phase switch 230 .

[0051] Similarly, the passive device layer 340 is disposed between the active device layer 330 and the active device layer 350 to form Figure 2A , for the second phase. Thus, phase switch 230 in active device layer 330 may be shared by two phases and interconnected with both capacitors 240 and 250. Specifically, passive device layer 340 is stacked above active device layer 330, and active device layer 350, which may be the top layer, is stacked above passive device layer 340. As used herein, a "bottom" layer is the layer closest to the substrate that provides the electrical interface, and a "top" layer is the layer farthest from the substrate.

[0052] The active device layer 350 includes a third switch (eg, Figure 2A The passive device layer 340 includes a second capacitor (eg, Figure 2AThe stack switch 220 in the active device layer 350 and the phase switch 230 in the active device layer 330 may be interconnected with the capacitor 250 in the passive device layer 340 by providing conductive features (e.g., contacts) to form Figure 2A The switched capacitor circuit for the second phase is shown in FIG.

[0053] Thus, structure 300a can form a multi-phase switched capacitor circuit (eg, Figure 2A A two-phase switched capacitor circuit 200a) is provided, which transitions between at least two states in response to switching of stacked switches 210, 220 and phase switches 230 arranged in different active device layers. In the present embodiment, the first switch in the bottom layer (e.g., active device layer 310) may be a stacked switch 210 associated with the first phase. The third switch in the top layer (e.g., active device layer 350) may be a stacked switch 220 associated with the second phase. The second switch in the middle layer (e.g., active device layer 330) is a phase switch 230 for both the first phase and the second phase to connect a first capacitor in a layer (e.g., passive device layer 320) stacked below the middle layer and a second capacitor in another layer (e.g., passive device layer 340) stacked above the middle layer to a shared phase node (e.g., Figure 2A phase nodes P1 and P2).

[0054] It should also be noted that in other embodiments, the structure 300a may have multiple passive device layers stacked on a single active device layer, or multiple active device layers stacked on a single passive device layer, or a stack including at least one of a passive device layer, an interconnect layer, and an active device layer. For example, the structure 300a may additionally include an interconnect layer to provide electrical connections between active device layers and passive device layers, or provide electrical connections between devices in an active device layer through metal lines.

[0055] Figure 3B is a diagram showing another exemplary structure 300b according to some embodiments of the present disclosure. Figure 3A Compared with the implementation method, Figure 3B As shown, the controller layer 360 of the circuit system including the controller circuit 114 can be set as the bottom layer, and the device layers 310 to 350 are stacked above the controller layer 360. The controller circuit 114 in the controller layer 360 can be coupled to the switches in the device layers 310, 330 and 350 through the contacts and through holes to provide control signals to control the stack switches and phase switches for each phase. Therefore, the structure 300b can be used to implement Figure 1 The device 110a shown in FIG.

[0056] Figure 3Cis a diagram showing another exemplary structure 300c according to some embodiments of the present disclosure. Figure 3A and Figure 3B Compared to the embodiment of FIG. 300 , in structure 300 c, device layers 310, 330, and 350 may each include a corresponding control circuit system for controlling the switching of stack switches or phase switches in the same device layer. In some embodiments, the control circuit systems in these device layers 310, 330, and 350 may communicate with each other through contacts and through holes, and jointly perform the operation of controller circuit 114 to provide control signals for each phase. Therefore, structure 300 c may also be used to implement Figure 1 The device 110a shown in FIG.

[0057] Figure 3D is a diagram showing another exemplary structure 300d according to some embodiments of the present disclosure. FIG. 3A to FIG. 3C Compared to the embodiment of the present invention, the structure 300d further includes additional passive device layers 370 and 380. The passive device layers 370 and 380 are respectively Figure 2B For example, the passive device layer 370 may be stacked between the passive device layer 320 and the active device layer 330, such that the inductor (eg, Figure 2B The first inductors L1A, L2A and L3A in the passive device layer 320 are connected to the corresponding capacitors (eg, Figure 2B between the first capacitors C1A, C2A and C3A in the active device layer 330 and the phase switch 230 in the active device layer 330.

[0058] Similarly, the passive device layer 380 may be stacked between the passive device layer 340 and the active device layer 330 such that the inductor (eg, Figure 2B The second inductors L1B, L2B, and L3B in the passive device layer 340 are connected to corresponding capacitors (eg, Figure 2B between the second capacitors C1B, C2B and C3B in the active device layer 330 and the phase switch 230 in the active device layer 330. Therefore, the structure 300d can also be used to implement Figure 2B It should be noted that in other alternative embodiments, the passive device layer 370 may be stacked between the passive device layer 320 and the active device layer 310 , and the passive device layer 380 may be stacked between the passive device layer 340 and the active device layer 350 . Figure 3D The structure 300d in FIG. 3 is an example and is not meant to limit the present disclosure.

[0059] In various implementations, the passive device layers 320 and 340 may be implemented in different ways to provide vertical capacitors connected between the phase switches and the stack switches, which may reduce routing distances and reduce parasitic inductance in the circuit. FIG. 4A to FIG. 4C 4 is a diagram showing exemplary passive device layers 400a, 400b and 400c according to some embodiments of the present disclosure. In some embodiments, the capacitors C1, C2, C3 to Cn embedded in each passive device layer 400a, 400b or 400c can be multilayer ceramic capacitors (MLCC). MLCC can store electrical energy in multiple ceramic layers with a high dielectric constant. For example, barium titanate (BaTiO3) can be selected as a dielectric. In the structure of MLCC, multiple metal electrodes and ceramic layers are alternately stacked in the capacitor. The internal electrodes are arranged in a forked finger pattern, where adjacent electrodes extend to opposite terminals and non-adjacent electrodes extend to the same terminal. At each terminal, a metallized coating (called an end terminal) applied to the outer face is electrically connected to the leaked electrode edge. MLCC has high capacitance, small size, low cost, high reliability and excellent high frequency characteristics, and can be widely used in different applications.

[0060] like Figure 4A As shown, in some embodiments, the positive terminals of capacitors C1, C2, C3 to Cn are coupled to corresponding contacts on a first surface 402 of the passive device layer 400a, and the negative terminals of capacitors C1, C2, C3 to Cn are coupled to corresponding contacts on a second surface 404 of the passive device layer 400a opposite to the first surface 402. The passive device layer 400a is stacked with a layer having stacked switches via the first surface 402, and with a layer having phase switches via the second surface 404. Therefore, the stacked switches can be coupled to the positive terminals of capacitors C1, C2, C3 to Cn via a dc node, and the phase switches can be coupled to the negative terminals of capacitors C1, C2, C3 to Cn via corresponding phase nodes. It should be understood that in different arrangements, the stacked switches can be stacked below or above the passive device layer 400a, so the first surface 402 can be a top surface or a bottom surface. In Figure 4A In the embodiment, the multilayer ceramic capacitors C1, C2, C3 to Cn are embedded in the substrate, wherein the long side of each multilayer ceramic capacitor C1, C2, C3 to Cn is substantially perpendicular to the top surface or the bottom surface of the passive device layer 400a, but the present disclosure is not limited thereto.

[0061] like Figure 4B As shown in the passive device layer 400b in FIG. 1 , the multilayer ceramic capacitors C1, C2, C3 to Cn may also be embedded in the substrate, wherein the long side of each multilayer ceramic capacitor C1, C2, C3 to Cn is substantially parallel to the top surface or the bottom surface of the passive device layer 400b. Figure 4A In the embodiment of the present invention, the positive terminals of the capacitors C1, C2, C3 to Cn are coupled to corresponding contacts on the first surface 402, and the negative terminals of the capacitors C1, C2, C3 to Cn are coupled to corresponding contacts on the second surface 404 opposite to the first surface 402. Figure 4C As shown in the passive device layer 400c in FIG. 1 , in some other embodiments, the multilayer ceramic capacitors C1, C2, C3 to Cn may also be vertically embedded in a molding compound material 406 (e.g., molded plastic or other electrical insulator material) to form the passive device layer 400c. It should be understood that the passive device layer may be implemented by other methods, and FIG. 4A to FIG. 4C The embodiments shown in FIG. 5 are examples only and are not meant to limit the present disclosure.

[0062] In some embodiments, Figure 3A The active device layers 310, 330, and 350 and / or the passive device layers 320 and 340 in the structure 300a may also be formed using a molded interconnect substrate (MIS), and one or more of the stacked switches 210, 220, the phase switch 230, and the capacitors 240, 250 may be embedded using the molded interconnect substrate (MIS). The molded interconnect substrate is a packaging technology built on a lead frame substrate that supports single die or multi-die configurations.

[0063] Figure 4D 4 is a diagram showing an exemplary active device layer 400d with a molded interconnect substrate according to some embodiments of the present disclosure. In the active device layer 400d, one or more IC dies 410 including active components (e.g., switches) are attached to a lead frame 420, wherein a thermal interface material 430 is disposed between the IC die 410 and the lead frame 420. Conductive pillars (e.g., Cu pillars) 440 and 450 are disposed to connect the IC die 410 or the lead frame 420 to a MIS 460 having a pre-molded structure. The MIS 460 may include one or more layers pre-configured with copper plating or interconnects to provide electrical connections.

[0064] Figure 5 is a diagram illustrating an exemplary switched capacitor circuit 500 according to some embodiments of the present disclosure. Figure 5 As shown, in some embodiments, the switched capacitor circuit 500 includes a plurality of single-phase switched capacitor networks 510, 520, and 530 connected in parallel for three different phases. Figure 5As shown, the switched capacitor network 510 can be implemented by a 4:1 Dickson switched capacitor network having switches S1A to S8A and capacitors C1A, C2A, and C3A. Similarly, the switched capacitor networks 520 and 530 can be implemented by a 4:1 Dickson switched capacitor network having corresponding switches S1B to S8B, S1C to S8C and capacitors C1B to C3B, C1C to C3C. The switches S1A to S8A, S1B to S8B, and S1C to S8C can be controlled in response to commands from a controller circuit 540 coupled to the switched capacitor networks 510, 520, and 530.

[0065] The switched capacitor network 510 includes a stack switch 512 and a phase switch 514 for a first phase, and a capacitor 516 associated with the first phase. The stack switch 512 associated with the first phase includes switches S1A, S2A, S3A, and S4A forming a switch chain. The phase switch 514 includes switches S5A, S6A, S7A, and S8A. Figure 5 In the design shown, stack switches S1A, S2A, S3A, and S4A are coupled to the positive terminals of capacitors C1A, C2A, and C3A, respectively, via corresponding dc nodes. Phase switches S5A and S6A are connected to the negative terminals of capacitors C1A and C3A via one phase node, while phase switches S7A and S8A are connected to the negative terminal of capacitor C2A via another phase node. Similarly, switched capacitor networks 520 and 530 include stack switches 522, 532 and phase switches 524, 534 for the second phase or the third phase, respectively, and capacitors 526, 536 associated with the second phase or the third phase. The arrangement of circuit components in switched capacitor networks 520 and 530 is similar to those in switched capacitor network 510, and therefore further details are omitted for the sake of brevity. Figure 2A Compared to the embodiment of FIG. 5 , in the switched capacitor circuit 500 , the switched capacitor networks 510 , 520 , and 530 do not share phase nodes and phase switches. The capacitors 516 , 526 , and 536 are coupled to the corresponding phase switch groups 514 , 524 , and 534 for different phases.

[0066] picture Figure 2A As in the embodiments of the present invention, in response to commands from the controller circuit 540, each of the switched capacitor networks 510, 520, and 530 causes a transition between a first state and a second state depending on which of the switches are open and which are closed. Thus, a charge pumping action is generated due to the switches causing the switched capacitor network to switch between these states. In some embodiments, the controller circuit 540 can output corresponding control signals to cause the switched capacitor networks 510, 520, and 530 to operate 120 degrees out of phase with each other. Figure 5The topology shown in can be further modified to combine N phases in parallel and run them 360 / N degrees out of phase with each other, N being any integer greater than 1. With such an arrangement, the switched capacitor circuit 500 provides reduced output voltage ripple and increased output power handling capability.

[0067] Fig. 6A is a diagram showing an exemplary structure 600 according to some embodiments of the present disclosure. The structure 600 may be used to implement Figure 5 The switched capacitor circuit 500 shown in FIG. Fig. 6A As shown, structure 600 includes substructures 610 , 620 , 630 , and 640 vertically stacked on top of one another along a z-direction perpendicular to a substrate.

[0068] Each of the substructures 610, 620, and 630 is associated with Figure 5 For example, substructure 610 corresponds to switched capacitor network 510 for a first phase, substructure 620 corresponds to switched capacitor network 520 for a second phase, and substructure 630 corresponds to switched capacitor network 530 for a third phase. Substructure 640, which may be a bottom layer below substructures 610, 620, and 630, includes controller circuit 540.

[0069] like Fig. 6A As shown, each of the substructures 610, 620, and 630 includes a first device layer (e.g., layer 612, 622, or 632) including a stacked switch (e.g., stacked switch 512, 522, or 524), a second device layer (e.g., layer 614, 624, or 634) including a phase switch (e.g., phase switch 514, 524, or 534), and a third device layer (e.g., layer 616, 626, or 636) including a capacitor (e.g., capacitor 516, 526, or 536) stacked between the first device layer and the second device layer. By providing contacts and vias in each layer of the structure 600, the substructures 610, 620, and 630 can be stacked on top of each other to couple the switched capacitor networks 510, 520, and 530 in parallel, thereby forming Figure 5 In addition, the controller circuit 540 in the bottom layer can be coupled to the switches in the substructures 610, 620 and 630 through these contacts and vias to provide control signals to control the stack switches and phase switches for each phase.

[0070] Figure 6B 6 is a diagram showing an exemplary substructure 610 according to some embodiments of the present disclosure. It should be understood that substructures 620 and 630 may also include Figure 6B The substructure 610 has the same or similar features. Figure 6B, passive device layer 616 is stacked above active device layer 614, and active device layer 612 is stacked above passive device layer 616. Substructure 610 provides bottom contact 611 on the bottom surface and top contact 615 on the top surface opposite to the bottom surface for electrical connection to other substructures stacked above or below substructure 610. One or more through holes 613 may be formed and extend through active device layer 612, passive device layer 616, and active device layer 614 in height. Figure 6B As shown, the through-holes 613 may be configured to connect corresponding bottom contacts 611 and top contacts 615 .

[0071] use Figure 3A or Fig. 6A The stacked structure shown in , can form a switched capacitor power converter in the following manner: its stacked switches, capacitors and phase switches are vertically stacked in different layers. Therefore, the horizontal surface area required for the power converter can be reduced. Figure 3A and Fig. 6A The structures 300a and 600 disclosed in the embodiment are applicable to various devices or systems, such as power converters used in modern data centers, but the present disclosure is not limited thereto. The disclosed embodiments can also be used in other power applications or scenarios where the package height is not critical.

[0072] Figure 7 is a diagram illustrating an exemplary structure 700 according to some embodiments of the present disclosure. The structure 700 may be used to implement a single-phase switched capacitor network. Figure 7 As shown, the structure 700 includes two unit groups 710 and 720 and a phase device unit 730. The units 710 and 720 are vertically stacked on each other along the z direction perpendicular to the substrate and above the phase device unit 730. Figure 7 As shown, each cell 710 or 720 includes a top contact on a top surface and a bottom contact on a bottom surface for connecting to a contact of another cell stacked above or below the cell.

[0073] Each of the units 710 and 720 includes at least one capacitor (e.g., one of the capacitors C1 to C5) and a first switch (e.g., one of the switches S1 to S5) coupled to the positive terminal of the corresponding capacitor. The first switches S1 to S5 in the stacked units 710 and 720 are coupled in series as stacked switches of a single-phase switched capacitor network. The phase device unit 730 includes second switches S6, S7, S8, and S9, which are phase switches of the single-phase switched capacitor network and are coupled to the negative terminals of the corresponding capacitors C1 to C5. By stacking the units 710 and 720 on the phase device unit 730, the capacitors C1 to C5 and the first switches S1 to S5 in each unit 710 or 720 are interconnected with the second switches S6, S7, S8, and S9 to form a single-phase switched capacitor network. Like the previous embodiment, Figure 7 The switched capacitor circuit shown in FIG. 7 may be configured to transition between at least two states in response to switching of the first switches S1 to S5 and the second switches S6 to S9 in each cell 710 or 720 .

[0074] In the structure 700, the cells 710 and 720 are alternately stacked to couple the capacitors C1 to C5 to the corresponding phase nodes 732 or 734. In particular, in each cell 710, the capacitor (e.g., capacitor C1, C3, or C5) is coupled to a first subset of second switches (e.g., switches S8 and S9) at a first phase node 732 of the switched capacitor circuit, and in each cell 720, the capacitor (e.g., capacitor C2 or C4) is coupled to a second subset of second switches (e.g., switches S6 and S7) at a second phase node 734 of the switched capacitor circuit.

[0075] Like the previous embodiment, in the switch chain including the first switches S1 to S5, the adjacent switches are in complementary states. In other words, during operation, in the first state, in response to a command from the controller circuit, the first switch in each unit 710 (e.g., switches S1, S3, and S5) can be closed, and the first switch in each unit 720 (e.g., switches S2 and S4) can be opened. In the second state after the first state, in response to a command from the controller circuit, the first switch in each unit 710 can be opened and the first switch in each unit 720 can be closed.

[0076] In some embodiments, each of the first switches S1 to S5 may be a field effect transistor having a source terminal and a drain terminal coupled to one of the top contacts and one of the bottom contacts, respectively. Each of the capacitors C1 to C5 is coupled between a source terminal of the corresponding field effect transistor and the first phase node 732 or the second phase node 734 of the switched capacitor circuit through corresponding contacts and / or vias in the cells 710 and 720.

[0077] Fig. 8A and Figure 8B are diagrams showing exemplary units 710 and 720, respectively, according to some embodiments of the present disclosure. Fig. 8A and Figure 8B As shown, each of the units 710 and 720 includes top contacts T1 to T5 on the top surface and bottom contacts B1 to B5 on the bottom surface. The top contacts T1, T2, T4, and T5 are coupled to the bottom contacts B1, B2, B4, and B5, respectively, to provide electrical connections between the stacked units 710 and 720.

[0078] In cells 710 and 720, the source terminal S of transistor 712 or 722 is coupled to bottom contact B3, and the drain terminal D of transistor 712 or 722 is coupled to top contact T3. Fig. 8A In the cell 710, the gate terminal G of the transistor 712 is coupled to the top contact T1 and the bottom contact B1. Figure 8B In the cell 720 in the switch chain, the gate terminal G of the transistor 722 is coupled to the top contact T2 and the bottom contact B2. Therefore, when the cells 710 and 720 are alternately stacked, the gate terminals of the transistor 712 in the cell 710 are electrically coupled to each other to receive the first control signal, and the gate terminals of the transistor 722 in the cell 720 are electrically coupled to each other to receive the second control signal. Therefore, adjacent switches in the switch chain can operate in complementary states.

[0079] for Fig. 8A In the cell 710 in the stack, capacitor 714 is coupled between the source terminal S of transistor 712 and node 716. Node 716 is coupled to top contact T5 and bottom contact B5, which are electrically coupled to a first phase node (e.g., Figure 7 On the other hand, for the phase node 732 in Figure 8B In the cell 720 in the stack, the capacitor 724 is coupled between the source terminal S of the transistor 722 and the node 726. The node 726 is coupled to the top contact T4 and the bottom contact B4, which are electrically coupled to the second phase node (e.g., Figure 7 Thus, when cells 710 and 720 are stacked alternately, capacitors 714 and 724 in adjacent cells are coupled to different subsets of phase switches, thereby forming Figure 7 The single-phase switched capacitor network shown in .

[0080] Fig. 9Some embodiments according to the present disclosure are shown in Fig. 8A FIG. 7 is a diagram of an exemplary structure of unit 710. Fig. 9 As shown, the top contacts T1 to T5 and the bottom contacts B1 to B5 can be placed at corresponding positions on opposite surfaces of the cell 710, so that the top contacts T1 to T5 can be connected to corresponding contacts of the adjacent cell 720 stacked above the cell 710, and the bottom contacts B1 to B5 can be connected to corresponding contacts of the adjacent cell 720 stacked below the cell 710. The transistors 712 and capacitors 714 within the cell 710 can be arranged to optimize the electrical connections between the components, the top contacts T1 to T5, and the bottom contacts B1 to B5. Similar structures can be applied to Figure 8B Unit 720 is not repeated herein for the sake of brevity.

[0081] Fig.10 is a diagram illustrating another exemplary unit 1000 according to some embodiments of the present disclosure. Fig.10 As shown, transistors 712 and 722 and capacitors 714 and 724 operating in complementary states may also be integrated into a single unit to form a switched capacitor network. Figure 7 The single-phase switched capacitor network shown in FIG. 1 can be formed by stacking one or more cells 1000 as an alternative to a pair of one cell 710 and one cell 720. Fig.10 , cell 1000 includes transistors 712 and 722 and capacitors 714 and 724. Fig. 8A and Figure 8B In an embodiment, capacitor 714 is coupled between source terminal S1 of transistor 712 and node 716 coupled to top contact T5 and bottom contact B5, and capacitor 724 is coupled between source terminal S2 of transistor 722 and node 726 coupled to top contact T4 and bottom contact B4.

[0082] Transistors 712 and 722 are coupled in series between top contact T3 and bottom contact B3. Specifically, drain terminal D1 of transistor 712 is coupled to top contact T3, drain terminal D2 of transistor 722 is coupled to source terminal S1 of transistor 712, and source terminal S2 of transistor 722 is coupled to bottom contact B3. Gate terminal G1 of transistor 712 is coupled to top contact T1 and bottom contact B1, while gate terminal G2 of transistor 722 is coupled to top contact T2 and bottom contact B2.

[0083] Note that although the cell 1000 includes two stacked switches (e.g., transistors 712 and 722) and two capacitors 714 and 724 in a single cell, the disclosure is not limited thereto. In other embodiments, a cell may include any number of stacked switches coupled in series and corresponding capacitors coupled to the stacked switches. In other words, in some embodiments, at least one of the stacked cells may include multiple capacitors and multiple stacked switches interconnected with phase switches to form a switched capacitor circuit.

[0084] exist Figures 7 to 10 In the embodiment of the present invention, by stacking a plurality of stackable units 710, 720 and / or 1000 above a phase device unit 730, a switched capacitor power converter whose electrical components are vertically stacked can be formed. Figure 2A 6D, the horizontal surface area required for the power converter can be reduced, which is desirable for various power applications or scenarios where package height is not critical. In addition, the conversion ratio of the switched capacitor network can be easily modified by stacking different numbers of units, which provides modularity and flexibility for the power converter design to meet different power requirements in different applications at a low cost.

[0085] It should be understood that the structures 300a to 300d, 600 and 700 in the present disclosure may also be modified and applied to other types of power converters having different implementations, arrangements and / or topologies. For example, the structures disclosed herein may form a resonant switched capacitor converter or a multi-level power converter including transistors, capacitors and one or more inductors as energy storage elements, or a converter having an LC filter coupled to a switched capacitor network to facilitate adiabatic charging or discharging.

[0086] In such an implementation, the capacitors and inductors can be placed in the same passive device layer, or in separate passive device layers. Figure 3A In some embodiments, the passive device layer 320 or 340 may also include one or more inductors coupled to one or more of the capacitors 240 or 250 in the same layer. Alternatively, as Figure 3D As shown, structure 300d may include one or more additional inductor layers vertically stacked adjacent to passive device layer 320 or 340, namely passive device layers 370 and 380. Passive device layers 370 and 380 include one or more inductors coupled to one or more of capacitors 240 or 250 in passive device layer 320 or 340.

[0087] Reference Fig.11A and Fig. 11B, which shows one or more additional inductor layers stacked vertically adjacent to a passive device layer including a capacitor. Fig.11A 1 shows a cross-sectional view of an exemplary portion of an LC network 1100a according to some embodiments of the present disclosure. Fig.11A As shown, the LC network 1100a may include a capacitor layer 1110 and an inductor layer 1120, wherein the contacts and / or vias are configured to achieve a series electrical connection of the inductor layer 1120 with the capacitor layer 1110. The LC network 1100a may be fabricated by bonding the bottom surface of the capacitor layer 1110 to the top surface of the inductor layer 1120. In some embodiments, the bonding may include a hybrid bonding such that metal-to-metal and oxide-to-oxide bonding is formed between the bonding surfaces of the capacitor layer 1110 and the inductor layer 1120.

[0088] Fig. 11B A cross-sectional view of an exemplary portion of another LC network 1100b is shown according to some embodiments of the present disclosure. Fig. 11B In the embodiment, the LC network 1100b may include two inductor layers 1120 and 1130, and a capacitor layer 650 coupled between the two inductor layers 1120 and 1130, wherein the contacts and / or through-holes are configured to achieve a series electrical connection. As an example, the LC network 1100b may be used in a resonant switched capacitor converter. It should be understood that Fig.11A and Fig. 11B The relative arrangement of inductor layers 1120 and 1130 and capacitor layer 1110 shown in is a non-limiting example, and other arrangements are possible. In various embodiments, the LC network may include one or more inductor layers, one or more capacitor layers, one or more vias, and electrical contact pads as desired.

[0089] Reference Fig.12 . Fig.12 is a diagram illustrating an exemplary power converter 1200 according to some embodiments of the present disclosure. Figure 1 Compared to the embodiment of the present invention, the power converter 1200 may include a plurality of devices 110a, 110b and 110c coupled to each other, and each device provides a power module. In a preferred embodiment, the power module may include one or more of the devices 110a, 110b and 110c. It should be noted that the number of devices 110a, 110b and 110c may vary in different embodiments, and Fig.12 are simplified examples and are not meant to limit the present disclosure. Fig.12In the embodiment, by using a plurality of power modules (e.g., including a plurality of devices 110a, 110b, and 110c) having input terminals V1p and V1n of a switched capacitor circuit connected together and output terminals V2p and V2n of a switched capacitor circuit connected together in the power converter 1200, the power converter 1200 can achieve a higher rated power based on low-cost and low-rated devices. Therefore, the modular design also provides flexibility and scalability of the power conversion circuit to meet different requirements for power supply systems in various applications.

[0090] In some embodiments, the devices 110a, 110b, and 110c may include corresponding switched capacitor circuits 112 and separate controller circuits 114, respectively, but the present disclosure is not limited thereto. In some embodiments, the switched capacitor circuits 112 in the devices 110a, 110b, and 110c may be controlled by an external master controller coupled to the devices 110a, 110b, and 110c. In some other embodiments, the power converter 1200 may include an internal master controller (e.g., the controller circuit 114 in the device 110a) and one or more slave controllers (e.g., the controller circuits 114 in the devices 110b and 110c) configured to communicate with the internal master controller. In addition, one or more power modules in the power converter 100 may support a power management bus (PMBUS) communication protocol, while the remaining power modules are "light" power modules with a simpler design that do not have PMBUS and / or telemetry circuits.

[0091] like Fig.12 As shown, in some embodiments, the input terminals V1p, V1n and the output terminals V2p, V2n of the switch capacitor circuit 112 in each device 110a, 110b and 110c are coupled in parallel. In addition, some input terminals of the controller circuit 114, such as the PG terminal or the CLK terminal, can also be coupled in parallel, so that the devices 110a, 110b and 110c receive the same PG signal and the same clock signal. Some other terminals, such as the I / O pins IO of the devices 110a, 110b and 110c, can also be coupled in parallel. in and IO out Can be coupled in series to facilitate circuit operation.

[0092] In various embodiments of the present disclosure, for applications where size of the circuit is critical, devices 110a, 110b, and 110c including charge pump circuits can be stacked vertically in a package to provide high power density for the power converter 1200. For example, a central processing unit (CPU) in a laptop computer or a data center can provide sufficient height margin (e.g., about 2 mm to 9 mm, or about 7 mm to 22 mm) to allow low profile charge pump power modules to be stacked vertically in the z-direction. Therefore, as the package height increases, the area occupied by the charge pump circuit on the horizontal surface (i.e., the xy plane) can be reduced, and the floor space is also saved accordingly.

[0093] Compared to the charge pump power module in the present embodiment, the step-down converter power module typically has a relatively high-profile inductor such as a wound inductor. In particular, the inductor is typically the largest and tallest component in a conventional module and is a bottleneck in reducing the module height in the z-direction. Due to the height of the large inductor, conventional step-down converters will not be stacked, and such vertically stacked step-down converter power modules will exceed the height limitation and are therefore undesirable for power supply applications for CPUs in laptop computers or data centers. On the other hand, utilizing the switched capacitor architecture in the present embodiment, the low-profile (e.g., approximately 1 mm) charge pump power module is suitable for stacking in various power supply applications.

[0094] Fig.13 1 is a diagram illustrating an exemplary power converter package 1300 according to some embodiments of the present disclosure. The power converter package 1300 includes multiple integrated circuit packages (eg, devices 110a, 110b, and 110c) stacked vertically to increase power density without increasing the overall package area. Fig.13 As shown, the device 110a at the bottom layer can be a bottom package, which provides a bottom bonding contact 1312a on one surface (e.g., the bottom surface) and a top bonding contact 1314a on another surface (e.g., the top surface) opposite to the surface having the bottom bonding contact 1312a. One or more through holes 1316a of the device 110a connect the corresponding bottom bonding contact 1312a and the corresponding top bonding contact 1314a.

[0095] Similarly, the device 110b at the middle layer may be a middle package that provides a bottom bonding contact 1312b on the bottom surface and a top bonding contact 1314b on the top surface opposite the bottom surface, wherein one or more through holes 1316b connect the corresponding bottom bonding contact 1312b and the corresponding top bonding contact 1314b. The device 110c at the top layer may be a top package that provides a bottom bonding contact 1312c on the bottom surface. Alternatively, Fig.13 In an embodiment, a bottom bonding contact on one surface of the package provides a connection to a substrate or an adjacent lower package stacked below the package, and a top bonding contact on the opposite surface provides a connection to an adjacent upper package stacked above the package.

[0096] Note that in some embodiments, the top package may be a stackable package or a non-stackable package. In other words, while the device 110c at the top layer may provide a top bonding contact on the top surface, in some other embodiments, the device 110c may only provide a bottom bonding contact 1312c. It should also be noted that in various embodiments, the orientation of the non-stackable package and the stackable package may vary in the power converter package 1300 depending on the application.

[0097] like Fig.13 As shown, devices 110a, 110b and 110c are stacked on each other by joints 1320a, 1320b and 1320c, which can be electrical joints (e.g., bumps), thermocompression joints or hybrid joints between two adjacent packages. In some embodiments, joints 1320a, 1320b and 1320c can include conductive bumps for conducting both heat signals and electrical signals and heat-conducting bumps that are only dedicated to heat transfer. In particular, joint 1320a is configured to join the bottom joint contact 1312a in the bottom layer to substrate such as main printed circuit board (PCB) 1310. Joints 1320b and 1320c are configured to join the top joint contact on the top surface of the package placed in a layer to the corresponding bottom joint contact on the bottom surface of another package placed in an adjacent layer. The bonding members 1320a, 1320b, and 1320c and the through holes 1316a and 1316b provide electrical connections between the stacked devices 110a, 110b, and 110c. Fig.13 The stacked devices 110a, 110b and 110c may form Fig.12 The power converter 1200 in FIG. 1 is a power converter 100 in which the switched capacitor circuits in different modules are electrically connected in parallel to each other.

[0098] As described above, one or more controller circuits configured to control the operation of the switched capacitor circuit may be disposed in devices 110a, 110b, and 110c. In some embodiments, the master controller circuit may be disposed in the bottom package (e.g., device 110a), and the slave controller circuit may be disposed in one or more intermediate packages (e.g., device 110b) or in the top package (e.g., device 110c). The slave controller circuit may be electrically connected to the master controller circuit disposed in the bottom package through the corresponding bottom bonding contacts 1312a to 1312c and top bonding contacts 1314a and 1314b of the integrated circuit package.

[0099] Fig.14 is a flow chart of a method 1400 of manufacturing a switched capacitor circuit according to some embodiments of the present disclosure. It should be understood that Fig.14 Additional operations may be performed before, during, and / or after the method 1400 depicted in the drawings, and some other processes may only be briefly described herein. The method 1400 may be performed to manufacture Figure 3A The structure 300a is used to manufacture an integrated circuit for power converter applications, such as Figure 1 The power converter 100 and Fig.12 The power converter 1200. The method 1400 includes operations 1410 to 1490.

[0100] In operation 1410, a first device layer (eg, Figure 3A In operation 1420, a third device layer (eg, Figure 3A In operation 1430, the first capacitor in the third device layer (eg, Figure 3A The capacitor 240 in the first device layer and the first switch in the first device layer (eg, Figure 3A The stacked switches 210 in the third device layer are interconnected. The bottom contact of the third device layer can be connected to the corresponding top contact of the first device layer to couple the positive terminal of the first capacitor to the corresponding first switch.

[0101] In operation 1440, a second device layer (eg, Figure 3A In operation 1450, a second switch (eg, Figure 3A The phase switch 230 in the second device layer is interconnected with the first capacitor. The bottom contact of the second device layer can be connected to the corresponding top contact of the third device layer to couple the negative terminal of the first capacitor to the corresponding second switch.

[0102] In operation 1460, a fifth device layer (eg, Figure 3A In operation 1470, a second capacitor (eg, Figure 3A The capacitor 250 in the fifth device layer is interconnected with the second switch. The bottom contact of the fifth device layer can be connected to the corresponding top contact of the second device layer to couple the negative terminal of the second capacitor to the corresponding second switch.

[0103] In operation 1480, a fourth device layer (eg, Figure 3A In operation 1490, a third switch (eg, Figure 3A The stack switch 220 in the fourth device layer is interconnected with the second capacitor. The bottom contact of the fourth device layer can be connected to the corresponding top contact of the fifth device layer to couple the positive terminal of the second capacitor to the corresponding third switch.

[0104] Optionally, in some embodiments, in operation 1420 or 1460, one or more inductor layers (eg, Fig.11A and Fig. 11B The inductor layer 1120 and / or 1130 in the embodiment may be adjacent to the passive device layer (eg, Fig.11A and Fig. 11B The capacitor layer 1110 in the passive device layer is vertically stacked. The inductor layer may include one or more inductors coupled to one or more first capacitors in the passive device layer to form an LC network.

[0105] As described above, in method 1400, the first device layer and the fifth device layer can be formed by vertically embedding a multilayer ceramic capacitor in a substrate, wherein one or more contacts are coupled to a positive terminal of the multilayer ceramic capacitor located on a first surface, and one or more contacts are coupled to a negative terminal of the multilayer ceramic capacitor located on a second surface opposite to the first surface. In some other embodiments, the first device layer and the fifth device layer can be formed by embedding a multilayer ceramic capacitor in a molding compound material. In some other embodiments, one or more of the active device layer or the passive device layer can be formed by embedding switches and / or capacitors using a molded interconnect substrate.

[0106] Through operations 1410 to 1490 discussed above, a structure having a plurality of layers vertically stacked on each other (eg, Figure 3A Thus, a switched capacitor power converter in which stacked switches, capacitors, and phase switches are vertically stacked in different layers can be formed, and the horizontal surface area required for the power converter can be reduced.

[0107] Fig.15 is a flow chart of another method 1500 of manufacturing a switched capacitor circuit according to some embodiments of the present disclosure. It should be understood that in Fig.15 Additional operations may be performed before, during, and / or after the method 1500 depicted in the drawings, and some other processes may only be briefly described herein. The method 1500 may be performed to manufacture Figure 7 The structure 700 is used to manufacture an integrated circuit for power converter applications, such as Figure 1 The power converter 100 and Fig.12 The power converter 1200 of FIG. 1500 includes operations 1510 and 1520 .

[0108] In operation 1510, a phase switch (eg, Figure 7 The phase device unit (for example, Figure 7 In operation 1520, a plurality of units (eg, Figure 7 710 and 720 in the embodiment of the present invention. Each of the cells includes a capacitor (e.g., one of capacitors C1 to C5) and a stack switch (e.g., one of switches S1 to S5). The capacitor and the stack switch in each cell are interconnected with the phase switch. In each cell, the capacitor is coupled between the corresponding bottom contact and the top contact, and the stack switch is coupled between the corresponding bottom contact and the top contact.

[0109] The process of stacking the cells in operation 1520 may include placing a bottom contact (eg, Fig. 8A and Figure 8B The bottom contacts B1 to B5 in the cell are connected to the contacts of another cell stacked below the cell, and the top contacts (e.g., Fig. 8A and Figure 8B The top contacts T1 to T5 in the cell are connected to the contacts of another cell stacked above the cell.

[0110] In some embodiments, in operation 1520, one or more units in a group (e.g., Figure 7 710) and one or more units in another group (e.g., Figure 7 In each unit 710, the capacitor is at the first phase node (e.g., Figure 7 A phase node 732 in the embodiment is coupled to a first subset of phase switches (eg, Figure 7 In each unit 720, the capacitor is connected to the second phase node of the switched capacitor circuit (e.g., Figure 7 A phase node 734 in the embodiment is coupled to a second subset of phase switches (eg, Figure 7 Switches S6 and S7 in FIG.

[0111] Through the operations 1510 and 1520 discussed above, a structure for implementing a switched capacitor circuit (eg, Figure 7 The structure 700 of FIG. 1500 is a schematic diagram of a power converter circuit structure, and thus a switched capacitor power converter whose electrical components are vertically stacked can be formed, which reduces the horizontal surface area required for the power converter. As described above, by applying method 1500 to manufacture a switched capacitor circuit, the conversion ratio of the switched capacitor network can be easily modified by stacking different numbers of units, which provides modularity and flexibility for power converter design to meet different power requirements in different applications at a low cost.

[0112] In summary, in various embodiments of the present disclosure, switches and capacitors can be stacked vertically in different ways to construct a single-phase or multi-phase switched capacitor network, which can be applied to various power conversion circuits such as charge pump circuits, resonant switched capacitor converter circuits, multi-level power converter circuits, etc., to provide increased power density per unit area. Therefore, the total area required for the power converter can be reduced, which is desirable for data center power transmission facilities and other power applications. It should be noted that the switched capacitor circuits and / or power converters in the present disclosure can be implemented using various topologies, depending on the desired voltage conversion ratio and the allowed switching voltage.

[0113] In the foregoing description, embodiments have been described with reference to many specific details that may vary with implementation. Certain adaptive changes and modifications may be made to the described embodiments. In view of the practice of the disclosure disclosed herein and the disclosure of this specification, other embodiments may be apparent to those skilled in the art. It is also expected that the sequence of steps shown in the figure is for illustrative purposes only and is not intended to be limited to any particular sequence of steps. Therefore, it will be appreciated by those skilled in the art that these steps may be performed in different orders when implementing the same method.

[0114] It should be understood that, for the sake of clarity, certain features of this specification described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features of this specification described in the context of a single embodiment may also be provided individually or in any suitable sub-combination or appropriately in any other described embodiment of this specification. Certain features described in the context of various embodiments are not considered essential features of these embodiments, unless the embodiment is inoperable without these elements.

[0115] The following terms may be used to further describe the embodiments:

[0116] 1. A device comprising:

[0117] a first device layer, the first device layer comprising a plurality of first switches;

[0118] a second device layer, the second device layer comprising a plurality of second switches; and

[0119] a third device layer disposed between the first device layer and the second device layer, the third device layer comprising a plurality of first capacitors,

[0120] wherein the plurality of first switches and the plurality of second switches are interconnected with the plurality of first capacitors to form a switched capacitor circuit; and

[0121] The switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches.

[0122] 2. The apparatus of clause 1, wherein the plurality of first switches are stacked switches coupled to positive terminals of the plurality of first capacitors via a plurality of dc nodes; and

[0123] The plurality of second switches are phase switches coupled to negative terminals of the plurality of first capacitors via the first phase node or the second phase node.

[0124] 3. The apparatus of clause 2, wherein the first phase node is coupled to negative terminals of a first subset of the plurality of first capacitors, and the second phase node is coupled to negative terminals of a second subset of the plurality of first capacitors.

[0125] 4. The apparatus according to any one of clauses 1 to 3, further comprising:

[0126] a fourth device layer, the fourth device layer comprising a plurality of third switches; and

[0127] a fifth device layer disposed between the second device layer and the fourth device layer, the fifth device layer comprising a plurality of second capacitors,

[0128] wherein the switched capacitor circuit is a multi-phase switched capacitor circuit;

[0129] wherein the plurality of second switches are phase switches for a first phase and a second phase to connect the plurality of first capacitors and the plurality of second capacitors to a shared phase node of the switched capacitor circuit;

[0130] wherein the plurality of first switches are stacked switches associated with the first phase; and

[0131] Wherein, the plurality of third switches are stacked switches associated with the second phase.

[0132] 5. A device according to any one of clauses 1 to 4, wherein the positive terminals of the plurality of first capacitors are coupled to corresponding contacts located on a first surface of the third device layer, and the negative terminals of the plurality of first capacitors are coupled to corresponding contacts located on a second surface of the third device layer opposite to the first surface.

[0133] 6. The device of any of clauses 1 to 5, wherein the first plurality of capacitors are multilayer ceramic capacitors.

[0134] 7. The apparatus of clause 6, wherein the multilayer ceramic capacitors are embedded in a substrate, a long side of each multilayer ceramic capacitor being substantially perpendicular to a top surface of the third device layer.

[0135] 8. The apparatus of clause 6, wherein the multilayer ceramic capacitors are embedded in a substrate, a long side of each multilayer ceramic capacitor being substantially parallel to a top surface of the third device layer.

[0136] 9. The device of clause 6, wherein the multilayer ceramic capacitor is vertically embedded in a molding compound material.

[0137] 10. The apparatus of any of clauses 1 to 9, wherein one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded using a molded interconnect substrate.

[0138] 11. The apparatus of any of clauses 1 to 10, wherein the third device layer further comprises an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter.

[0139] 12. The apparatus according to any one of clauses 1 to 11, further comprising:

[0140] An inductor layer is vertically stacked adjacent to the third device layer, the inductor layer including an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter.

[0141] 13. An apparatus according to any one of clauses 1 to 12, wherein the apparatus comprises a plurality of substructures stacked vertically on top of one another, each substructure being associated with a respective phase of the switched capacitor circuit and comprising the first device layer, the second device layer and the third device layer.

[0142] 14. The apparatus of clause 13, wherein the plurality of substructures form a multiphase switched capacitor circuit having n phases, wherein the n phases are 360 / n degrees out of phase with each other, n being any integer greater than 1.

[0143] 15. An apparatus comprising:

[0144] a plurality of cells, each cell comprising a capacitor and a first switch; and

[0145] a phase device unit, the phase device unit comprising a plurality of second switches, the plurality of units being stacked vertically above the phase device unit,

[0146] wherein the capacitor and the first switch in each unit are interconnected with the plurality of second switches to form a switched capacitor circuit; and

[0147] The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the plurality of second switches in each cell.

[0148] 16. An apparatus according to clause 15, wherein the plurality of cells comprises two cell groups stacked alternately vertically, wherein, in one cell group, the capacitor is coupled to a first subset of the plurality of second switches at a first phase node of the switch capacitor circuit, and in the other cell group, the capacitor is coupled to a second subset of the plurality of second switches at a second phase node of the switch capacitor circuit.

[0149] 17. The apparatus of clause 16, wherein during the first state of the switched capacitor circuit, each first switch in the one cell group is turned on and each first switch in the other cell group is turned off; and

[0150] Wherein, during the second state of the switched capacitor circuit, each first switch in the one cell group is turned off and each first switch in the other cell group is turned on.

[0151] 18. The apparatus of any one of clauses 15 to 17, wherein each unit comprises:

[0152] a top contact on a top surface of the cell, the top contact connected to a contact of another cell stacked above the cell; and

[0153] A bottom contact is located on the bottom surface of the cell, the bottom contact being connected to a contact of another cell stacked below the cell.

[0154] 19. An apparatus according to clause 18, wherein a first phase node of the switched capacitor circuit is electrically coupled to one of the top contacts and one of the bottom contacts, and a second phase node of the switched capacitor circuit is electrically coupled to another of the top contacts and another of the bottom contacts.

[0155] 20. The apparatus of clause 18 or clause 19, wherein each first switch of each cell comprises a field effect transistor having a source terminal and a drain terminal respectively coupled to one of the top contacts and one of the bottom contacts of the cell.

[0156] 21. The apparatus of clause 20, wherein, in each cell, the capacitor is coupled between a source terminal of the field effect transistor and one of a first phase node or a second phase node of the switched capacitor circuit.

[0157] 22. An apparatus according to any of clauses 15 to 21, wherein at least one of the cells comprises a plurality of first switches and a plurality of capacitors interconnected with the plurality of second switches to form the switched capacitor circuit.

[0158] 23. The apparatus of any of clauses 15 to 22, wherein at least one of the cells further comprises an inductor.

[0159] 24. A method of manufacturing a switched capacitor circuit, comprising:

[0160] providing a first device layer;

[0161] Disposing a third device layer on the first device layer;

[0162] interconnecting a plurality of first capacitors within the third device layer with a plurality of first switches within the first device layer;

[0163] disposing a second device layer on the third device layer; and

[0164] A second plurality of switches within the second device layer are interconnected with the first plurality of capacitors.

[0165] 25. The method according to clause 24, further comprising:

[0166] Disposing a fifth device layer on the second device layer;

[0167] interconnecting a plurality of second capacitors within the fifth device layer with the plurality of second switches;

[0168] disposing a fourth device layer on the fifth device layer; and

[0169] A plurality of third switches within the fourth device layer are interconnected with the plurality of second capacitors.

[0170] 26. The method according to clause 24 or clause 25, further comprising:

[0171] Connecting a bottom contact of the third device layer to a corresponding top contact of the first device layer to couple a positive terminal of a first capacitor of the plurality of first capacitors to a first switch of the plurality of first switches.

[0172] 27. The method according to any one of clauses 24 to 26, further comprising:

[0173] Connecting a bottom contact of the second device layer to a corresponding top contact of the third device layer to couple a negative terminal of a first capacitor of the plurality of first capacitors to a second switch of the plurality of second switches.

[0174] 28. The method according to any one of clauses 24 to 27, further comprising:

[0175] vertically embedding a multilayer ceramic capacitor in the substrate to form the third device layer;

[0176] wherein one or more contacts are coupled to a positive terminal of the multilayer ceramic capacitor located on the first surface of the third device layer; and

[0177] Wherein, one or more contacts are coupled to a negative terminal of the multilayer ceramic capacitor located on a second surface of the third device layer opposite to the first surface.

[0178] 29. The method according to any one of clauses 24 to 27, further comprising:

[0179] A multilayer ceramic capacitor is embedded in a molding compound material to form the third device layer.

[0180] 30. The method according to any one of clauses 24 to 29, further comprising:

[0181] One or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded using a molded interconnect substrate.

[0182] 31. The method according to any one of clauses 24 to 30, further comprising:

[0183] An inductor layer is vertically stacked adjacent to the third device layer, the inductor layer including an inductor coupled to one or more first capacitors of the plurality of first capacitors.

[0184] 32. A method of manufacturing a switched capacitor circuit, comprising:

[0185] providing a phase device unit comprising a plurality of phase switches of a switched capacitor circuit; and

[0186] vertically stacking a plurality of cells above the phase device cell, each of the cells comprising a capacitor and a stack switch;

[0187] The capacitor and the stack switch in each of the plurality of units are interconnected with the plurality of phase switches.

[0188] 33. The method of clause 32, wherein stacking the plurality of units comprises:

[0189] One or more cells in one group and one or more cells in another group are vertically stacked, wherein, in each cell in the one group, the capacitor is coupled to a first subset of the plurality of phase switches at a first phase node of the switch capacitor circuit, and in each cell in the other group, the capacitor is coupled to a second subset of the plurality of phase switches at a second phase node of the switch capacitor circuit.

[0190] 34. The method of clause 32 or clause 33, wherein stacking the plurality of units comprises:

[0191] In each cell, connecting a bottom contact located on a bottom surface of the cell to a contact of another cell stacked below the cell; and

[0192] In each cell, a top contact located on the top surface of the cell is connected to a contact of another cell stacked above the cell.

[0193] 35. The method of clause 34, wherein, in each cell, the capacitor is coupled between a respective bottom contact and a top contact.

[0194] 36. The method of clause 34 or clause 35, wherein, in each unit, the stack switch is coupled between respective bottom and top contacts.

[0195] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A device comprising: a first device layer, the first device layer comprising a plurality of first switches; a second device layer, the second device layer comprising a plurality of second switches; as well as a third device layer disposed between the first device layer and the second device layer, the third device layer comprising a plurality of first capacitors, wherein the plurality of first switches and the plurality of second switches are interconnected with the plurality of first capacitors to form a switched capacitor circuit; and The switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches.

2. The device according to claim 1, wherein: The plurality of first switches are stacked switches coupled to positive terminals of the plurality of first capacitors via a plurality of dc nodes; and The plurality of second switches are phase switches coupled to negative terminals of the plurality of first capacitors via the first phase node or the second phase node.

3. The device according to claim 2, wherein: The first phase node is coupled to negative terminals of a first subset of the plurality of first capacitors, and the second phase node is coupled to negative terminals of a second subset of the plurality of first capacitors.

4. The device according to any one of claims 1 to 3, further comprising: a fourth device layer, the fourth device layer comprising a plurality of third switches; as well as a fifth device layer disposed between the second device layer and the fourth device layer, the fifth device layer comprising a plurality of second capacitors, wherein the switched capacitor circuit is a multi-phase switched capacitor circuit; wherein the plurality of second switches are phase switches for a first phase and a second phase to connect the plurality of first capacitors and the plurality of second capacitors to a shared phase node of the switched capacitor circuit; wherein the plurality of first switches are stacked switches associated with the first phase; and Wherein, the plurality of third switches are stacked switches associated with the second phase.

5. The device according to any one of claims 1 to 4, wherein: Positive terminals of the plurality of first capacitors are coupled to corresponding contacts on a first surface of the third device layer, and negative terminals of the plurality of first capacitors are coupled to corresponding contacts on a second surface of the third device layer opposite the first surface.

6. The device according to any one of claims 1 to 5, wherein: The plurality of first capacitors are multilayer ceramic capacitors.

7. The device according to claim 6, wherein: The multilayer ceramic capacitors are embedded in the substrate, and a long side of each multilayer ceramic capacitor is substantially perpendicular to a top surface of the third device layer.

8. The device according to claim 6, wherein: The multilayer ceramic capacitors are embedded in the substrate, and a long side of each multilayer ceramic capacitor is substantially parallel to a top surface of the third device layer.

9. The device according to claim 6, wherein: The multilayer ceramic capacitor is vertically embedded in a molding compound material.

10. The device according to any one of claims 1 to 9, wherein: One or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded using a molded interconnect substrate.

11. The device according to any one of claims 1 to 10, wherein: The third device layer also includes an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter.

12. The device according to any one of claims 1 to 11, further comprising: An inductor layer is vertically stacked adjacent to the third device layer, the inductor layer including an inductor coupled to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multi-level converter.

13. The device according to any one of claims 1 to 12, wherein: The apparatus includes a plurality of substructures stacked vertically on top of one another, each substructure being associated with a respective phase of the switched capacitor circuit and including the first device layer, the second device layer, and the third device layer.

14. The device according to claim 13, wherein: The plurality of substructures form a multi-phase switched capacitor circuit having n phases that are 360 / n degrees out of phase with each other, where n is any integer greater than 1.

15. An apparatus comprising: a plurality of units, each unit comprising a capacitor and a first switch; as well as a phase device unit, the phase device unit comprising a plurality of second switches, the plurality of units being vertically stacked above the phase device unit, wherein the capacitor and the first switch in each unit are interconnected with the plurality of second switches to form a switched capacitor circuit; and The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the plurality of second switches in each cell.

16. The device according to claim 15, wherein: The plurality of cells include two cell groups stacked alternately vertically, wherein in one cell group, the capacitor is coupled to a first subset of the plurality of second switches at a first phase node of the switch capacitor circuit, and in another cell group, the capacitor is coupled to a second subset of the plurality of second switches at a second phase node of the switch capacitor circuit.

17. The device according to claim 16, wherein: During a first state of the switched capacitor circuit, each first switch in the one cell group is turned on and each first switch in the other cell group is turned off; and Wherein, during the second state of the switched capacitor circuit, each first switch in the one cell group is turned off and each first switch in the other cell group is turned on.

18. The device according to any one of claims 15 to 17, wherein: Each unit includes: a top contact on a top surface of the cell, the top contact connected to a contact of another cell stacked above the cell; and A bottom contact is located on the bottom surface of the cell, the bottom contact being connected to a contact of another cell stacked below the cell.

19. The device according to claim 18, wherein: A first phase node of the switched capacitor circuit is electrically coupled to one of the top contacts and one of the bottom contacts, and a second phase node of the switched capacitor circuit is electrically coupled to the other of the top contacts and the other of the bottom contacts.

20. The apparatus of claim 18 or claim 19, wherein: Each first switch of each cell comprises a field effect transistor having a source terminal and a drain terminal respectively coupled to one of the top contacts and one of the bottom contacts of the cell.

21. The device according to claim 20, wherein: In each cell, the capacitor is coupled between a source terminal of the field effect transistor and one of a first phase node or a second phase node of the switched capacitor circuit.

22. The device according to any one of claims 15 to 21, wherein At least one of the cells includes a plurality of capacitors and a plurality of first switches interconnected with the plurality of second switches to form the switched capacitor circuit.

23. The device according to any one of claims 15 to 22, wherein: At least one of the cells further comprises an inductor.

24. A method of manufacturing a switched capacitor circuit, comprising: providing a first device layer; Disposing a third device layer on the first device layer; interconnecting a plurality of first capacitors within the third device layer with a plurality of first switches within the first device layer; Disposing a second device layer on the third device layer; as well as A second plurality of switches within the second device layer are interconnected with the first plurality of capacitors.

25. The method according to claim 24, further comprising: Disposing a fifth device layer on the second device layer; interconnecting a plurality of second capacitors within the fifth device layer with the plurality of second switches; Disposing a fourth device layer on the fifth device layer; as well as A plurality of third switches within the fourth device layer are interconnected with the plurality of second capacitors.

26. The method of claim 24 or claim 25, further comprising: Connecting a bottom contact of the third device layer to a corresponding top contact of the first device layer to couple a positive terminal of a first capacitor of the plurality of first capacitors to a first switch of the plurality of first switches.

27. The method according to any one of claims 24 to 26, further comprising: Connecting a bottom contact of the second device layer to a corresponding top contact of the third device layer to couple a negative terminal of a first capacitor of the plurality of first capacitors to a second switch of the plurality of second switches.

28. The method according to any one of claims 24 to 27, further comprising: vertically embedding a multilayer ceramic capacitor in the substrate to form the third device layer; wherein one or more contacts are coupled to a positive terminal of the multilayer ceramic capacitor located on the first surface of the third device layer; and Wherein, one or more contacts are coupled to a negative terminal of the multilayer ceramic capacitor located on a second surface of the third device layer opposite to the first surface.

29. The method according to any one of claims 24 to 27, further comprising: A multilayer ceramic capacitor is embedded in a molding compound material to form the third device layer.

30. The method according to any one of claims 24 to 29, further comprising: One or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded using a molded interconnect substrate.

31. The method according to any one of claims 24 to 30, further comprising: An inductor layer is vertically stacked adjacent to the third device layer, the inductor layer including an inductor coupled to one or more first capacitors of the plurality of first capacitors.

32. A method of manufacturing a switched capacitor circuit, comprising: providing a phase device unit, the phase device unit comprising a plurality of phase switches of a switched capacitor circuit; as well as vertically stacking a plurality of cells above the phase device cell, each of the cells comprising a capacitor and a stack switch; The capacitor and the stack switch in each of the plurality of units are interconnected with the plurality of phase switches.

33. The method of claim 32, wherein: Stacking the plurality of units comprises: One or more cells in one group and one or more cells in another group are vertically stacked, wherein, in each cell in the one group, the capacitor is coupled to a first subset of the plurality of phase switches at a first phase node of the switch capacitor circuit, and in each cell in the other group, the capacitor is coupled to a second subset of the plurality of phase switches at a second phase node of the switch capacitor circuit.

34. The method according to claim 32 or 33, wherein: Stacking the plurality of units comprises: In each cell, connecting a bottom contact located on a bottom surface of the cell to a contact of another cell stacked below the cell; and In each cell, a top contact located on the top surface of the cell is connected to a contact of another cell stacked above the cell.

35. The method of claim 34, wherein: In each cell, the capacitor is coupled between the corresponding bottom contact and top contact.

36. The method according to claim 34 or 35, wherein: In each unit, the stack switch is coupled between corresponding bottom and top contacts.

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