Packaging structure corresponding to wafer back power supply of chips of 2nm and below 2nm

Abstract

The invention discloses a packaging structure corresponding to wafer back power supply of a chip of 2nm and below 2nm. According to the scheme, an adapter plate is arranged on a substrate, and a first chip with the thickness of 2nm and below 2nm is inversely arranged on the basis of the adapter plate, so that smaller packaging height and smaller physical size are realized. Through the vertical metal blocks and the transverse metal blocks, the sectional area of current transmission is increased, the resistance is reduced, and the current transmission efficiency is improved. The vertical metal blocks and the transverse metal blocks serve as conductive channels and also serve as heat conduction paths, the heat conduction and dissipation capacity is effectively improved, and stable operation of the chip is guaranteed. Through the arrangement of the flip first chip, wafer back power supply is realized, the power supply path is shortened, the IR voltage drop is reduced, and the power supply efficiency is improved. And the vertical metal block is flush with the back surface of the first chip, so that the length of a current transmission path is reduced, the energy loss and electromagnetic interference are reduced, the electrical performance is improved, the uniformity of current distribution is ensured, and the resistance is further reduced.

Description

Technical Field

[0001] The present invention relates to a chip packaging structure, and in particular to a packaging structure corresponding to back-end power supply of chips with a nanometer (nm) or less. Background Art

[0002] With the rapid development of semiconductor technology, chip manufacturing processes are constantly moving towards finer scales, especially in the 2nm and below process era, the integration and performance of chips have been unprecedentedly improved. However, this technological advancement has also brought many challenges, especially in the field of chip packaging. Traditional packaging technology can no longer meet the stringent requirements of these high-end chips for power efficiency, thermal management, and physical size control.

[0003] For chips with a process of 2nm or below, the power consumption density increases significantly. Coupled with the surge in the number of transistors inside the chip, the resistance control of the power supply line becomes critical. High resistance not only leads to energy waste, but also may cause voltage drop, affecting the stability and performance of the chip. At the same time, high power consumption also means greater heat generation. How to effectively dissipate heat and prevent performance degradation or damage caused by chip overheating has become an urgent problem to be solved.

[0004] Therefore, it is particularly important to develop a packaging structure that can achieve low resistance, high current power supply, and efficient heat dissipation capabilities. Summary of the invention

[0005] The present invention overcomes the shortcomings of the above-mentioned technology and provides a packaging structure corresponding to the back-side power supply of 2nm and below chips.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A packaging structure corresponding to back-end power supply of chips of 2nm and below, comprising a substrate 1, wherein the substrate 1 is connected to an adapter plate 2 on its upper surface, a first chip 3 of 2nm and below thickness is flip-mounted on the upper surface of the adapter plate 2, a plurality of first metal contacts 31 are arranged on the back of the first chip 3, the substrate 1 is formed with a plurality of back-end power supply metal contacts 11 on its upper surface corresponding to the number of the first metal contacts 31, a first conductive material layer 41 is arranged on the surface of each first metal contact 31, each back-end power supply metal contact 11 is connected to a vertical metal block 5 via a second conductive material layer 42, and a third conductive material layer 43 is arranged on the upper surface of each vertical metal block 5; wherein the upper surface of each vertical metal block 5 is flush with the back of the first chip 3; the first conductive material layer 41 and the third conductive material layer 43 are conductively connected via a horizontal metal block 6.

[0008] Preferably, the substrate 1 is provided with a chip mounting area 110 and a back power supply area 120 arranged in a ring-shaped manner around the chip mounting area 110, the substrate 1 is provided with a plurality of first solder balls 7 protruding from the upper surface of the chip mounting area 110, the back power supply area 120 is connected to the vertical metal block 5 through the second conductive material layer 42, and the adapter board 2 is provided with a plurality of first solder points 21 correspondingly connected to the first solder balls 7 on its lower surface.

[0009] Preferably, the first solder joint 21 is protrudingly provided on the lower surface of the adapter plate 2 , and the back-side power supply metal contact 11 is formed in the back-side power supply area 120 and embedded in the top of the substrate 1 .

[0010] Preferably, a plurality of second metal contacts 32 are provided on the front side of the first chip 3 , and a second solder joint 22 embedded in the top and bonded to the second metal contacts 32 is provided on the upper surface of the adapter board 2 .

[0011] Preferably, a filling glue layer 8 for filling the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 is provided in the gap therebetween; and a plastic sealing layer 9 for encapsulating all components into one is provided on the upper surface of the substrate 1 .

[0012] Preferably, the vertical metal block 5 and the horizontal metal block 6 are both made of metal with high conductivity.

[0013] Preferably, the first conductive material layer 41 , the second conductive material layer 42 , and the third conductive material layer 43 are solder paste layers or conductive adhesive layers.

[0014] Preferably, the vertical metal block 5 is mounted on the substrate 1 through the second conductive material layer 42 in a SMT manner and is conductively connected to the back-side power supply metal contact 11 .

[0015] Preferably, the substrate 1 is such that the second metal contacts 32 and the second solder joints 22 are directly bonded and interconnected in a point-to-point manner.

[0016] Preferably, the substrate 1 is a FCBGA packaging substrate.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. This case achieves high integration between the chip and the substrate by setting an adapter plate on the substrate and flipping the first chip with a thickness of 2nm or less on this basis, which can achieve a smaller package height and smaller physical size. The cross-sectional area of ​​current transmission is increased by vertical metal blocks and horizontal metal blocks. According to the resistance formula, the resistance is directly reduced, the energy loss is reduced, and the current transmission efficiency is improved. At the same time, the cooperation with the multi-layer conductive material layer ensures the low resistance and high conductivity of the entire conductive path. The vertical metal blocks and horizontal metal blocks serve not only as conductive channels, but also as heat conduction paths, which effectively improve the heat conduction and dissipation capabilities and ensure the stable operation of the chip. The setting of flipping the first chip realizes back-of-the-chip power supply, shortens the power supply path, reduces IR voltage drop, and improves power supply efficiency. The setting of the vertical metal block flush with the back of the first chip reduces the length of the current transmission path, reduces energy loss and electromagnetic interference, improves electrical performance, ensures the uniformity of current distribution, and further reduces resistance.

[0019] 2. The substrate of this case is divided into a chip installation area and a back-end power supply area, which can reasonably layout the packaging structure and facilitate subsequent packaging. The back-end power supply area is arranged in a ring-shaped manner around the chip installation area. Such a ring-shaped power supply structure can provide power support for the chip more effectively, reduce the resistance and inductance in the power transmission path, thereby reducing voltage drop and electromagnetic interference, and improving the stability and efficiency of power supply. In addition, the ring-shaped arrangement allows a natural heat dissipation channel to be formed between the conductive network composed of vertical metal blocks and horizontal metal blocks, which helps to quickly remove the heat generated by the chip. The direct connection between the first solder ball 7 and the first solder joint 21 provides a short and direct current path, which helps to reduce inductance and resistance, thereby reducing energy loss and electromagnetic interference during signal transmission. Moreover, the contact area between the solder ball and the solder joint is relatively large, which helps to conduct and dissipate heat. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the cross-sectional structure of this case.

[0021] Figure 2 This is a schematic diagram of the top view of the structure of this case without the plastic sealing layer and the horizontal metal block.

[0022] Figure 3 This is a schematic diagram of the top view of the structure of this case without the plastic sealing layer. DETAILED DESCRIPTION

[0023] The features of the present invention and other related features are further described in detail below through embodiments to facilitate understanding by those skilled in the art:

[0024] like Figure 1 and Figure 3As shown, a packaging structure corresponding to back-end power supply of chips of 2nm and below, includes a substrate 1, an adapter plate 2 is connected to the upper surface of the substrate 1, a first chip 3 with a thickness of 2nm and below is flip-mounted on the upper surface of the adapter plate 2, a plurality of first metal contacts 31 are provided on the back of the first chip 3, and a plurality of back-end power supply metal contacts 11 are formed on the upper surface of the substrate 1 according to the number of the first metal contacts 31, a first conductive material layer 41 is provided on the surface of each first metal contact 31, each back-end power supply metal contact 11 is connected to a vertical metal block 5 through a second conductive material layer 42, and a third conductive material layer 43 is provided on the upper surface of each vertical metal block 5; wherein the upper surface of each vertical metal block 5 is flush with the back of the first chip 3; the first conductive material layer 41 and the third conductive material layer 43 are conductively connected via a horizontal metal block 6. In specific implementation, the vertical metal blocks and the horizontal metal blocks can be mounted in an SMT manner. In actual production, since the vertical metal blocks are stacked on the substrate in an SMT manner, vertical metal blocks of different heights can be selected according to the different heights of the stacked adapter board and the chip during production. This makes the manufacturing process flexible and allows suitable metal blocks to be selected for mounting according to different chip requirements. This can be applied to the production of packaging structures of various thicknesses.

[0025] As described above, this case provides a new type of high-end packaging structure specifically used in the most high-end chips on the market (corresponding to chips of 2nm and below). By setting an adapter plate 2 on the substrate 1, and flipping the first chip 3 with a thickness of 2nm and below on this basis, a high degree of integration between the chip and the substrate is achieved, which can achieve a smaller packaging height and a smaller physical size. At the same time, since the thickness of the first chip 3 is relatively small, the adapter plate can play a certain role in raising the height, so as to facilitate the subsequent connection to a metal contact on the back of the first chip 3 through a horizontal metal block and a vertical metal block. Since the thickness of the first chip is extremely thin at 2nm and below, the present application forms a conductive network that can power the back of the crystal through carefully designed vertical metal blocks 5, horizontal metal blocks 6, first conductive material layers, second conductive material layers, and third conductive material layers, which effectively improves the heat conduction and dissipation capabilities. Specifically, the design of the vertical metal block and the horizontal metal block can increase the cross-sectional area of ​​current transmission. According to the resistance formula R=ρL / A, where R is resistance, ρ is resistivity, L is length, and A is cross-sectional area, the increase in cross-sectional area A directly leads to a decrease in resistance R, thereby reducing the energy loss of current during transmission and improving transmission efficiency; and the vertical metal block / horizontal metal block not only serves as a conductive channel, but also as a heat conduction path, and cooperates with the first conductive material layer 41, the second conductive material layer 42, and the third conductive material layer 43 to ensure low resistance and high conductivity of the entire conductive path, which helps to reduce losses during power transmission and improve energy utilization efficiency. In addition, the first chip 3 with a thickness of 2nm or less is provided with a first metal contact 31 on the back, so that all electrodes do not need to be concentrated on the front, and a larger metal contact can be provided on the back, so that a larger-sized horizontal metal block can be provided to connect with it, and the larger horizontal metal block is connected in a manner to meet the requirements of low resistance and large current. Moreover, the first chip is connected to the adapter board in a flip-chip manner, so that the back side of the first chip 3 faces upward, and can cooperate with the above-mentioned conductive network to realize back-end power supply. Compared with traditional chips, on the one hand, back-end power supply can shorten the power supply path and reduce resistance, thereby significantly reducing IR voltage drop and improving power supply efficiency; on the other hand, the front side of the chip with back-end power supply can appropriately reduce the circuit density, which helps to improve the heat dissipation conditions and improve the reliability and stability of the chip.

[0026] Furthermore, the upper surface of each vertical metal block 5 is flush with the back of the first chip 3, so that the stacked first chip is equal in height to the vertical metal block 5, so that the vertical metal block and the back of the first chip can be directly connected horizontally through an ordinary horizontally extending square metal block, without the need for complex design, while ensuring heat transfer and conductivity, saving costs. Moreover, the flush design allows the horizontal metal block to fit tightly with the back of the first chip, reducing the length of the path that the current needs to bypass during transmission, which can reduce energy loss and electromagnetic interference during signal transmission and improve electrical performance; and the flush design allows the current to be more evenly distributed on the contact surface between the metal block and the chip, which can reduce current congestion during transmission, thereby reducing resistance.

[0027] like Figure 2 As shown, in a specific implementation, the substrate 1 is provided with a chip mounting area 110 and a back power supply area 120 arranged around the chip mounting area 110 in a ring-shaped manner, the substrate 1 is provided with a plurality of first solder balls 7 protruding from the upper surface of the chip mounting area 110, the back power supply area 120 is connected to the vertical metal block 5 through the second conductive material layer 42, and the adapter board 2 is provided with a plurality of first solder joints 21 correspondingly connected to the first solder balls 7 on its lower surface. A plurality of back power supply metal contacts 11 are provided in each side of the back power supply area 120.

[0028] As mentioned above, the substrate of this case is divided into a chip mounting area 110 and a back-end power supply area 120, which can reasonably layout the packaging structure and facilitate subsequent packaging. The back-end power supply area 120 is arranged around the chip mounting area 110 in a ring-shaped manner. Such a ring-shaped power supply structure can provide power support for the chip more effectively, reduce the resistance and inductance in the power transmission path, thereby reducing the voltage drop and electromagnetic interference, and improving the stability and efficiency of the power supply. In addition, the ring-shaped arrangement allows a natural heat dissipation channel to be formed between the conductive network composed of the vertical metal blocks and the horizontal metal blocks, which helps to quickly export the heat generated by the chip. The direct connection between the first solder ball 7 and the first solder joint 21 provides a short and direct current path, which helps to reduce inductance and resistance, thereby reducing energy loss and electromagnetic interference during signal transmission. Moreover, the contact area between the solder ball and the solder joint is relatively large, which helps to conduct and dissipate heat.

[0029] like Figure 2 and 3As shown, in a specific implementation, the first solder joint 21 is convexly arranged on the lower surface of the adapter plate 2, and the crystal back power supply metal contact 11 is formed in the crystal back power supply area 120 and embedded in the top of the substrate 1. In this way, the first solder joint 21 is convexly arranged on the lower surface of the adapter plate 2, so that the space on the substrate 1 is more efficiently utilized, which helps to improve the integration and density of the package. Moreover, the setting of the convexly arranged first solder joint 21 facilitates the transfer of heat generated by the first chip to the substrate 1, thereby improving the heat dissipation efficiency. The crystal back power supply metal contact 11 is embedded in the top of the substrate 1, and is not protruding from the top surface of the substrate, so that since the contact does not protrude, the top surface of the substrate can be more compactly arranged with a conductive material layer and a metal block, thereby further improving the integration and density of the entire package. Moreover, the design of the embedded contact makes the top surface of the substrate flatter, which is conducive to the mounting of heat dissipation components such as heat sinks or heat pipes, thereby improving the heat dissipation efficiency of the package.

[0030] like Figure 1 As shown, in a specific implementation, a plurality of second metal contacts 32 are provided on the front side of the first chip 3 , and a second solder joint 22 embedded in the top and connected to the second metal contacts 32 is provided on the upper surface of the adapter board 2 .

[0031] As described above, the second solder joint 22 is embedded in the top of the adapter board 2 and is closely connected to the second metal contact 32, which helps to reduce the contact resistance and improve the stability and reliability of the electrical connection. At the same time, since the second solder joint 22 is embedded in the adapter board, on the one hand, the influence of the external environment on the electrical connection is reduced, and on the other hand, the height of the upper surface of the adapter board 2 is not increased, which is conducive to improving the integration of the packaging structure of the present application.

[0032] like Figure 1 As shown, a filling glue layer 8 for filling the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 is provided. In this way, through the provision of the filling glue layer 8, on the one hand, after curing, the adapter plate 2 and the substrate 1 can be firmly bonded to enhance the connection strength between them; on the other hand, the filling glue layer 8 can have good thermal conductivity, so as to transfer the heat generated by the chip to the substrate 1, further improving the heat dissipation efficiency. Moreover, the filling glue layer 8 can fill the tiny gap between the adapter plate 2 and the substrate 1, reduce thermal resistance, and improve thermal conduction efficiency.

[0033] As a preferred embodiment, the vertical metal block 5 and the horizontal metal block 6 are both made of a metal with high conductivity. The metal with high conductivity is copper, aluminum or its alloy, preferably copper. In this way, the back conductive network of the present application has excellent conductive properties, can significantly reduce resistance, and improve current transmission efficiency.

[0034] like Figure 1As shown, the upper surface of the substrate 1 is provided with a plastic layer 9 for packaging all components into one. In this way, it is convenient to package all components into one, so as to provide insulation protection and moisture-proof effect to the internal components. In specific implementation, the plastic layer 9 is usually epoxy resin material.

[0035] As a preferred embodiment, the first conductive material layer 41, the second conductive material layer 42, and the third conductive material layer 43 are solder paste layers or conductive adhesive layers. Thus, solder paste layers or conductive adhesive layers are selected as the first conductive material layer 41, the second conductive material layer 42, and the third conductive material layer 43 to meet the requirements of conduction and heat dissipation, and both solder paste layers and conductive adhesive layers are commonly used conductive materials in the packaging process, so as to reduce the complexity and cost of the packaging process.

[0036] As a preferred embodiment, the vertical metal block 5 is mounted on the substrate 1 through the second conductive material layer 42 in an SMT manner and is conductively connected to the back power supply metal contact 11. In specific implementation, the back power supply metal contact 11 of the substrate 1 can be coated with solder paste first, and then the vertical metal block can be mounted on the solder paste by a chip mounter to achieve connection. In this way, according to the actual different heights of the first chip and the adapter plate stack, a suitable vertical metal block can be selected to ensure that the same height is maintained, which has good flexibility and can also ensure the stability of the packaging structure.

[0037] As a preferred embodiment, the substrate 1 is directly interconnected by bonding the second metal contact 32 and the second solder joint 22 in a point-to-point manner, that is, connected together in a hybrid bonding manner. In this way, the first chip and the adapter board are precisely aligned and directly pressed together to form a direct electrical contact, eliminating traditional intermediate media such as solder and other materials.

[0038] As a preferred embodiment, the substrate 1 is a FCBGA packaging substrate. In this way, the use of the FCBGA packaging substrate can realize the flip chip technology, that is, the chip is flipped upside down and attached to the substrate, so as to facilitate the subsequent realization of the back-side power supply of 2nm and below chips, without the need to use wires to connect the chip and the substrate, so as to achieve higher integration and higher density packaging.

[0039] As mentioned above, this case protects a packaging structure corresponding to the back-end power supply of 2nm and below chips. All technical solutions that are the same or similar to this case should be deemed to fall within the scope of protection of this case.

Claims

1. A packaging structure for back-side power supply of chips with a chip size of 2nm or less, comprising a substrate (1), characterized in that The substrate (1) is connected to an adapter plate (2) on its upper surface, a first chip (3) with a thickness of 2 nm or less is flip-mounted on the upper surface of the adapter plate (2), a plurality of first metal contacts (31) are provided on the back of the first chip (3), and a plurality of back-end power supply metal contacts (11) are formed on the upper surface of the substrate (1) according to the number of the first metal contacts (31), a first conductive material layer (41) is provided on the surface of each first metal contact (31), each back-end power supply metal contact (11) is connected to a vertical metal block (5) via a second conductive material layer (42), and a third conductive material layer (43) is provided on the upper surface of each vertical metal block (5); wherein the upper surface of each vertical metal block (5) is flush with the back of the first chip (3); and the first conductive material layer (41) and the third conductive material layer (43) are conductively connected via a horizontal metal block (6).

2. The packaging structure according to claim 1, characterized in that The substrate (1) is provided with a chip mounting area (110) and a back-end power supply area (120) arranged around the chip mounting area (110) in a ring-shaped manner; a plurality of first solder balls (7) are convexly provided on the upper surface of the chip mounting area (110); the back-end power supply area (120) is connected to the vertical metal block (5) via a second conductive material layer (42); and the adapter plate (2) is provided with a plurality of first solder points (21) correspondingly connected to the first solder balls (7) on its lower surface.

3. The packaging structure according to claim 2, characterized in that: The first solder joint (21) is convexly arranged on the lower surface of the adapter plate (2), and the back-side power supply metal contact (11) is formed in the back-side power supply area (120) and embedded in the top of the substrate (1).

4. The packaging structure according to claim 2, characterized in that The first chip (3) is provided with a plurality of second metal contacts (32) on the front surface, and the adapter board (2) is provided with a second soldering point (22) embedded in the top and connected to the second metal contacts (32) on its upper surface.

5. The packaging structure according to any one of claims 1 to 4, characterized in that A filling glue layer (8) for filling the gap between the lower surface of the adapter plate (2) and the upper surface of the base plate (1) is provided, and a plastic sealing layer (9) for sealing all components into one body is provided on the upper surface of the base plate (1).

6. The packaging structure according to claim 1, characterized in that The vertical metal block (5) and the horizontal metal block (6) are both metal blocks made of highly conductive metal.

7. The packaging structure according to claim 1, characterized in that The first conductive material layer (41), the second conductive material layer (42), and the third conductive material layer (43) are solder paste layers or conductive adhesive layers.

8. The packaging structure according to claim 1, characterized in that The vertical metal block (5) is mounted on the substrate (1) through the second conductive material layer (42) in a SMT manner and is conductively connected to the back-side power supply metal contact (11).

9. The packaging structure according to claim 4, characterized in that The substrate (1) is such that the second metal contact (32) and the second solder joint (22) are directly bonded and interconnected in a point-to-point manner.

10. The packaging structure according to claim 1, characterized in that The substrate (1) is a FCBGA packaging substrate.

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