Wiring process of multilayer printed circuit board

Abstract

The invention discloses a multilayer printed circuit board wiring process, and relates to the technical field of electronic circuit board manufacturing, and the method comprises the steps: obtaining a wiring target and preset parameter conditions of a multilayer printed circuit board; calculating a target connection mode by adopting a circuit board wiring model based on the wiring target of the multi-layer printed circuit board and preset parameter conditions; coating photoresist on an inner-layer copper foil of the middle-layer substrate, transferring a circuit pattern to the copper foil through exposure and development processes according to a wiring target path, target layer selection, a target via hole position and a target element position, and drilling at a specified position by using a drilling machine; forming a conductive layer on the hole wall of the hole through an electroplating process; and repeating the manufacturing process of the inner layer of the middle-layer substrate on the outer-layer copper foil of the middle-layer substrate according to the wiring target path, the target layer selection, the target via hole position and the target element position to form an outer-layer circuit pattern. The efficiency of the wiring process of the printed circuit board is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuit board manufacturing, and in particular to a multi-layer printed circuit board wiring process. Background Art

[0002] With the rapid development of electronic technology, integrated circuit design and manufacturing, the functions of printed circuit boards are increasingly enhanced, and the number of stacking layers is increasing. In the prior art, technicians usually design the circuit of the printed circuit board according to the wiring target, so as to determine the wiring process of the printed circuit board. However, this method has the technical problem of low efficiency of manual wiring.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiment of the present application provides a multi-layer printed circuit board wiring process to solve the above-mentioned technical problems.

[0005] The present application provides a multi-layer printed circuit board wiring process, comprising:

[0006] Obtaining target and preset parameter conditions for multi-layer printed circuit board wiring;

[0007] Based on the target and the preset parameter conditions of the multi-layer printed circuit board wiring, a circuit board wiring model is used to calculate a target connection mode; wherein the circuit board wiring model is trained and optimized based on a machine learning algorithm; the target connection mode includes a target path for wiring, a target layer selection, a target via position, and a target component position;

[0008] Cut the copper foil into an intermediate substrate of a preset processing size;

[0009] Coating photoresist on the inner copper foil of the intermediate substrate, transferring the circuit pattern to the copper foil through exposure and development processes according to the target path of the wiring, the target layer selection, the target via position and the target component position; removing the excess copper foil through an etching process to form an inner circuit pattern;

[0010] Alternately stacking the inner layer circuit pattern and the insulating layer, and pressing the inner layer circuit pattern and the insulating layer into one by a high temperature and high pressure process; drilling holes at designated positions using a drilling machine;

[0011] A conductive layer is formed on the hole wall of the hole by an electroplating process to achieve electrical connection between different layers;

[0012] According to the target routing path, the target layer selection, the target via position and the target component position, the inner layer manufacturing process of the intermediate layer substrate is repeated on the outer copper foil of the intermediate layer substrate to form an outer layer circuit pattern.

[0013] Further, the objectives of the multilayer printed circuit board wiring include one or more of the following: wiring density objectives, signal integrity objectives, electromagnetic compatibility objectives, power consumption objectives, noise objectives, component distance objectives, thermal management objectives, cost objectives, mechanical stability objectives, electrical safety objectives, maintainability objectives, and transmission objectives; wherein the transmission objectives include that the wiring design meets preset impedance matching and transmission line requirements;

[0014] The preset parameter conditions include signal line length, wiring width, wiring spacing, interlayer insulation thickness, and diameter and depth of microholes; wherein the signal line length includes data signal lines and clock signal lines, and the data signal lines include single-ended signal lines or differential signal lines.

[0015] Furthermore, the target component positions include the positions of special components, the positions of noise components, the positions of noise element modules, the positions of high-voltage components and the positions of low-voltage components; wherein the special components include large-scale ICs, high-power tubes and signal sources; the noise components include clock generators and crystal oscillators; and the noise element modules include high-current circuits and switching circuits.

[0016] Further, the component distance target includes: the position of the noise component meets the first spacing condition; the position of the noise module meets the second spacing condition; the width of the electrical isolation zone between the high-voltage component and the low-voltage component is greater than a preset width threshold;

[0017] Among them, the first spacing condition includes that the distance between the noise component and the clock input terminal of the central processing unit is greater than the first preset distance, and the distance between the noise component and the high-speed signal circuit is greater than the second preset distance; the second spacing condition includes that the distance between the noise element module and the high-speed signal circuit is greater than the third preset distance; the high-speed signal circuit includes a logic control circuit and a storage circuit.

[0018] Furthermore, the construction and training optimization steps of the circuit board wiring model include:

[0019] Collecting circuit board wiring data in various wiring cases, and creating a wiring information multi-cross tree data structure according to the circuit board wiring data; wherein the circuit board wiring data includes wiring targets, parameter conditions, paths, layer selections, via positions, and component positions; the nodes in the wiring information multi-cross tree structure include decision points, connection points, and branch points; the decision points correspond to the wiring targets; the branch points correspond to the parameter conditions; the connection points correspond to the paths, the layer selections, the via positions, and the component positions;

[0020] Using a particle swarm algorithm to update each node in the wiring information multi-cross tree data structure to obtain an optimized multi-cross tree data structure;

[0021] Building a machine learning model based on the optimized multi-cross tree data structure;

[0022] The machine learning algorithm is used to train and optimize the constructed machine learning model.

[0023] Furthermore, the particle swarm algorithm is used to update each node in the wiring information multi-cross tree data structure to obtain an optimized multi-cross tree data structure, including:

[0024] Setting initial parameters; wherein the initial parameters include population size, inertia weight, learning factor, number of iterations, maximum speed value and minimum speed value;

[0025] Determine an initial position vector set based on the decision points, connection points and branch points included in the multi-cross tree structure of the wiring information;

[0026] Randomly assigning a position vector to each particle according to the initial position vector set; and randomly assigning a velocity vector to each particle; wherein the position vector represents the current solution, and the velocity vector represents the trend and amplitude of particle movement;

[0027] Evaluate the quality of each particle's position vector and velocity vector according to its fitness function;

[0028] Based on the evaluation results of the quality of the position vector and the velocity vector of each particle, the individual optimal position and the global optimal position of the particle are updated until the number of iterations is reached;

[0029] According to the individual optimal position and the global optimal position of the particles after the iteration, each node in the wiring information multi-crossing tree data structure is updated to obtain the optimized multi-crossing tree data structure.

[0030] Furthermore, the machine learning algorithm includes a standard LM algorithm and a long short-term memory algorithm; the machine learning model is constructed based on the optimized multi-cross tree data structure; and the machine learning algorithm is used to train and optimize the constructed machine learning model, including:

[0031] Based on the optimized multi-cross tree data structure, a long short-term memory network model is constructed using a sequential model; wherein the long short-term memory network model includes a vector embedding layer, a bidirectional LSTM layer and a fully connected layer;

[0032] Using the standard LM algorithm to correct the model parameters of the constructed long short-term memory network model, and obtain the fitting feature quantity of the model parameters;

[0033] According to the optimized multi-cross tree data structure, the modified long short-term memory network model is trained and optimized until the fitting feature quantity of the model parameters meets the cross entropy loss condition;

[0034] The modified long short-term memory network model after training and optimization is determined as the circuit board wiring model.

[0035] Furthermore, the circuit board routing model is integrated into multi-layer printed circuit board design software, so that the multi-layer printed circuit board design software automatically assists designers in making routing decisions.

[0036] Furthermore, the top layer of the multilayer printed circuit board is a power layer; the bottom layer of the multilayer printed circuit board is a ground layer; both the top layer and the bottom layer use negative films; the power layer is partitioned and isolated using partition lines, and the line width of the partition lines is between 20 and 70 mi l.

[0037] Furthermore, a drilling machine is used to drill holes at designated locations, including: using micro-hole technology and blind-buried hole technology to drill holes at the designated locations.

[0038] Based on the embodiments provided in the present application, the target and preset parameter conditions of the multi-layer printed circuit board wiring are obtained; based on the target and preset parameter conditions of the multi-layer printed circuit board wiring, the target connection mode is calculated using the circuit board wiring model; wherein the circuit board wiring model is trained and optimized based on a machine learning algorithm; the target connection mode includes a target path for wiring, a target layer selection, a target via position, and a target component position; the copper foil is cut into an intermediate layer substrate of a preset processing size; photoresist is coated on the inner copper foil of the intermediate layer substrate, and a target via position is obtained according to the target path for wiring, the target layer selection, the target via position, and the target component position. Position, transfer the circuit pattern to the copper foil through exposure and development process; remove the excess copper foil through etching process to form the inner layer circuit pattern; alternately stack the inner layer circuit pattern and the insulating layer, and press the inner layer circuit pattern and the insulating layer into one through high temperature and high pressure process; use a drilling machine to drill holes at designated positions; form a conductive layer on the hole wall through electroplating process to achieve electrical connection between different layers; according to the target routing path, target layer selection, target via position and target component position of the wiring, repeat the inner layer production process of the middle layer substrate on the outer copper foil of the middle layer substrate to form the outer layer circuit pattern. Thus, it is realized that the multi-layer printed circuit board is designed automatically according to the wiring target and preset parameter conditions, thereby improving the efficiency of the wiring process of the printed circuit board.

[0039] Specifically, it has the following beneficial effects: clarifying the wiring goals and preset parameters helps to formulate a reasonable design plan and ensure the feasibility and effectiveness of the design; optimizing the wiring model through machine learning algorithms can quickly calculate the optimal connection method, including wiring paths, layer selection, via locations and component locations, thereby improving design efficiency and accuracy; the coating of photoresist provides a basis for subsequent circuit pattern transfer, ensuring the clarity and accuracy of the pattern; through precise exposure and development processes, the fidelity of the circuit pattern is ensured, the error in the subsequent etching process is reduced, and the reliability of the circuit is improved; the etching process can effectively remove unnecessary copper foil, form a clear circuit pattern, and ensure the functionality and performance of the circuit; the high temperature and high pressure process can ensure good adhesion between the layers and improve the mechanical strength and electrical performance of the circuit board; the precise drilling position ensures the reliability of the subsequent electrical connection and reduces circuit failures caused by improper hole positions; the electroplating process can effectively achieve interlayer connection, ensure smooth signal transmission, and improve the overall performance of the circuit board; through repeated production processes, the consistency and reliability of the outer circuit pattern and the inner circuit pattern are ensured, and finally a complete multi-layer printed circuit board is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the embodiments of the present invention and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 is a flow chart of an optional multi-layer printed circuit board wiring process according to an embodiment of the present application;

[0042] Figure 2 The flowchart is another optional multi-layer printed circuit board wiring process according to an embodiment of the present application.

[0043] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0045] Alternatively, if Figure 1 As shown, the present application provides a multi-layer printed circuit board wiring process, including:

[0046] S101, obtaining the target and preset parameter conditions of the multi-layer printed circuit board wiring;

[0047] S102, based on the target and preset parameter conditions of the multi-layer printed circuit board routing, a circuit board routing model is used to calculate a target connection mode; wherein the circuit board routing model is trained and optimized based on a machine learning algorithm; the target connection mode includes a target routing path, a target layer selection, a target via position, and a target component position;

[0048] S103, cutting the copper foil into an intermediate layer substrate of a preset processing size;

[0049] S104, coating photoresist on the inner copper foil of the intermediate substrate, transferring the circuit pattern to the copper foil through exposure and development processes according to the target routing path, target layer selection, target via position and target component position; removing excess copper foil through etching process to form the inner circuit pattern;

[0050] S105, alternately stacking the inner layer circuit pattern and the insulating layer, and pressing the inner layer circuit pattern and the insulating layer into one by a high temperature and high pressure process; drilling holes at designated positions using a drilling machine;

[0051] S106, forming a conductive layer on the hole wall of the hole by an electroplating process to achieve electrical connection between different layers;

[0052] S107, repeating the inner layer manufacturing process of the intermediate layer substrate on the outer copper foil of the intermediate layer substrate according to the target routing path, target layer selection, target via position and target component position, to form an outer layer circuit pattern.

[0053] Based on the embodiments provided in the present application, the target and preset parameter conditions of the multi-layer printed circuit board wiring are obtained; based on the target and preset parameter conditions of the multi-layer printed circuit board wiring, the target connection mode is calculated using the circuit board wiring model; wherein the circuit board wiring model is trained and optimized based on a machine learning algorithm; the target connection mode includes a target path for wiring, a target layer selection, a target via position, and a target component position; the copper foil is cut into an intermediate layer substrate of a preset processing size; photoresist is coated on the inner copper foil of the intermediate layer substrate, and a target via position is obtained according to the target path for wiring, the target layer selection, the target via position, and the target component position. Position, transfer the circuit pattern to the copper foil through exposure and development process; remove the excess copper foil through etching process to form the inner layer circuit pattern; alternately stack the inner layer circuit pattern and the insulating layer, and press the inner layer circuit pattern and the insulating layer into one through high temperature and high pressure process; use a drilling machine to drill holes at designated positions; form a conductive layer on the hole wall through electroplating process to achieve electrical connection between different layers; according to the target routing path, target layer selection, target via position and target component position of the wiring, repeat the inner layer production process of the middle layer substrate on the outer copper foil of the middle layer substrate to form the outer layer circuit pattern. Thus, it is realized that the multi-layer printed circuit board is designed automatically according to the wiring target and preset parameter conditions, thereby improving the efficiency of the wiring process of the printed circuit board.

[0054] Specifically, it has the following beneficial effects: clarifying the wiring goals and preset parameters helps to formulate a reasonable design plan and ensure the feasibility and effectiveness of the design; optimizing the wiring model through machine learning algorithms can quickly calculate the optimal connection method, including wiring paths, layer selection, via locations and component locations, thereby improving design efficiency and accuracy; the coating of photoresist provides a basis for subsequent circuit pattern transfer, ensuring the clarity and accuracy of the pattern; through precise exposure and development processes, the fidelity of the circuit pattern is ensured, the error in the subsequent etching process is reduced, and the reliability of the circuit is improved; the etching process can effectively remove unnecessary copper foil, form a clear circuit pattern, and ensure the functionality and performance of the circuit; the high temperature and high pressure process can ensure good adhesion between the layers and improve the mechanical strength and electrical performance of the circuit board; the precise drilling position ensures the reliability of the subsequent electrical connection and reduces circuit failures caused by improper hole positions; the electroplating process can effectively achieve interlayer connection, ensure smooth signal transmission, and improve the overall performance of the circuit board; through repeated production processes, the consistency and reliability of the outer circuit pattern and the inner circuit pattern are ensured, and finally a complete multi-layer printed circuit board is formed.

[0055] Further, the objectives of the multilayer printed circuit board wiring include one or more of the following: wiring density objectives, signal integrity objectives, electromagnetic compatibility objectives, power consumption objectives, noise objectives, component distance objectives, thermal management objectives, cost objectives, mechanical stability objectives, electrical safety objectives, maintainability objectives, and transmission objectives; wherein the transmission objectives include that the wiring design meets preset impedance matching and transmission line requirements;

[0056] The preset parameter conditions include signal line length, wiring width, wiring spacing, interlayer insulation thickness, and diameter and depth of microholes; wherein the signal line length includes data signal lines and clock signal lines, and the data signal lines include single-ended signal lines or differential signal lines.

[0057] Furthermore, the target component positions include the positions of special components, the positions of noise components, the positions of noise element modules, the positions of high-voltage components and the positions of low-voltage components; among which, special components include large-scale ICs, high-power tubes and signal sources; noise components include clock generators and crystal oscillators; noise element modules include high-current circuits and switching circuits.

[0058] Further, the component distance target includes: the position of the noise component meets the first spacing condition; the position of the noise module meets the second spacing condition; the width of the electrical isolation zone between the high voltage component and the low voltage component is greater than a preset width threshold;

[0059] Among them, the first spacing condition includes that the distance between the noise component and the clock input terminal of the central processing unit is greater than the first preset distance, and the distance between the noise component and the high-speed signal circuit is greater than the second preset distance; the second spacing condition includes that the distance between the noise component module and the high-speed signal circuit is greater than the third preset distance; the high-speed signal circuit includes a logic control circuit and a storage circuit.

[0060] Furthermore, the construction and training optimization steps of the circuit board wiring model include:

[0061] Collecting circuit board wiring data in various wiring cases, and creating a wiring information multi-cross tree data structure according to the circuit board wiring data; wherein the circuit board wiring data includes wiring targets, parameter conditions, paths, layer selections, via positions, and component positions; nodes in the wiring information multi-cross tree structure include decision points, connection points, and branch points; decision points correspond to wiring targets; branch points correspond to parameter conditions; connection points correspond to paths, layer selections, via positions, and component positions;

[0062] The particle swarm algorithm is used to update each node in the multi-cross tree data structure of the wiring information to obtain an optimized multi-cross tree data structure;

[0063] Build machine learning models based on optimized multi-cross tree data structures;

[0064] The machine learning algorithm is used to train and optimize the constructed machine learning model.

[0065] Furthermore, a particle swarm algorithm is used to update each node in the wiring information multi-cross tree data structure to obtain an optimized multi-cross tree data structure, including:

[0066] Set initial parameters, including population size, inertia weight, learning factor, number of iterations, maximum speed value, and minimum speed value;

[0067] Determine an initial position vector set based on the decision points, connection points and branch points included in the multi-cross tree structure of the wiring information;

[0068] A position vector is randomly assigned to each particle according to the initial position vector set; and a velocity vector is randomly assigned to each particle; wherein the position vector represents the current solution, and the velocity vector represents the trend and amplitude of the particle movement;

[0069] Update the position vector and velocity vector of each particle based on the following formula;

[0070]

[0071] in, is the velocity vector of particle i at time t; is the position vector of particle i at time t; p i is the individual optimal position of particle i; g i is the global optimal position; α is the inertia weight; β and γ are both learning factors; rand() is a random number; is the velocity vector of particle i at time t+1; The position vector of particle i at time t+1;

[0072] Evaluate the quality of each particle's position vector and velocity vector according to its fitness function;

[0073]

[0074] Among them, f is the fitness function of each particle; the two-dimensional coordinates of the jth point of a particle are (x j ,y j ); the two-dimensional coordinates of the j+1th point of a particle are (x j+1 ,y j+1 );

[0075] Based on the evaluation results of the quality of the position vector and velocity vector of each particle, the individual optimal position and the global optimal position of the particle are updated until the number of iterations is reached;

[0076] According to the individual optimal position and the global optimal position of the particles after the iteration, each node in the wiring information multi-cross tree data structure is updated to obtain an optimized multi-cross tree data structure.

[0077] Based on the embodiments provided in this application, the particle swarm algorithm can effectively optimize the multi-cross tree data structure of wiring information and improve the efficiency and accuracy of circuit board wiring. This method combines the advantages of swarm intelligence and adaptive learning, and can find the optimal solution in a complex wiring environment, thereby improving the overall performance and reliability of circuit design.

[0078] Machine learning algorithms include the standard LM algorithm and the long short-term memory algorithm; machine learning models are constructed based on the optimized multi-cross tree data structure;

[0079] Alternatively, if Figure 2 As shown, a machine learning algorithm is used to train and optimize the constructed machine learning model, including:

[0080] S201, based on the optimized multi-cross tree data structure, a long short-term memory network model is constructed using a sequential model; wherein the long short-term memory network model includes a vector embedding layer, a bidirectional LSTM layer and a fully connected layer;

[0081] S202, using a standard LM algorithm to modify the model parameters of the constructed long short-term memory network model to obtain fitting feature quantities of the model parameters;

[0082] S203, training and optimizing the modified long short-term memory network model according to the optimized multi-cross tree data structure until the fitting feature quantity of the model parameters meets the cross entropy loss condition;

[0083] S204, determining the modified long short-term memory network model after training and optimization as a circuit board wiring model.

[0084]

[0085] Among them, ω is the fitting characteristic quantity of the model parameters; θ is the model parameter of the long short-term memory network model; J(θ) is the Jacobian matrix of the model parameters; J(θ) T is the transpose of the Jacobian matrix of the model parameters; ε is the jitter term of the standard LM algorithm; J(θ) -1 is the inverse of the Jacobian matrix of the model parameters.

[0086] Based on the embodiments provided in this application, by using a sequential model, time series data can be effectively processed, which is particularly important for time-dependent problems in circuit board wiring. The combination of vector embedding layer, bidirectional LSTM layer and fully connected layer helps the model capture complex spatiotemporal features and improve the accuracy of wiring decisions; the LM algorithm is an effective nonlinear least squares optimization algorithm for quickly correcting model parameters. In this way, a more accurate model parameter fit can be obtained; through continuous training and optimization, the model can better adapt to the structure and characteristics of wiring data. This iterative process ensures that the fitting feature quantity of the model parameters meets the cross-entropy loss condition, thereby improving the predictive performance and generalization ability of the model; the final model can be used as an effective tool for circuit board wiring, providing accurate routing paths, layer selection, via locations and component location predictions. This helps to automate and optimize the circuit board design process, improve design efficiency and the quality of the final product.

[0087] Furthermore, the circuit board routing model is integrated into the multi-layer printed circuit board design software, so that the multi-layer printed circuit board design software automatically assists the designer in making routing decisions.

[0088] Furthermore, the top layer of the multilayer printed circuit board is a power layer; the bottom layer of the multilayer printed circuit board is a ground layer; both the top layer and the bottom layer use negative films; the power layer is partitioned and isolated using partition lines, and the line width of the partition lines is 20 to 70 mi l.

[0089] Further, a drilling machine is used to drill holes at designated locations, including: using micro-hole technology and blind-buried hole technology to drill holes at designated locations.

[0090] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A multi-layer printed circuit board wiring process, characterized in that: include: Obtaining target and preset parameter conditions for multi-layer printed circuit board wiring; Based on the target and the preset parameter conditions of the multi-layer printed circuit board wiring, a circuit board wiring model is used to calculate a target connection mode; wherein the circuit board wiring model is trained and optimized based on a machine learning algorithm; the target connection mode includes a target path for wiring, a target layer selection, a target via position, and a target component position; Cut the copper foil into an intermediate substrate of a preset processing size; Coating photoresist on the inner copper foil of the intermediate substrate, transferring the circuit pattern to the copper foil through exposure and development processes according to the target path of the wiring, the target layer selection, the target via position and the target component position; removing the excess copper foil through an etching process to form an inner circuit pattern; Alternately stacking the inner layer circuit pattern and the insulating layer, and pressing the inner layer circuit pattern and the insulating layer into one by a high temperature and high pressure process; drilling holes at designated positions using a drilling machine; A conductive layer is formed on the hole wall of the hole by an electroplating process to achieve electrical connection between different layers; According to the target routing path, the target layer selection, the target via position and the target component position, the inner layer manufacturing process of the intermediate layer substrate is repeated on the outer copper foil of the intermediate layer substrate to form an outer layer circuit pattern.

2. The multilayer printed circuit board wiring process according to claim 1, characterized in that: The objectives of the multilayer printed circuit board wiring include one or more of the following: wiring density objectives, signal integrity objectives, electromagnetic compatibility objectives, power consumption objectives, noise objectives, component distance objectives, thermal management objectives, cost objectives, mechanical stability objectives, electrical safety objectives, maintainability objectives, and transmission objectives; wherein the transmission objectives include that the wiring design meets preset impedance matching and transmission line requirements; The preset parameter conditions include signal line length, wiring width, wiring spacing, interlayer insulation thickness, and diameter and depth of microholes; wherein the signal line length includes data signal lines and clock signal lines, and the data signal lines include single-ended signal lines or differential signal lines.

3. The multilayer printed circuit board wiring process according to claim 2, characterized in that: The target component positions include the positions of special components, noise components, noise element modules, high-voltage components and low-voltage components; wherein the special components include large-scale ICs, high-power tubes and signal sources; the noise components include clock generators and crystal oscillators; and the noise element modules include high-current circuits and switching circuits.

4. The multilayer printed circuit board wiring process according to claim 3, characterized in that: The component distance target includes: the position of the noise component meets the first spacing condition; the position of the noise module meets the second spacing condition; the width of the electrical isolation zone between the high-voltage component and the low-voltage component is greater than a preset width threshold; Among them, the first spacing condition includes that the distance between the noise component and the clock input terminal of the central processing unit is greater than the first preset distance, and the distance between the noise component and the high-speed signal circuit is greater than the second preset distance; the second spacing condition includes that the distance between the noise element module and the high-speed signal circuit is greater than the third preset distance; the high-speed signal circuit includes a logic control circuit and a storage circuit.

5. The multi-layer printed circuit board wiring process according to claim 1, characterized in that: The construction and training optimization steps of the circuit board wiring model include: Collect circuit board wiring data in various wiring cases, and create a wiring information multi-cross tree data structure based on the circuit board wiring data; wherein the circuit board wiring data includes wiring targets, parameter conditions, paths, layer selections, via positions, and component positions; the nodes in the wiring information multi-cross tree structure include decision points, connection points, and branch points; the decision points correspond to the wiring targets; the branch points correspond to the parameter conditions; the connection points correspond to the paths, the layer selections, the via positions, and the component positions.

6. The multilayer printed circuit board wiring process according to claim 5, characterized in that: Using a particle swarm algorithm to update each node in the wiring information multi-cross tree data structure to obtain an optimized multi-cross tree data structure; Building a machine learning model based on the optimized multi-cross tree data structure; The machine learning algorithm is used to train and optimize the constructed machine learning model.

7. The multilayer printed circuit board wiring process according to claim 6, characterized in that: The particle swarm algorithm is used to update each node in the wiring information multi-cross tree data structure to obtain an optimized multi-cross tree data structure, including: Setting initial parameters; wherein the initial parameters include population size, inertia weight, learning factor, number of iterations, maximum speed value and minimum speed value; Determine an initial position vector set based on the decision points, connection points and branch points included in the multi-cross tree structure of the wiring information; A position vector is randomly assigned to each particle according to the initial position vector set; and a velocity vector is randomly assigned to each particle; wherein the position vector represents the current solution, and the velocity vector represents the trend and amplitude of particle movement.

8. The multi-layer printed circuit board wiring process according to claim 7, characterized in that: Evaluate the quality of each particle's position vector and velocity vector according to its fitness function; Based on the evaluation results of the quality of the position vector and the velocity vector of each particle, the individual optimal position and the global optimal position of the particle are updated until the number of iterations is reached; According to the individual optimal position and the global optimal position of the particles after the iteration, each node in the wiring information multi-crossing tree data structure is updated to obtain the optimized multi-crossing tree data structure.

9. The multilayer printed circuit board wiring process according to claim 8, characterized in that: The machine learning algorithm includes a standard LM algorithm and a long short-term memory algorithm; the machine learning model is constructed based on the optimized multi-cross tree data structure; The machine learning algorithm is used to train and optimize the constructed machine learning model, including: Based on the optimized multi-cross tree data structure, a long short-term memory network model is constructed using a sequential model; wherein the long short-term memory network model includes a vector embedding layer, a bidirectional LSTM layer and a fully connected layer; The model parameters of the constructed long short-term memory network model are corrected using the standard LM algorithm to obtain the fitting feature quantities of the model parameters.

10. The multi-layer printed circuit board wiring process according to claim 98, characterized in that: The machine learning algorithm includes a standard LM algorithm and a long short-term memory algorithm; the machine learning model is constructed based on the optimized multi-cross tree data structure; The machine learning model constructed by using the machine learning algorithm is trained and optimized, and further includes: According to the optimized multi-cross tree data structure, the modified long short-term memory network model is trained and optimized until the fitting feature quantity of the model parameters meets the cross entropy loss condition; The modified long short-term memory network model after training and optimization is determined as the circuit board wiring model.

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