Semiconductor device and semiconductor device preparation method

Abstract

The invention relates to a semiconductor device and a semiconductor device preparation method. The semiconductor device comprises a substrate; the epitaxial layer is arranged on one side of the substrate, and a first groove is formed in the surface of the side, away from the substrate, of the epitaxial layer; the grid electrode is at least partially located in the first groove; the first oxide layer is located at the bottom of the first groove and comprises a plane part and a curved surface part connected with the edge of the plane part, the curved surface part faces the grid electrode, and the corner of the grid electrode is matched and connected with the curved surface part; the gate dielectric layer is arranged on the side wall of the gate, and the thickness of the first oxide layer is larger than that of the gate dielectric layer. The first oxide layer at the bottom of the first groove and the corner position of the grid electrode are smoothed, the peak electric field intensity of the corner position is reduced, the breakdown resistance of the device is improved, and the reliability of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Semiconductor power devices MOSFET are widely used in the field of power electronics due to their unique advantages such as fast switching speed, high input impedance, good frequency characteristics, and good thermal stability. Compared with traditional planar MOSFET, trench MOSFET eliminates the JFET area and has no JFET resistance, so it has lower characteristic on-resistance and lower power loss. At present, the industry has gradually shifted from planar to trench type.

[0003] However, due to the structural and process limitations of existing semiconductor devices, the reliability of semiconductor devices needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for preparing the semiconductor device, which achieves smooth processing of the first oxide layer at the bottom of the first trench and the gate corner position, reduces the peak electric field strength at the corner position, enhances the breakdown resistance of the device, and improves the reliability of the device.

[0005] On the one hand, according to an embodiment of the present application, a semiconductor device is proposed, including: a substrate, the substrate is of a first conductivity type; an epitaxial layer, arranged on one side of the substrate, a first groove is provided on the surface of the epitaxial layer facing away from the substrate, and the epitaxial layer is of the first conductivity type; a gate, at least partially located in the first groove; a first oxide layer, located at the bottom of the first trench, the first oxide layer includes a planar portion and a curved portion connected to the edge of the planar portion, the curved portion is arranged toward the gate, and the corners of the gate are matched and connected to the curved portion; a gate dielectric layer, arranged on the sidewalls of the gate, the thickness of the first oxide layer is greater than the thickness of the gate dielectric layer.

[0006] According to one aspect of an embodiment of the present application, in a cross section of the semiconductor device in a thickness direction, the curved portion is in the form of an arc toward a first surface of the gate.

[0007] According to one aspect of the embodiment of the present application, the central angle corresponding to the arc is equal to 90°.

[0008] According to one aspect of an embodiment of the present application, the thickness of the first oxide layer is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms; and / or the thickness of the gate dielectric layer is greater than or equal to 500 angstroms and less than or equal to 800 angstroms.

[0009] According to one aspect of an embodiment of the present application, the semiconductor device also includes a first well region arranged on both sides of the first trench, a source region located in the first well region, and a second well region; the source region is located on the side of the second well region away from the substrate, the first well region is of the second conductivity type, the source region is of the first conductivity type, and the second well region is of the second conductivity type.

[0010] According to one aspect of an embodiment of the present application, the semiconductor device also includes an isolation dielectric layer arranged on the side of the source region away from the second well region and a contact hole penetrating the isolation dielectric layer and the source region, wherein the contact hole is connected to the second well region; a first electrode layer is arranged on the surface of the isolation dielectric layer on the side away from the second well region and in the contact hole.

[0011] On the other hand, according to an embodiment of the present application, a method for preparing a semiconductor device is proposed, comprising the following steps: providing a substrate, and forming an epitaxial layer on one side of the substrate, the substrate being of a first conductivity type, and the epitaxial layer being of a first conductivity type; forming a first trench on the side of the epitaxial layer away from the substrate; growing a first oxide material layer on the surface of the epitaxial layer away from the substrate, the bottom of the first trench, and the sidewall; forming a first masking layer on the side of the first oxide material layer away from the epitaxial layer, and patterning the first masking layer to form a masking portion, the masking portion covering the first oxide material layer at the bottom of the first trench; using the masking portion as a shield, removing the first oxide material layer not shielded by the masking portion to form a first oxide layer, the first oxide layer comprising a planar portion and a curved portion connected to the edge of the planar portion; removing the masking portion; forming a gate and a gate dielectric layer located on the sidewall of the gate on the side of the first oxide layer away from the epitaxial layer, respectively, the corners of the gate and the curved portion are matched and connected, and the thickness of the first oxide layer is greater than the thickness of the gate dielectric layer.

[0012] According to another aspect of the embodiment of the present application, the step of growing a first oxide material layer on a surface of the epitaxial layer facing away from the substrate, the bottom of the first trench, and the sidewall includes: A first oxide material layer is grown on the surface of the epitaxial layer facing away from the substrate, the bottom and the sidewall of the first trench by a thermal oxidation growth process.

[0013] According to another aspect of an embodiment of the present application, a first masking layer is formed on a side of the first oxide material layer away from the epitaxial layer, and the first masking layer is patterned to form a masking portion, wherein the masking portion covers the first oxide material layer at the bottom of the first trench, the step includes: forming a first masking layer on a side of the first oxide material layer away from the epitaxial layer, and removing a portion of the first masking layer by a chemical mechanical polishing process and / or a dry etching process to form a masking portion, wherein the masking portion covers the first oxide material layer at the bottom of the first trench, and the thickness of the masking portion is equal to the thickness of the first oxide material layer.

[0014] According to another aspect of an embodiment of the present application, in the step of using the masking portion as a shield to remove the first oxide material layer not blocked by the masking portion to form a first oxide layer, wherein the first oxide layer includes a planar portion and a curved portion connected to an edge of the planar portion, the step includes: using the masking portion as a shield to remove the first oxide material layer not blocked by the masking portion through a wet etching process to form a first oxide layer, wherein the first oxide layer includes a planar portion and a curved portion connected to an edge of the planar portion.

[0015] According to the semiconductor device of the embodiment of the present application, the semiconductor device provided by the embodiment of the present invention includes a substrate, an epitaxial layer, a gate, a first oxide layer and a gate dielectric layer. The first oxide layer is located at the bottom of the first trench and is arranged corresponding to the bottom surface of the gate. By limiting the thickness of the first oxide layer to be greater than the thickness of the gate dielectric layer, the thickness of the oxide layer located in the first trench is increased, and the electric field strength at the bottom of the first trench is effectively reduced. Furthermore, the first oxide layer in the present embodiment includes a planar portion and a curved portion connected to the edge of the planar portion, and the corners of the gate are matched and connected to the curved portion, that is, the curved portion corresponds to the corners of the coated gate, and the corners of the gate are smooth surfaces corresponding to the curved portion, so as to achieve smooth processing of the first oxide layer and the gate corner position at the bottom of the first trench, reduce the peak electric field strength at the corner position, enhance the breakdown resistance of the device, and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0017] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention; Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention; Figures 3 to 10 It is a film layer structure diagram of a structure obtained by a semiconductor device preparation method provided according to an embodiment of the present invention.

[0018] Reference numerals: 100, substrate; 101, epitaxial layer; 102, gate dielectric layer; 103, gate; 104, first well region; 105, source region; 106, isolation dielectric layer; 107, contact hole; 108, second well region; 109, first electrode layer; 110, passivation layer; 111, second electrode layer; 112, first oxide layer; 112', first oxide material layer; 1121, planar portion; 1122, curved portion; 113, first shielding layer; K1, first trench.

[0019] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0020] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0021] The directional words appearing in the following description are all directions shown in the figure, and do not limit the specific structure of the semiconductor device and the semiconductor device manufacturing method of this application. In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0022] The semiconductor device of the embodiment of the present application may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The semiconductor device will be mainly described below by taking the structure of a MOSFET transistor as an example. It is understood that the semiconductor device of the embodiment of the present application may also be other types of semiconductor devices with structures similar to those of a MOSFET transistor.

[0023] In order to better understand this application, Figures 1 to 10 The semiconductor device and the method for manufacturing the semiconductor device according to the embodiments of the present application are described in detail.

[0024] The semiconductor device may include an active region and a termination region surrounding at least a portion of a periphery of the active region. Figure 1 A schematic diagram of at least one cell structure of the active region of the semiconductor device is shown in FIG.

[0025] In this article, the cell structure refers to the smallest repeating unit of the conductive structure of the active area of ​​the semiconductor device. The structural schematic diagrams in this application are all schematic diagrams of the structural principle, and the actual size, detailed position, etc. of each component included in the power device can be adjusted according to actual conditions.

[0026] See also Figure 1 A semiconductor device provided in an embodiment of the present application includes: a substrate 100, which is of a first conductivity type; an epitaxial layer 101, which is arranged on one side of the substrate 100, and a first trench K1 is arranged on a surface of the epitaxial layer 101 facing away from the substrate 100, and the epitaxial layer 101 is of the first conductivity type; a gate 103, which is at least partially located in the first trench K1; a first oxide layer 112, which is located at the bottom of the first trench K1, and the first oxide layer 112 includes a planar portion 1121 and a curved portion 1122 connected to the edge of the planar portion 1121, and the curved portion 1122 is arranged toward the gate 103, and the corners of the gate 103 and the curved portion 1122 are matched and connected; a gate dielectric layer 102, which is arranged on the sidewall of the gate 103, and the thickness of the first oxide layer 112 is greater than the thickness of the gate dielectric layer 102.

[0027] The semiconductor device provided in the embodiment of the present invention includes a substrate 100, an epitaxial layer 101, a gate 103, a first oxide layer 112 and a gate dielectric layer 102. The first oxide layer 112 is located at the bottom of the first trench K1 and is arranged corresponding to the bottom surface of the gate 103. By limiting the thickness of the first oxide layer 112 to be greater than the thickness of the gate dielectric layer 102, the thickness of the oxide layer located in the first trench K1 is increased, and the electric field strength at the bottom of the first trench K1 is effectively reduced. Furthermore, the first oxide layer 112 in this embodiment includes The planar portion 1121 and the curved portion 1122 connected to the edge of the planar portion 1121, the corners of the gate 103 are matched and connected to the curved portion 1122, that is, the curved portion 1122 corresponds to the corners of the gate 103, and the corners of the gate 103 are smooth curved surfaces corresponding to the curved portion 1122, so as to achieve rounding of the corners of the first oxide layer 112 and the gate 103 at the bottom of the first trench K1, reduce the peak electric field strength at the corners, enhance the breakdown resistance of the device, and improve the reliability of the device.

[0028] In this embodiment, the first oxide layer 112 can be made of an oxide material such as silicon dioxide. The first oxide layer 112 contacts the bottom of the gate 103, and the curved portion 1122 covers the corners of the gate 103, and the corners of the gate 103 are arranged in a curved surface to avoid the appearance of right-angled peaks, achieve smooth transition, reduce the peak electric field strength at the corner position, enhance the breakdown resistance of the device, and improve the reliability of the device.

[0029] The substrate 100 may be, for example, but not limited to, a silicon substrate 100 , a III-V compound substrate 100 , a germanium (SiGe) substrate 100 , or an epi-substrate 100 (epi-silicon substrate 100 ).

[0030] The epitaxial layer 101 covers the substrate 100. The resistivity of the epitaxial layer 101 is selected according to the structure and breakdown voltage of the device. Generally, the resistivity of the epitaxial layer 101 corresponding to the device with a breakdown voltage of 100V to 200V is 0.3 ohm•cm to 3 ohm•cm. The thickness of the epitaxial layer 101 is selected according to the breakdown voltage of the MOSFET device. The higher the voltage, the thicker the epitaxial layer 101.

[0031] A gate dielectric layer 102 is formed on the surface of the first trench K1, and a gate 103 formed of a gate conductive material is filled in the first trench K1. The shape of the first trench K1 can be a strip, a square, etc., and the width and depth of the first trench K1 can be determined according to the process parameters of the MOSFET device, which is not limited here. The side and bottom surfaces of the first trench K1 are formed with a gate dielectric layer 102. Optionally, the gate dielectric layer 102 is a gate oxide layer, and the gate conductive material is polysilicon.

[0032] In some optional embodiments, in a cross section in the thickness direction of the semiconductor device, the first surface of the curved portion 1122 facing the gate 103 is in an arc shape. Correspondingly, in a cross section in the thickness direction of the semiconductor device, a portion of the surface of the gate 103 and the curved portion 1122 facing each other is in an arc shape, so as to achieve matching connection between the gate 103 and the curved portion 1122.

[0033] The inventors have discovered through experimental research that when the curved portion 1122 is in an arc shape toward the first surface of the gate 103, the transition between the first oxide layer 112 at the bottom of the first trench K1 and the corner of the gate 103 is smoother, and the peak electric field strength at the corner is lower, which can further enhance the breakdown resistance of the device and improve the reliability of the device.

[0034] Optionally, the central angle corresponding to the arc is equal to 90°, in which case the peak electric field strength is lower and the device has better breakdown resistance. Specifically, the specific size of the central angle corresponding to the arc can be adjusted by controlling the preparation process of the first oxide layer 112, that is, the central angle corresponding to the arc can also be greater than or less than 90°, and can be adjusted according to actual needs without special limitation.

[0035] In some optional embodiments, the thickness of the first oxide layer 112 is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms; and / or the thickness of the gate dielectric layer 102 is greater than or equal to 500 angstroms and less than or equal to 800 angstroms.

[0036] It can be understood that the thickness of the first oxide layer 112 should not be too small, otherwise it will affect the breakdown resistance, nor should it be too large, otherwise it will increase the preparation cost and the overall thickness of the semiconductor device. Optionally, the thickness of the first oxide layer 112 can be equal to any one of 2000 angstroms, 2200 angstroms, 2600 angstroms, 2800 angstroms, and 3000 angstroms.

[0037] However, due to the limitation of the manufacturing process, the thickness of the gate dielectric layer 102 is less than that of the first oxide layer 112 . Optionally, the thickness of the gate dielectric layer 102 may be equal to any one of 500 angstroms, 600 angstroms, 700 angstroms, and 800 angstroms.

[0038] See also Figure 1 In some optional embodiments, the semiconductor device further includes a first well region 104 disposed on both sides of the first trench K1, a source region 105 located in the first well region 104, and a second well region 108; the source region 105 is located on the side of the second well region 108 away from the substrate 100, the first well region 104 is of the second conductivity type, the source region 105 is of the first conductivity type, and the second well region 108 is of the second conductivity type.

[0039] In this embodiment, the second well region 108 located on the surface of the first well region 104 can be formed by implanting and activating doping ions of the second conductivity type on the epitaxial layer 101. Optionally, the source region 105 of the first conductivity type can be formed by implanting and activating doping ions of the first conductivity type in the first well region 104. Further optionally, in order to increase the implantation concentration, the source region 105 can be formed by implanting and activating doping ions of the first conductivity type in the first well region 104 multiple times at different energies.

[0040] Ion implantation is a process of implanting charged and energetic particles into the epitaxial layer 101. Compared with the diffusion process, ion implantation can more accurately control impurity doping, repeatability and lower process temperature. High-energy ions lose energy due to collisions with electrons and atoms in the epitaxial layer 101, and finally stop at a certain depth in the lattice. Ion collisions can cause fractures or damage to the semiconductor lattice, so annealing is required to remove these damages.

[0041] See also Figure 1 In some optional embodiments, the semiconductor device further includes an isolation dielectric layer 106 disposed on the side of the source region 105 away from the second well region 108 and a contact hole 107 penetrating the isolation dielectric layer 106 and the source region 105, wherein the contact hole 107 is connected to the second well region 108; a first electrode layer 109 is disposed on the surface of the isolation dielectric layer 106 away from the second well region 108 and in the contact hole 107.

[0042] In this embodiment, the isolation dielectric layer 106 is used to isolate the first electrode layer 109 from the gate 103. The first electrode layer 109 is a metal deposition layer. Optionally, the material of the first electrode layer 109 can be metal aluminum or copper-aluminum alloy. Optionally, the first electrode layer 109 is a source electrode.

[0043] Optionally, the semiconductor device further includes a second electrode layer 111 disposed on a side of the substrate 100 away from the epitaxial layer 101. The second electrode layer 111 is a metal deposition layer. Optionally, the second electrode layer 111 is a drain.

[0044] Optionally, the semiconductor device further includes a passivation layer 110 located on the surface of the first electrode layer 109 .

[0045] Optionally, either one of the first conductivity type and the second conductivity type is N-type, and the other is P-type. When the MOSFET is an N-type semiconductor device, the polarity of the drain relative to the source is positive, and when the MOSFET is a P-type semiconductor device, the polarity of the drain relative to the source is negative. For ease of description, the following is an example in which the first conductivity type is N-type and the second conductivity type is P-type.

[0046] The substrate 100 is of N type, the N type epitaxial layer 101 covers the N type substrate 100, a P type first well region 104 is formed on the epitaxial layer 101, and P type doping ions are injected and activated on the epitaxial layer 101 to form a second well region 108 located on the surface of the first well region 104. N type doping ions are injected and activated in the first well region 104 to form a source region 105, and the second well region 108 covers the source region 105. Optionally, the P type doping ions may be boron, and the N type doping ions may be phosphorus, arsenic and / or other Group V elements. The concentration of the doping ions is determined according to specific design requirements and is not limited here.

[0047] The first trench K1 passes through the second well region 108, the source region 105 and the first well region 104, and contacts the epitaxial layer 101. The first trench K1 is filled with a gate 103 formed of a gate conductive material. The first electrode layer 109, i.e., the source, fills the first trench K1 and contacts the second well region 108 and the source region 105. The isolation dielectric layer 106 is used to isolate the source from the gate 103. The second electrode layer 111, i.e., the drain, is located on the side of the substrate 100 away from the epitaxial layer 101.

[0048] The working principle of the semiconductor device is as follows: when the gate 103 is not biased and the drain is positively biased, the semiconductor device can withstand high voltage. At this time, the J1 junction formed by the first well region 104 and the epitaxial layer 101 is reverse biased, and the voltage is mainly borne by the thicker N-type epitaxial layer 101. When the gate 103 is positively biased, an inversion layer channel is formed on the surface of the P-type well region along the longitudinal side wall of the first trench K1. When the drain is positively biased, the inversion layer channel provides a transmission path for electrons from the source region 105 to the drain. After the electrons pass through the channel from the source region 105, they enter the epitaxial layer 101 at the bottom of the first trench K1, and then the circuit expands within the entire cell cross-sectional width.

[0049] See also Figure 2 The present invention also provides a method for preparing a semiconductor device, comprising the following steps: S110: providing a substrate 100, and forming an epitaxial layer 101 on one side of the substrate 100, wherein the substrate 100 is of a first conductivity type, and the epitaxial layer 101 is of a first conductivity type; S120: forming a first trench K1 on the side of the epitaxial layer 101 facing away from the substrate 100, such as Figure 3 As shown; S130: growing a first oxide material layer 112' on the surface of the epitaxial layer 101 facing away from the substrate 100, the bottom of the first trench K1 and the sidewalls, such as Figure 4 As shown; S140: forming a first masking layer 113 on the side of the first oxide material layer 112' away from the epitaxial layer 101, and patterning the first masking layer 113 to form a masking portion, the masking portion covers the first oxide material layer 112' at the bottom of the first trench K1, such as Figure 5 and Figure 6 As shown; S150: Using the masking portion as a shield, removing the first oxide material layer 112' not shielded by the masking portion to form a first oxide layer 112, wherein the first oxide layer 112 includes a planar portion 1121 and a curved portion 1122 connected to the edge of the planar portion 1121, such as Figure 7 As shown; S160: Remove the masking part, such as Figure 8 As shown; S170: A gate 103 and a gate dielectric layer 102 located on the side of the first oxide layer 112 away from the epitaxial layer 101 are formed respectively, and the corners of the gate 103 and the curved portion 1122 are matched and connected. The thickness of the first oxide layer 112 is greater than the thickness of the gate dielectric layer 102. Fig. 9 shown.

[0050] The semiconductor device manufacturing method provided by the embodiment of the present invention forms a first oxide layer 112 of a desired pattern through a masking portion. The first oxide layer 112 is located at the bottom of the first trench K1 and is arranged corresponding to the bottom surface of the gate 103. By limiting the thickness of the first oxide layer 112 to be greater than the thickness of the gate dielectric layer 102, the thickness of the oxide layer located in the first trench K1 is increased, and the electric field strength at the bottom of the first trench K1 is effectively reduced. Furthermore, the first oxide layer 112 in this embodiment includes a planar portion 1121 and a curved portion 1122 connected to the edge of the planar portion 1121. The corners of the gate 103 and the curved portion 1122 are matched and connected, that is, the curved portion 1122 corresponds to the corners of the gate 103, and the corners of the gate 103 are smooth surfaces corresponding to the curved portion 1122, so as to achieve smooth processing of the corners of the first oxide layer 112 and the gate 103 at the bottom of the first trench K1, reduce the peak electric field strength at the corners, enhance the breakdown resistance of the device, and improve the reliability of the device.

[0051] In step S110 , the substrate 100 may be, for example but not limited to, a silicon substrate 100 , a III-V compound substrate 100 , a germanium (SiGe) substrate 100 , or an epi-substrate 100 (epi-silicon substrate 100 ).

[0052] In step S120 , the epitaxial layer 101 may have a first conductivity type, a second masking layer may be grown on the surface of the epitaxial layer 101 of the first conductivity type, the first trench K1 may be etched, and the second masking layer may be removed to form the first trench K1 on the surface of the epitaxial layer 101 .

[0053] In step S130 , a thermal oxidation growth process may be performed to grow a first oxide layer 112 on the surface of the epitaxial layer 101 and the bottom and sidewalls of the first trench K1 ; In step S140 , a first masking layer 113 , such as silicon nitride, is grown on the first oxide layer 112 . The first masking layer 113 is to fill up the first trench K1 .

[0054] In step S150, a first masking layer 113 may be formed on a side of the first oxide material layer 112' away from the epitaxial layer 101, and a portion of the first masking layer 113 may be removed by a chemical mechanical polishing process and / or a dry etching process to form a masking portion, wherein the masking portion covers the first oxide material layer 112' located at the bottom of the first trench K1; Optionally, the thickness of the masking portion is equal to the thickness of the first oxide material layer 112', that is, the thickness of the first oxide material layer 112' formed on the side wall of the first trench K1 is also exactly equal to the thickness of the masking portion, and the masking portion can be in contact with the first oxide material layer 112' formed on the side wall of the first trench K1, so that the curvature of the curved portion 1122 of the formed first oxide layer 112 meets the requirements. The inventors have found through research and experiments that the thickness of the masking portion is equal to the thickness of the first oxide material layer 112' when, in the cross section of the semiconductor device in the thickness direction, the surface of the gate 103 and the curved portion 1122 relative to each other is an arc, and the central angle corresponding to the arc is equal to 90°, so as to achieve a smooth transition.

[0055] Optionally, a chemical mechanical polishing process is used to remove the first masking layer 113 on the surface of the thick oxide layer, and a dry etching process is used to remove a portion of the first masking layer 113 in the first trench K1, and finally a certain thickness of the first masking layer 113 is retained in the first trench K1; or only a dry etching process can be used to remove the thick oxide surface and a portion of the first masking layer 113 in the trench in one step, and finally a certain thickness of the first masking layer 113 is retained in the first trench K1.

[0056] In some optional embodiments, the step of growing a first oxide material layer 112' on the surface of the epitaxial layer 101 facing away from the substrate 100, the bottom and the sidewall of the first trench K1 includes: growing the first oxide material layer 112' on the surface of the epitaxial layer 101 facing away from the substrate 100, the bottom and the sidewall of the first trench K1 through a thermal oxidation growth process.

[0057] Thermal oxidation is a method of generating silicon oxide on the silicon surface by chemical reaction at high temperature. The first oxide material layer 112' formed by the thermal oxidation growth process has good film quality and strong breakdown resistance. Of course, other process forms can also be used to form the first oxide material layer 112', which is not limited to the above examples.

[0058] In some optional embodiments, the step of removing the first oxide material layer 112' not blocked by the masking portion to form a first oxide layer 112, wherein the first oxide layer 112 includes a planar portion 1121 and a curved portion 1122 connected to the edge of the planar portion 1121, includes: removing the first oxide material layer 112' not blocked by the masking portion through a wet etching process to form a first oxide layer 112, wherein the first oxide layer 112 includes a planar portion 1121 and a curved portion 1122 connected to the edge of the planar portion 1121, using the masking portion as a shield.

[0059] The first oxide layer 112 on the surface of the epitaxial layer 101 and the sidewall of the first trench K1 is removed by a wet etching process. The first oxide layer 112 at the bottom of the first trench K1 is protected from being etched by the masking effect of the remaining first masking layer 113 in the trench, and the first oxide layer 112 at the corner of the bottom of the first trench K1 is made smooth after etching by utilizing the isotropic property of wet etching.

[0060] Optionally, after the step of removing the first oxide material layer 112' not blocked by the masking portion to form a first oxide layer 112, wherein the first oxide layer 112 includes a planar portion 1121 and a curved portion 1122 connected to the edge of the planar portion 1121, the step includes: Using a dry etching or wet etching process to remove the remaining first masking layer 113 at the bottom of the first trench K1; Growing a gate dielectric layer 102 such as silicon dioxide, depositing a gate 103 such as polysilicon and performing dry etching to form the gate 103; On the surface of the epitaxial layer 101, ion implantation and high temperature diffusion processes are used to form a first well region 104 of the second conductivity type and a source region 105 of the first conductivity type. The depth of the first well region 104 is greater than that of the source region 105 and less than the thickness of the gate 103. Deposit an isolation dielectric layer 106, etch a contact hole 107, form a second well region 108 of a second conductivity type by ion implantation and annealing, deposit a first electrode layer 109 and selectively etch it to form a source, deposit a passivation layer 110 and selectively etch it to prepare a second electrode layer 111 to form a drain, such as Fig.10 and Figure 1 shown.

[0061] Specifically, by controlling the thickness of the first oxide layer 112 grown in step S130, the thickness of the mask retained at the bottom of the first trench K1 in step S150, and the time of wet etching in step S150, the device structure can be precisely controlled to form a preset first oxide layer 112 thickness at the bottom of the gate 103 and a preset smooth morphology at the bottom corner of the gate 103.

[0062] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate being of a first conductivity type; An epitaxial layer is provided on one side of the substrate, a first groove is provided on a surface of the epitaxial layer facing away from the substrate, and the epitaxial layer is of a first conductivity type; a gate, at least partially located in the first trench; A first oxide layer, located at the bottom of the first trench, the first oxide layer comprising a planar portion and a curved portion connected to an edge of the planar portion, the curved portion being arranged toward the gate, and the corners of the gate being matched and connected to the curved portion; The gate dielectric layer is disposed on the side wall of the gate, and the thickness of the first oxide layer is greater than the thickness of the gate dielectric layer.

2. The semiconductor device according to claim 1, wherein: In a cross section of the semiconductor device in a thickness direction, the curved portion is in an arc shape toward a first surface of the gate.

3. The semiconductor device according to claim 2, characterized in that The central angle corresponding to the arc is equal to 90°.

4. The semiconductor device according to claim 1, wherein: The thickness of the first oxide layer is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms; and / or, The thickness of the gate dielectric layer is greater than or equal to 500 angstroms and less than or equal to 800 angstroms.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a first well region disposed on both sides of the first trench, a source region located in the first well region, and a second well region; The source region is located on a side of the second well region away from the substrate, the first well region is of the second conductivity type, the source region is of the first conductivity type, and the second well region is of the second conductivity type.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device further comprises an isolation dielectric layer disposed on a side of the source region away from the second well region and a contact hole penetrating the isolation dielectric layer and the source region, wherein the contact hole is connected to the second well region; A first electrode layer is provided on the surface of the isolation dielectric layer on a side away from the second well region and in the contact hole.

7. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, and forming an epitaxial layer on one side of the substrate, wherein the substrate is of a first conductivity type, and the epitaxial layer is of the first conductivity type; forming a first trench on a side of the epitaxial layer facing away from the substrate; Growing a first oxide material layer on the surface of the epitaxial layer facing away from the substrate, the bottom and the sidewall of the first trench; forming a first masking layer on a side of the first oxide material layer away from the epitaxial layer, and patterning the first masking layer to form a masking portion, wherein the masking portion covers the first oxide material layer disposed at the bottom of the first trench; Using the masking portion as a shield, removing the first oxide material layer not shielded by the masking portion to form a first oxide layer, wherein the first oxide layer includes a planar portion and a curved portion connected to an edge of the planar portion; removing the masking portion; A gate and a gate dielectric layer located on the sidewall of the gate are formed on the first oxide layer away from the epitaxial layer. The corners of the gate and the curved portion are matched and connected. The thickness of the first oxide layer is greater than that of the gate dielectric layer.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The step of growing a first oxide material layer on a surface of the epitaxial layer facing away from the substrate, a bottom of the first trench and a sidewall includes: A first oxide material layer is grown on the surface of the epitaxial layer facing away from the substrate, the bottom and the sidewall of the first trench by a thermal oxidation growth process.

9. The method for preparing a semiconductor device according to claim 7, wherein: The step of forming a first masking layer on a side of the first oxide material layer away from the epitaxial layer, and patterning the first masking layer to form a masking portion, wherein the masking portion covers the first oxide material layer at the bottom of the first trench, comprises: A first masking layer is formed on the side of the first oxide material layer away from the epitaxial layer, and a portion of the first masking layer is removed by a chemical mechanical polishing process and / or a dry etching process to form a masking portion, wherein the masking portion covers the first oxide material layer at the bottom of the first groove, and the thickness of the masking portion is equal to the thickness of the first oxide material layer.

10. The method for preparing a semiconductor device according to claim 7, wherein: In the step of removing the first oxide material layer not blocked by the shielding portion using the shielding portion as a shield to form a first oxide layer, wherein the first oxide layer includes a planar portion and a curved portion connected to an edge of the planar portion, the step includes: With the masking portion as a shield, the first oxide material layer not shielded by the masking portion is removed by a wet etching process to form a first oxide layer, wherein the first oxide layer includes a planar portion and a curved portion connected to an edge of the planar portion.

Images