Evaluation test system for fault-tolerant algorithm of pure-light CT core chip

Abstract

The invention discloses an evaluation test system for a fault-tolerant algorithm of a pure-light CT core chip, and the system comprises an SLD light source and an SLD light source control unit, and the SLD light source control unit is disposed between an FPGA main control unit and the SLD light source. The adjustable attenuator is arranged between the first coupler and a tail fiber of the PINFET photoelectric detector, and the first coupler is connected with the SLD light source; the noise simulation unit is arranged between the FPGA main control unit and the A / D converter and is used for simulating common detector noise, and the A / D converter is connected with the PINFET photoelectric detector; the step wave simulation unit is arranged between the FPGA main control unit and the D / A converter; the high and low temperature simulation unit is connected with the first coupler through the second coupler; and the countershaft angle change simulation unit is connected with the high and low temperature simulation unit and is used for simulating the influence of countershaft angle change on current measurement due to poor artificial optical fiber fusion.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and more specifically, to an evaluation test system for a pure optical CT core chip fault tolerance algorithm. Background Art

[0002] The fiber-optic current transformer (FIBER-OPTIC CT), also known as pure optical CT, which was developed with the development of laser and fiber optic technology, has the advantages of good insulation properties, fast dynamic response, simple structure, no need for power supply on the high-voltage side, and digital output. It has been gradually applied to converter stations to provide reliable measurement information for the control protection and operation status monitoring of DC systems. Its operation status is extremely important for the safe operation of the entire power grid.

[0003] Pure optical CT is based on Faraday's magneto-optical effect and Ampere's loop law, uses optical fiber as a sensor element, and contains a large number of electronic and optical components. The main function of the acquisition unit composed of its core chip is to perform analog-to-digital conversion, differential demodulation and digital output of the analog signal output by the optical path unit, and to perform digital square wave modulation and closed-loop feedback control on the optical path unit to achieve primary current transmission. Pure optical CT operates in a complex weather environment and electromagnetic environment. During operation, it is inevitable to be subjected to disturbances imposed by different environmental quantities, such as strong electromagnetic fields and vibrations generated by converter station switch operations and lightning strikes. These disturbance quantities are characterized by short duration and large peak values. On the one hand, it can be isolated through some shielding means; on the other hand, the selection of core chips and internal fault-tolerant design should also be used to reduce the risk of disturbances causing the effectiveness of pure optical CT. In order to further improve the reliability of pure optical CT, the core chip fault-tolerant technology of pure optical CT should be studied based on the fault mechanism and fault phenomenon characteristics of pure optical CT, the design and selection of core chips, and the fault characteristic characteristics. The pure optical CT acquisition unit is mainly used to perform analog-to-digital conversion, differential demodulation and digital output on the analog signal output by the optical path unit, and to perform digital square wave modulation and closed-loop feedback control on the optical path unit to achieve primary current transmission. When it fails or the software fails during actual operation, an alarm signal is sent to the operation and maintenance personnel to request maintenance. At present, the core chip of the pure optical CT is not designed with a fault-tolerant processing mechanism. As a result, once the internal core chip fails or the program fails, the acquisition unit sends a lock signal, causing the pure optical CT to exit operation as a whole, resulting in power outage losses. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides an evaluation test system for a pure optical CT core chip fault tolerance algorithm.

[0005] According to one aspect of the present invention, a pure optical CT core chip fault tolerance algorithm evaluation test system is provided, comprising:

[0006] An SLD light source and an SLD light source control unit, wherein the SLD light source control unit is arranged between the FPGA main control unit and the SLD light source and is used to change the output power and the tube core temperature of the SLD light source;

[0007] An adjustable attenuator, disposed between the first coupler and the pigtail of the PINFET photodetector, for changing the received optical power of the PINFET photodetector, wherein the first coupler is connected to the SLD light source;

[0008] A noise simulation unit is provided between the FPGA main control unit and the A / D converter to simulate common detector noise, wherein the A / D converter is connected to the PINFET photodetector;

[0009] The step wave simulation unit is arranged between the FPGA main control unit and the D / A converter, and controls the step wave height output by the D / A converter to change the half-wave voltage of the modulator;

[0010] A high and low temperature simulation unit is connected to the first coupler through the second coupler to control the test temperature to change the modulator crosstalk;

[0011] The axis angle change simulation unit is connected to the high and low temperature simulation unit to simulate the influence of axis angle change on current measurement due to poor artificial optical fiber fusion.

[0012] Optionally, the pure optical CT core chip fault tolerance algorithm evaluation test system also includes: a chip control signal abnormality simulation unit, connected to the A / D conversion, D / A conversion and the FPGA main control unit, for verifying the chip reset capability.

[0013] Optionally, the pure optical CT core chip fault tolerance algorithm evaluation test system also includes: a message control unit connected to the corresponding interface of the FPGA main control unit, used to control the frame format of the digital output FT3 message and verify the correctness of the CRC check program.

[0014] Optionally, the high and low temperature simulation unit is formed by placing the modulator in a high and low temperature test chamber.

[0015] Optionally, a polarizer is arranged between the high and low temperature simulation unit and the second coupler.

[0016] Optionally, the axis angle simulation unit is embedded between the optical path modulator and the delay line of the pure light CT via a 2×1 coupler, and the polarization direction of the polarizer in the original optical path of the pure light CT is defined as 0°. The second return port of the 2×1 coupler is connected to the 1×3 coupler, and the three same-side ports of the 1×3 coupler are respectively connected to a 90° polarizer, a 45° polarizer and a 1 / 4 wave plate, to establish the output light intensities of the 0° polarizer, the 90° polarizer, the 45° polarizer and the 1 / 4 wave plate, respectively.

[0017] Optionally, the axis angle simulation unit is connected to the sensing optical fiber ring through a delay line.

[0018] Optionally, the chip control signal abnormality simulation unit controls the clock of A / D conversion and D / A conversion, the set signal, the Ready bit abnormality signal, the FPGA self-test completion signal abnormality, and the closed-loop control logic program abnormality alone or in combination.

[0019] Therefore, the present invention verifies the effectiveness of the pure light CT fault-tolerant algorithm by controllably changing the state changes of the core components of the pure light CT. The driving current and temperature control current of the SLD light source of the pure light CT are controlled by the SLD light source control unit to change the output power and core temperature of the SLD light source; the adjustable attenuator is introduced into the photodetector pigtail to change the received optical power of the detector; the noise simulation unit incorporates common detector noise into the A / D signal received by the FPGA main control unit; the step wave control unit controls the step wave height of the D / A output to change the half-wave voltage of the modulator; the high and low temperature simulation unit places the phase modulator in a high and low temperature test box to control the test temperature to change the modulator crosstalk; the axis angle change simulation unit simulates the impact of the axis angle change on the current measurement due to poor artificial optical fiber fusion; the chip control signal abnormality simulation unit simulates the chip's recovery ability after the chip control signal is abnormal; the message control unit verifies the correctness of the CRC check program. The pure light CT core chip will start the internal fault-tolerant algorithm to ensure the stability of the output when detecting changes in external characteristic parameters. By changing the main degradation characteristic parameter value of one of the key optical components while keeping other characteristic parameter values ​​unchanged through the above method, the output of the pure optical CT is used as the monitoring quantity, and the effectiveness of the fault-tolerant algorithm control strategy of the pure optical CT core chip is judged by comparing the normal output with the degraded output. This method can effectively improve the reliability of the pure optical CT, support the stable operation of the DC transmission system, and reduce the workload of operation and maintenance personnel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings:

[0021] Figure 1 It is a structural schematic diagram of an evaluation test system for a pure optical CT core chip fault tolerance algorithm provided by an exemplary embodiment of the present invention; DETAILED DESCRIPTION

[0022] Below, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described here.

[0023] It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0024] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0025] It should also be understood that, in the embodiments of the present invention, “plurality” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0026] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0027] In addition, the term "and / or" in the present invention is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects before and after are in an "or" relationship.

[0028] It should also be understood that the description of the various embodiments of the present invention focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0029] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0030] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0031] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0032] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0033] Figure 1 FIG. 1 is a schematic diagram of a structure of an evaluation test system for a pure optical CT core chip fault tolerance algorithm provided by an exemplary embodiment of the present invention. Figure 1 As shown in the figure, the evaluation test system of the pure optical CT core chip fault tolerance algorithm includes:

[0034] An SLD light source and an SLD light source control unit, wherein the SLD light source control unit is arranged between the FPGA main control unit and the SLD light source and is used to change the output power and the tube core temperature of the SLD light source;

[0035] An adjustable attenuator, disposed between the first coupler and the pigtail of the PINFET photodetector, for changing the received optical power of the PINFET photodetector, wherein the first coupler is connected to the SLD light source;

[0036] A noise simulation unit is provided between the FPGA main control unit and the A / D converter to simulate common detector noise, wherein the A / D converter is connected to the PINFET photodetector;

[0037] The step wave simulation unit is arranged between the FPGA main control unit and the D / A converter, and controls the step wave height output by the D / A converter to change the half-wave voltage of the modulator;

[0038] A high and low temperature simulation unit is connected to the first coupler through the second coupler to control the test temperature to change the modulator crosstalk;

[0039] The axis angle change simulation unit is connected to the high and low temperature simulation unit to simulate the influence of axis angle change on current measurement due to poor artificial optical fiber fusion.

[0040] Specifically, based on the prior art, the present invention provides an evaluation test system for a pure optical CT core chip fault tolerance algorithm.

[0041] Aiming at the need of evaluating the effectiveness of pure optical CT fault-tolerant control strategy, a pure optical CT core chip fault-tolerant control evaluation test system based on key components is constructed, such as Figure 1 shown.

[0042] 1) SLD light source control. Connect the SLD light source control unit between the FPGA central control unit and the SLD light source. By controlling the driving current and temperature control current of the SLD light source, the output power and die temperature of the SLD light source can be changed;

[0043] 2) Adjustable attenuator. Introduce an adjustable attenuator into the pigtail between the coupler and the PINFET photodetector, and change the received optical power of the PINFET photodetector by adjusting the value of the attenuator;

[0044] 3) Noise simulation. Introduce common noise units between the FPGA main control unit and the A / D converter to simulate common detector noise;

[0045] 4) Step wave control. Add a step wave control unit between FPGA and D / A to control the step wave height output by D / A conversion to change the half-wave voltage of the modulator;

[0046] 5) High and low temperature simulation. Place the modulator in a high and low temperature test chamber and control the test temperature to change the modulator crosstalk;

[0047] 6) Simulate the poor fusion of artificial optical fiber by changing the axis angle. The 21 coupler is embedded in the optical path of the pure light CT, and the polarization direction of the polarizer in the original optical path of the pure light CT is defined as 0°. The second return port of the 21 coupler is connected to the 13 coupler, and its three ports on the same side are connected to the 90° polarizer, 45° polarizer and 1 / 4 wave plate respectively. Based on this, the output light intensity of the 0° polarizer, 90° polarizer, 45° polarizer and 1 / 4 wave plate is established respectively to simulate the influence of the axis angle change caused by the poor fusion of artificial optical fiber on the current measurement;

[0048] 7) Simulation of abnormal chip control signals. Control the A / D conversion, D / A conversion clock, set signal, Ready bit abnormal signal, FPGA self-test completion signal abnormality, closed-loop control logic program abnormality, and verify the chip reset capability;

[0049] 8) Message control. The message control unit is connected to the corresponding interface of the FPGA main control unit. It controls the frame format of the digital output FT3 message and verifies the correctness of the CRC check program.

[0050] By changing the main degradation characteristic parameter values ​​of key optical devices and keeping other components of the pure optical CT unchanged, the transformation ratio of the pure optical CT is tested, and the effectiveness of the control strategy is judged based on the occurrence of optical device degradation and the transformation ratio being better than the accuracy requirement.

[0051] Therefore, the present invention verifies the effectiveness of the pure light CT fault-tolerant algorithm by controllably changing the state changes of the core components of the pure light CT. The driving current and temperature control current of the SLD light source of the pure light CT are controlled by the SLD light source control unit to change the output power and core temperature of the SLD light source; the adjustable attenuator is introduced into the photodetector pigtail to change the received optical power of the detector; the noise simulation unit incorporates common detector noise into the A / D signal received by the FPGA main control unit; the step wave control unit controls the step wave height of the D / A output to change the half-wave voltage of the modulator; the high and low temperature simulation unit places the phase modulator in a high and low temperature test box to control the test temperature to change the modulator crosstalk; the axis angle change simulation unit simulates the impact of the axis angle change on the current measurement due to poor artificial optical fiber fusion; the chip control signal abnormality simulation unit simulates the chip's recovery ability after the chip control signal is abnormal; the message control unit verifies the correctness of the CRC check program. The pure light CT core chip will start the internal fault-tolerant algorithm to ensure the stability of the output when detecting changes in external characteristic parameters. By changing the main degradation characteristic parameter value of one of the key optical components while keeping other characteristic parameter values ​​unchanged through the above method, the output of the pure optical CT is used as the monitoring quantity, and the effectiveness of the fault-tolerant algorithm control strategy of the pure optical CT core chip is judged by comparing the normal output with the degraded output. This method can effectively improve the reliability of the pure optical CT, support the stable operation of the DC transmission system, and reduce the workload of operation and maintenance personnel.

[0052] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An evaluation test system for the fault-tolerant algorithm of a pure optical CT core chip, characterized in that: include: An SLD light source and an SLD light source control unit, wherein the SLD light source control unit is arranged between the FPGA main control unit and the SLD light source and is used to change the output power and the die temperature of the SLD light source; an adjustable attenuator, arranged between the first coupler and the pigtail of the PINFET photodetector, for changing the received optical power of the PINFET photodetector, wherein the first coupler is connected to the SLD light source; A noise simulation unit, arranged between the FPGA main control unit and the A / D converter, simulating common detector noise, wherein the A / D converter is connected to the PINFET photodetector; A step wave simulation unit is arranged between the FPGA main control unit and the D / A conversion, and controls the step wave height output by the D / A conversion to change the half-wave voltage of the modulator; A high and low temperature simulation unit is connected to the first coupler through a second coupler to control the test temperature to change the modulator crosstalk; The axis angle change simulation unit is connected to the high and low temperature simulation unit and is used to simulate the influence of the axis angle change on the current measurement due to the poor artificial optical fiber fusion.

2. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 1 is characterized in that: Also includes: The chip control signal abnormality simulation unit is connected to the A / D conversion, the D / A conversion and the FPGA main control unit, and is used to verify the chip reset capability.

3. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 1 is characterized in that: Also includes: The message control unit is connected to the corresponding interface of the FPGA main control unit and is used to control the frame format of the digital output FT3 message and check the correctness of the CRC check program.

4. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 1 is characterized in that: The high and low temperature simulation unit is formed by placing a modulator in a high and low temperature test box.

5. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 1 is characterized in that: A polarizer is arranged between the high and low temperature simulation unit and the second coupler.

6. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 3 is characterized in that: The axis angle simulation unit is embedded between the optical path modulator and the delay line of the pure light CT via a 2×1 coupler, and the polarization direction of the polarizer in the original optical path of the pure light CT is defined as 0°. The second return port of the 2×1 coupler is connected to a 1×3 coupler, and the three same-side ports of the 1×3 coupler are respectively connected to a 90° polarizer, a 45° polarizer and a 1 / 4 wave plate, to establish the output light intensities of the 0° polarizer, the 90° polarizer, the 45° polarizer and the 1 / 4 wave plate, respectively.

7. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 1 is characterized in that: The axis angle simulation unit is connected to the sensing optical fiber ring through a delay line.

8. The pure optical CT core chip fault tolerance algorithm evaluation test system according to claim 1 is characterized in that: The chip control signal abnormality simulation unit controls the clock, set signal, Ready bit abnormality signal, FPGA self-test completion signal abnormality, and closed-loop control logic program abnormality of the A / D conversion and the D / A conversion individually or in combination.

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