Anti-interference PAL external synchronization video display control method based on contract synchronization (CSYNC)

Abstract

The application relates to a PAL external synchronization video display control method based on a composite synchronization CSYNC and capable of resisting interference, and belongs to the technical field of development of logic gate arrays in aerospace and the like, and image transmission and video superposition of airborne pod display control components. An EP4CE115F23I7 FPGA is used as a master control in the application, only CYSNC composite synchronization signals generated by an EL1883 line field separation chip are analyzed, and a pixel clock PCLK, 8-bit pixel data PIX_DATA, a line synchronization hsync and a filed signal for indicating an odd and even field are generated, which are required for driving a physical layer video encoder GM7121. The method only needs to configure a small part of registers of the encoder GM7121, generates a timing sequence conforming to BT.656, and then superposes stable video generated by a control box on an airborne display screen. The hardware circuit design adopted in the application is low in cost, and the FPGA logic software can be upgraded flexibly to adapt to various picture scenes on the machine. The application makes the display control of the airborne equipment applicable to more different scenes, the control is more flexible, the video transmission is stronger in interference resistance, and the hardware cost is lower.

Description

Technical Field

[0001] This invention belongs to the field of logic gate array development in aerospace and other fields, and the field of image transmission and video overlay technology for airborne pod display and control components. In particular, it relates to the field of synchronous display control of airborne pod images and videos, specifically a PAL external synchronous video display control method based on composite synchronous CSYNC to achieve anti-interference. Background Technology

[0002] The video images displayed by the onboard equipment are extremely important for the coordinated operation of the equipment and for giving instructions to the operators. The personnel on board judge the next operation based on the peripheral buttons on the display screen and the central analog video screen, which involves the overlay and external synchronization control of local video and external video.

[0003] Currently, airborne analog video uses the PAL standard. Video overlay refers to the external video control equipment overlaying PAL analog video onto the central area of ​​the airborne display screen, while the perimeter of the screen displays simulated images generated locally by the display control components. This technology enables the display of specific video images in the central area by operating the peripheral buttons on the screen; therefore, it involves the external synchronization control method of PAL analog video.

[0004] Traditional PAL external synchronization display control schemes include using DSP processors or FPGAs to analyze horizontal and vertical separation chips to generate horizontal synchronization HSYNC and vertical synchronization VSYNC signals to ensure that the local video encoding timing is consistent with the timing generated by the airborne display and control, seamlessly embedding external analog video into the airborne display and control screen. However, the electromagnetic environment on board is complex, and the analog signals generated by the display and control components often need to be routed over long distances via cables to reach the external control box equipment. Therefore, they are highly susceptible to electromagnetic interference, resulting in distortion of the quality and timing of the analog image signal. Thus, implementing interference-resistant PAL external synchronization video display control technology is particularly important. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] The technical problem to be solved by the present invention is to provide a PAL external synchronous video display control method that can achieve anti-interference.

[0007] (II) Technical Solution

[0008] To address the aforementioned technical problems, this invention provides a PAL external synchronization video display control method based on composite synchronization CSYNC to achieve anti-interference. This method is implemented using a line and field separation chip EL1883, an FPGA, and an image encoder GM7121. The FPGA receives the CSYNC synchronization timing signal generated by the EL1883 and performs logic filtering and parsing on the CSYNC synchronization timing signal to obtain the pixel drive clock PCLK, 8-bit pixel data PIX_DATA, line synchronization signal hsync, and odd / even field indicator field control signal required to drive the GM7121. The CSYNC synchronization timing signal is referred to as CSYNC. The GM7121 performs DAC conversion of the encoded data. The FPGA also implements the BT.656 timing driven in external synchronization mode through a finite state machine. The finite state machine implemented by the FPGA includes an encoder state machine and a CSYNC timing state machine. The encoder state machine is used to control the BT.656 encoding process, and the CSYNC timing state machine is used to control the desynchronization process of CSYNC.

[0009] (III) Beneficial Effects

[0010] This invention uses an EP4CE115F23I7 FPGA as the main controller, only parsing the CYSNC composite synchronization signal generated by the EL1883 horizontal and vertical separation chip to generate the pixel clock PCLK, 8-bit pixel data PIX_DATA, and horizontal synchronization hsync and odd / even field indication field signals required to drive the physical layer video encoder GM7121. This method requires only configuring a small portion of the encoder GM7121 registers, generating timing conforming to BT.656, thereby stably superimposing the video generated by the control box onto the airborne display screen. The hardware circuit design used in this invention is low-cost and allows for flexible upgrades of the FPGA logic software to adapt to various onboard display scenarios. This invention enables the display control of airborne equipment to be applicable to more diverse scenarios, providing more flexible control, stronger anti-interference capabilities for video transmission, and lower hardware costs. Attached Figure Description

[0011] Figure 1 This is a block diagram of a scheme for implementing the anti-interference PAL external synchronous video display control method based on composite synchronous CSYNC according to the present invention;

[0012] Figure 2 This is a flowchart of the CSYNC timing state machine designed in this invention;

[0013] Figure 3 This is a flowchart of the encoder algorithm for a PAL external synchronous video display control method based on composite synchronous CSYNC to achieve anti-interference. Detailed Implementation

[0014] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0015] This invention provides a display control method for overlaying video with an externally input CVBS video analog source, based on the INTERSIL EL1883 horizontal and vertical separation chip, an EP4CE115F23I7 FPGA logic gate array, and a GM7121 physical encoder chip.

[0016] This invention provides a PAL external synchronous video display control method based on composite synchronization CSYNC to achieve anti-interference. This method is implemented using the EL1883 horizontal and vertical separation chip, an FPGA, and a GM7121 image encoder. (Reference) Figure 1 The FPGA receives the CSYNC synchronization timing signal (hereinafter referred to as CSYNC) generated by the EL1883 and performs logic filtering and parsing on the CSYNC synchronization timing signal to obtain the pixel drive clock PCLK, 8-bit pixel data PIX_DATA, line synchronization signal hsync, and parity field indicator field control signal required to drive the GM7121. The GM7121 performs DAC conversion of the encoded data. The FPGA also implements the BT.656 timing driven in external synchronization mode through a finite state machine. The finite state machine implemented by the FPGA includes an encoder state machine and a CSYNC timing state machine. The encoder state machine is used to control the BT.656 encoding process, and the CSYNC timing state machine is used to control the desynchronization process of CSYNC. The key design points are explained below.

[0017] 1. The FPGA receives the CSYNC synchronization timing signal generated by the EL1883.

[0018] The EL1883 can analyze both PAL and NTSC analog signals. The specific analog signal it analyzes depends entirely on its external input; there is no hardware difference between the two. The EL1883 is powered by a single 5V supply. Its inputs are a CVBS analog synchronization signal (voltage swing range: 0.5–2V), a timing configuration pin Rset (680KΩ resistance to ground, 1% accuracy), and an Rf pin used for pre-filtering the analog video source signal. The EL1883 can output horizontal synchronization HSYNC, vertical synchronization VSYNC, and a composite video synchronization signal, namely the CSYNC synchronization timing signal. In this invention, the FPGA only receives the CSYNC synchronization timing signal and compares its phase and period with the CVBS analog synchronization signal input to the EL1883 from the external airborne display and control system. When the phase difference between the two is constant and their periods are consistent, it proves that the EL1883 has successfully separated the external synchronization signal required by the FPGA.

[0019] 2. The FPGA performs logic filtering and analysis on the CSYNC synchronization timing signal.

[0020] Because the CVBS analog synchronization signal emitted by the airborne display and control system has a long cable route on the aircraft, it is susceptible to electromagnetic interference signals superimposed on the normal signal. Therefore, it is necessary for the FPGA to perform software logic filtering on the CSYNC synchronization timing signal output by the EL1883.

[0021] Analysis using a spectrum analyzer in the laboratory revealed that the interference pulse width superimposed on the CSYNC synchronization timing signal was less than 100ns, and this interference was unavoidable in hardware, belonging to random interference. Therefore, a 5-step filtering process was implemented on the FPGA with reference to a 27MHz clock cycle: if the CSYNC synchronization timing signal was 1 within 5 steps, then the effective level of the CSYNC synchronization timing signal was determined to be 1; if the CSYNC synchronization timing signal was logic 0 within 5 steps, then the effective value of the current CSYNC synchronization timing signal was determined to be 0; if the CSYNC synchronization timing signal experienced level fluctuations within 5 steps, these were treated as glitches, i.e., the logic value of the CSYNC synchronization timing signal in the previous state was maintained to ensure the accuracy of the CSYNC synchronization timing signal.

[0022] Parsing the CSYNC synchronization timing signal refers to the FPGA determining, based on the timing characteristics of the CSYNC synchronization timing signal (CSYNC high-level pulse width), which field, row, and column of the video encoder in the current airborne display and control system is encoding. Based on this pixel information, it generates the row synchronization signal (hsync), the odd / even field indicator (field control signal), and the 27MHz pixel drive clock (PCLK) recognized by the GM7121. The CSYNC synchronization timing signal is an LVTTL signal composed of pulses with different pulse widths and duty cycles. Different high-level pulse widths reflect different stages of encoding by the upstream video encoder. According to CCIR... In the BT.656 image transmission protocol, lines 624-625 are the back shoulder of even-field blanking, lines 1-22 are the front shoulder of odd-field blanking, lines 23-310 are the effective image coding lines for odd-field, lines 311-312 are the back shoulder of odd-field blanking; lines 313-335 are the front shoulder of even-field blanking, and lines 336-623 are the effective image coding lines for even-field.

[0023] The timing characteristics of the CSYNC synchronization timing signal refer to the following: Assuming T represents the duration of one cycle of a 27MHz clock, Wh represents the high-level pulse width of the CSYNC synchronization timing signal, and Wl represents the low-level interval of the CSYNC synchronization timing signal, then:

[0024] (1) When encoding lines 1 to 2.5, the timing characteristics are: Wh = 144T, Wl = 720T;

[0025] (2) When encoding lines 2.5 to 5, the timing characteristics are: Wh = 720T, Wl = 144T;

[0026] (3) When encoding lines 6 to 310, the timing characteristics are: Wh = 1440T, Wl = 288T;

[0027] (4) When encoding lines 311 to 312.5, the timing characteristics are: Wh = 720T, Wl = 144T;

[0028] (5) When encoding lines 312.5 to 315, the timing characteristics are: Wh = 144T, Wl = 720T;

[0029] (6) When encoding lines 316 to 317, the timing characteristics are: Wh = 720T, Wl = 144T;

[0030] (7) When encoding lines 318 to 622, the timing characteristics are: Wh = 1440T, Wl = 288T;

[0031] In response to the aforementioned timing characteristics of the CSYNC synchronization signal, and considering that the CSYNC synchronization signal may be affected by electromagnetic noise during transmission, resulting in glitches and delays, a high-level pulse width range is set for the CSYNC synchronization signal at each stage of the upstream video encoder in the FPGA. A counter implemented in the FPGA is used for detection. As long as the filtered CSYNC synchronization signal is within the range set for each stage, the CSYNC timing state machine will run normally. By running the CSYNC timing state machine normally, the horizontal synchronization signal hsync and the odd / even field indication field control signal (field flag signal) driving the GM7121 can be obtained.

[0032] Based on the different timing characteristics (different high-level pulse widths) of the CSYNC synchronization timing signal, the current stage of image encoding by the upstream video encoder is identified. In this invention, the working stage of the video encoder of the upstream airborne display and control system is divided into the following 23 stages, which operate under the control of the CSYNC synchronization timing signal to ensure that the timing of the downstream GM7121 is consistent with that of the upstream airborne display and control system, as detailed below:

[0033] (1) CSYNC_IDLE stage: The initial state of the CSYNC timing state machine, used to assign initial values ​​to the hsync and field control signals;

[0034] (2) WAIT_FOR_LINE1 stage: In this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies Wh>1200T (approximately the encoding time width of 1 line);

[0035] (3) LINE1_1 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T<Wh<600T (much smaller than the coding time width of a half line);

[0036] (4) LINE1_2 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T<Wh<600T (much smaller than the coding time width of a half line);

[0037] (5) LINE2_1 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T<Wh<600T (much smaller than the coding time width of a half line);

[0038] (6) LINE2_2 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T<Wh<600T (much smaller than the coding time width of a half line);

[0039] (7) LINE3_1 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T<Wh<600T (much smaller than the coding time width of a half line);

[0040] (8) LINE3_2 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T<Wh<1200T (approximately equal to the coding time width of a half line);

[0041] (9) LINE4_1 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T<Wh<1200T (approximately equal to the coding time width of a half line);

[0042] (10) LINE4_2 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T<Wh<1200T (approximately equal to the coding time width of a half line);

[0043] (11) LINE5_1 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T<Wh<1200T (approximately equal to the coding time width of a half line);

[0044] (12) LINE5_2 stage: in this stage, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T<Wh<1200T (approximately equal to the coding time width of a half line);

[0045] (13) WAIT_FOR_LINE313: in this stage, the high-level pulse width of CSYNC of the synchronous timing signal satisfies Wh>1200T (approximately the coding time width of one line);

[0046] (14) LINE313_1 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T < Wh < 1200T (approximately equal to the encoding time width of a half line);

[0047] (15) LINE313_2 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T < Wh < 600T (much smaller than the encoding time width of a half line);

[0048] (16) LINE314_1 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T < Wh < 600T (much smaller than the encoding time width of a half line);

[0049] (17) LINE314_2 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T < Wh < 600T (much smaller than the encoding time width of a half line);

[0050] (18) LINE315_1 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T < Wh < 600T (much smaller than the encoding time width of a half line);

[0051] (19) LINE315_2 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 100T < Wh < 600T (much smaller than the encoding time width of a half line);

[0052] (20) LINE316_1 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T < Wh < 1200T (approximately the encoding time width of a half line);

[0053] (21) LINE316_2 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T < Wh < 1200T (approximately the encoding time width of a half line);

[0054] (22) LINE317_1 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T < Wh < 1200T (approximately the encoding time width of a half line);

[0055] (23) LINE317_2 phase: In this phase, the high-level pulse width of the CSYNC synchronous timing signal satisfies 600T < Wh < 1200T (approximately the encoding time width of a half line);

[0056] 3. Register configuration of the image encoder GM7121

[0057] Image encoder configuration refers to the FPGA configuring the registers of the GM7121's internal operating mode via the I2C interface (400K baud rate). Specifically, the registers that need to be configured are: 0x3A (image encoder master / slave mode, configured as 03h slave mode), 0x5B (U component gain control, configured as 21h), 0x5C (V component gain control, configured as AFh), 0x5D (black level gain control, configured as 0x0E), 0x61 (image encoder output video standard, configured as 06h, PAL standard), 0x63~0x66 (subcarrier frequency selection: configured as CBh, 8Ah, 09h, 2Ah), 0x6B (RCV port configuration, configured as 60h, 7121 receives horizontal sync (hsync) and field flag (field) signals), 0x6C, 0x6D, and 0x75 (horizontal and vertical trigger positions of the image, both configured as 00h). The remaining registers are non-critical and do not require configuration.

[0058] 4. FPGA-based finite state machine-based generation of BT.656 timings driven in external synchronization mode.

[0059] The BT.656 timing refers to the FPGA transmitting timing consistent with the image encoding protocol, enabling the GM7121 to reliably receive data and achieve the expected DAC conversion effect. For standard definition PAL format encoding, with a resolution of 720*576, a YCbCr (4:2:2) encoding format is required. Each pixel is described by two luminance components Y1 and Y2, and a chrominance component CbCr. This means that the Cb-Y1-Cr-Y2 pixel group signal is generated within four pixel clock cycles (pcLK). Therefore, each row requires 1440 chrominance and luminance pixel information. Including the time for line blanking, encoding one row of image requires a total of 1728 PCLK cycles. This invention uses the variable Pixels to count the pcLK index within the current row, serving as the column index for the current encoding. However, the scanning of a PAL format image frame consists of: even field scan lines (288) + odd field scan lines (288) + field blanking lines (49). Therefore, in this invention, the variable Lines (maximum 625) is used as the line index for the current encoding.

[0060] Furthermore, this invention uses three variables—START_PIXEL, LINE_1ST, and LINE_313TH—generated by the CSYNC synchronization timing signal through the internal logic processing of the FPGA to determine the row encoding start point, the odd and even field encoding start point, and their respective encoding end points of the encoder state machine. At the same time, the GM7121 is driven by counting using the synchronization code to achieve strict timing synchronization with the analog video signal provided by the airborne display and control system.

[0061] The system processor in this design uses TI's TMS320F28377 to receive image and video commands from the host computer and control the lower-level computer. The image processing main control chip is ALTERA's EP4CE115F23I7 chip, which is used to configure the encoding chip, receive and process the composite synchronization signal CSYNC, and implement the BT656 encoding state machine. The line and field separation chip uses EL1883 to generate the composite synchronization CSYNC. The physical layer encoder chip uses Chengdu Zhenxin's GM7121 to realize the DAC conversion of the encoded data.

[0062] The I2C bus in this design conforms to the Philips standard and is a simple, bidirectional two-wire synchronous serial bus (SCL, SDA). Data is updated on SDA when SCL is low, and reliable sampling is possible during the high level of SCL. The interface circuit is an open-drain output, and both the master and slave devices have control over the bus. A typical write operation involves three stages: (sending the destination device address - sending the device's internal register address - writing the register configuration content). Each stage requires nine I2C clock cycles. In the ninth clock cycle of each stage, the master releases bus control (high impedance state) and switches to the slave to generate an ACK response. In this embodiment, the FPGA sequentially provides configuration data for certain registers of the GM7121 via the I2C bus and performs readbacks of certain critical registers to ensure successful configuration.

[0063] The GM7121 used in this design is a physical layer encoder chip compatible with the BT656 transmission protocol. It integrates an I2C slave interface to obtain configuration data from the host to determine the operating mode (external synchronization, receiving horizontal synchronization (hsync) and odd / even field signals from the host). The output of the GM7121 is typically paired with an SGM9111 video driver to enhance the driving capability of the 7121's DAC video signal to the aviation connector.

[0064] like Figure 1 The diagram shown is a block diagram of a PAL external synchronous video display control method based on composite synchronization CSYNC to achieve anti-interference.

[0065] In this embodiment, the system processor uses TI's TMS320F28377 to receive image and video commands from the host computer and control the display on the slave computer. The image processing main control chip uses ALTERA's EP4CE115F23I7 chip to configure the encoding chip, receive and process the synchronization signal of the EL1883 horizontal and vertical oscillator chip, and implement the BT656 algorithm. The horizontal and vertical oscillator chip uses EL1883 to generate the external synchronization signal CSYNC. The encoder chip uses GM7121 to perform DAC conversion of the encoded data and amplifies and drives the analog signal through SGM9111, thereby enabling the airborne host computer equipment to flexibly control the pod display screen.

[0066] like Figure 2 The diagram shown is a flowchart of the CSYNC timing state machine.

[0067] Based on the 23 different timing characteristics of the CSYNC synchronization timing signal, this design identifies 23 different stages in which the encoder of the current airborne display and control system is working. The work completed in each stage and the state transition conditions are clearly shown in the flowchart.

[0068] like Figure 3 The figure shows the encoder algorithm flowchart of a PAL external synchronous video display control method based on composite synchronization CSYNC to achieve anti-interference.

[0069] Specifically, the encoder state machine needs to encode the following states:

[0070] (1) IDLE state: Complete pixel row and column pointer initialization, default value initialization of all pixels in the image, GM7121 configuration, synchronization processing of CSYNC generated by EL1883, de-scratching, filtering and initialization;

[0071] (2) WORK state: detect the start point of line encoding START_PIXEL, the first line encoding flag LINE_1ST, the third line encoding flag LINE_313TH, and the line pointer increment trigger condition.

[0072] (3) EAV state (Pixels <= 4): End (not started) synchronization code state, including:

[0073] Output even field blanking end synchronization code EAV1 = 8'hB6;

[0074] Output even field data end synchronization code EAV2 = 8'h9D;

[0075] Output even-field blanking front shoulder end synchronization code EAV3 = 8'hB6;

[0076] Output the post-shoulder synchronization code EAV4=8'hF1 after the end of odd-field blanking;

[0077] Output the synchronization code EAV5=8'hDA at the end of odd-field data;

[0078] Output the pre-shoulder synchronization code EAV6=8'hF1 before the end of odd-field blanking;

[0079] (4) VBLANKING state (pixel pointer 4<Pixels≤284): horizontal blanking state, comprising:

[0080] Output the filling code BLANK_ODD=8'h10 for odd pixel positions in the horizontal blanking area;

[0081] Output the filling code BLANK_EVEN=8'h80 for even pixel positions in the horizontal blanking area;

[0082] (5) SAV state (pixel pointer 284<Pixels≤288): start synchronization code state, comprising:

[0083] Start synchronization code SAV1=8'hAB for the post-shoulder of even-field blanking;

[0084] Start synchronization code SAV2=8'h80 for even-field data;

[0085] Start synchronization code SAV3=8'hAB for the pre-shoulder of even-field blanking;

[0086] Start synchronization code SAV4=8'hEC for the post-shoulder of odd-field blanking;

[0087] Start synchronization code SAV5=8'hC7 for odd-field data;

[0088] Start synchronization code SAV6=8'hEC for the pre-shoulder of odd-field blanking;

[0089] (6) DATA state (pixel pointer 288<Pixels≤1728): frame data encoding state, comprising:

[0090] Chrominance component Cb encoding state: EVEN;

[0091] Luminance component Y1 encoding state: Y_DATA1;

[0092] Chrominance component Cr encoding state: ODD;

[0093] Luminance component Y2 encoding state: Y_DATA2;

[0094] (7) END state: the end state after completing the scanning of one frame with two fields, which will jump back to the WORK state and circularly refresh the encoded frame continuously.

[0095] Once the 27M pixel clock pclk generated by the FPGA's internal PLL is locked, and the I2C configuration timing for the GM7121 has been completed, the START_ENCODING flag signal is pulled high to trigger the GM7121 to operate. The specific process is as follows:

[0096] Step 1: The encoder state machine implemented in the FPGA is in the IDLE state. The pixel pointer Pixels = 0 and the line pointer Lines = 0 are initialized. The GM7121 data state is in the blanking end code state EAV by default. When START_ENCODING = 1, jump to step 2.

[0097] Step 2: The encoder state machine is in the WORK state. When START_PIXEL = 1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data 8'hFF is printed. In addition, within the same clock cycle of pclk, it is necessary to check whether the first row flag LINE_1ST is pulled high. If it is not pulled high, it means that the external analog source input state is abnormal or the EL1883 parsing is abnormal. At this time, the row pointer should remain unchanged from the previous state, and the GM7121 is driven to give blanking black level data 8'h10. If LINE_1ST is already pulled high at this time, the row pointer is set to 1. The pixel pointer Pixels is continuously incremented by 1 on the falling edge of pclk. When the EAV state is (Pixels <= 4), the preamble codes 8'hff, 8'h00, 8'h00, and EAVx are generated respectively. When the pixel pointer Pixels > 4, jump to step 3.

[0098] Step 3: The encoder state machine enters the line blanking region. When the pixel pointer satisfies 5 <= Pixels <= 283, the padding code 8'h10 is generated when the value of the Pixels pointer is odd, and the padding code 8'h80 is generated when the value of the Pixels pointer is even. When the pixel pointer satisfies Pixels >= 284, jump to step 4.

[0099] Step 4: The encoder state machine enters the SAV state. Based on the number of lines currently encoded, it enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, and odd field data start SAV5 states respectively. Similar to step 2, it generates the preamble: 8'hff, 8'h00, 8'h00, and SAVx. When the pixel indicator Pixels > 288, it jumps to step 5.

[0100] Step 5: The encoder state machine enters the data encoding DATA state. According to the YCbCr422 encoding format, it sequentially enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state. When the pixel pointer Pixels >= 1728 is detected, the data state transitions to EAV, the line index Lines is incremented by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When the current encoding line number is detected to be 625, the encoding of one frame of image has been completed. The data state datadone is pulled high, and the process jumps to step 2 again to determine whether the line pointer should remain at 2 or be set to 2 in the next cycle. This cycle continues, continuously refreshing the image to produce the video effect.

[0101] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A PAL external synchronous video display control method based on composite synchronization CSYNC to achieve anti-interference, characterized in that, This method is implemented based on the line and field separation chip EL1883, FPGA, and image encoder GM7121. The FPGA receives the CSYNC synchronization timing signal generated by the EL1883 and performs logic filtering and parsing on the CSYNC synchronization timing signal to obtain the pixel drive clock PCLK, 8-bit pixel data PIX_DATA, line synchronization signal hsync, and odd / even field indicator field control signal required to drive the GM7121. The CSYNC synchronization timing signal is referred to as CSYNC. The GM7121 implements DAC conversion of the encoded data. The FPGA also implements the BT.656 timing driven in external synchronization mode through a finite state machine. The finite state machine implemented by the FPGA includes an encoder state machine and a CSYNC timing state machine. The encoder state machine is used to control the encoding process of BT.656, and the CSYNC timing state machine is used to control the desynchronization process of CSYNC. Parsing the CSYNC synchronization timing signal means that the FPGA determines the field, row, and column of the video encoder of the current airborne display and control system based on the timing characteristics of the CSYNC synchronization timing signal, and generates the row synchronization signal hsync, the odd / even field indicator field control signal, and the 27MHz pixel drive clock PCLK that are recognized by the GM7121 based on this pixel information. The CSYNC synchronization timing signal is an LVTTL signal composed of pulses with different pulse widths and duty cycles. Different high-level pulse widths reflect the different stages that the video encoder is currently encoding. According to the CCIRBT.656 image transmission protocol, lines 624-625 are the back shoulder of even-field blanking, lines 1-22 are the front shoulder of odd-field blanking, lines 23-310 are the effective image coding lines for odd-field, lines 311-312 are the back shoulder of odd-field blanking; lines 313-335 are the front shoulder of even-field blanking, and lines 336-623 are the effective image coding lines for even-field. The timing characteristics of the CSYNC synchronization timing signal are as follows: assuming T represents the duration of one cycle of a 27MHz clock, Wh represents the high-level pulse width of the CSYNC synchronization timing signal, and Wl represents the low-level interval of the CSYNC synchronization timing signal, then: (1) The timing characteristics of encoding lines 1 to 2.5 are: Wh=144T, Wl=720T; (2) When encoding lines 2.5 to 5, the timing characteristics are: Wh=720T, Wl=144T; (3) When encoding lines 6 to 310, the timing characteristics are: Wh=1440T, Wl=288T; (4) When encoding lines 311 to 312.5, the timing characteristics are: Wh=720T, Wl=144T; (5) When encoding lines 312.5 to 315, the timing characteristics are: Wh=144T, Wl=720T; (6) When encoding lines 316-317, the timing characteristics are: Wh=720T, Wl=144T; (7) When encoding lines 318 to 622, the timing characteristics are: Wh=1440T, Wl=288T; In the FPGA, a high-level pulse width range is set for the CSYNC synchronization timing signal at each stage of the video encoder. The counter implemented by the FPGA detects this range. As long as the filtered CSYNC synchronization timing signal is within the range set for each stage, the CSYNC timing state machine will run normally. The horizontal synchronization signal hsync and the odd / even field indication control signal field are obtained by running the CSYNC timing state machine normally. Based on the different timing characteristics of the CSYNC synchronization timing signal, the current stage of image encoding by the video encoder is identified. The working stages of the airborne display and control system's video encoder are divided into the following 23 stages, which operate under the control of the CSYNC synchronization timing signal to ensure that the timing of the GM7121's operation is consistent with that of the airborne display and control system, as detailed below: (1) CSYNC_IDLE stage: The initial state of the CSYNC timing state machine, used to assign initial values ​​to the hsync and parity field indicator control signals; (2) WAIT_FOR_LINE1 stage: During this stage, the high-level pulse width of the CSYNC synchronization timing signal satisfies Wh>1200T; (3) LINE1_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (4) LINE1_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (5) LINE2_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (6) LINE2_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (7) LINE3_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (8) LINE3_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (9) LINE4_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (10) LINE4_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (11) LINE5_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (12) LINE5_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (13) WAIT_FOR_LINE313: The pulse width of the high level of the CSYNC synchronization signal in this stage satisfies Wh>1200T; (14) LINE313_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (15) LINE313_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (16) LINE314_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (17) LINE314_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (18) LINE315_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (19) LINE315_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 100T <Wh<600T; (20) LINE316_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (21) LINE316_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (22) LINE317_1 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; (23) LINE317_2 stage: The high-level pulse width of the CSYNC synchronization timing signal in this stage meets 600T <Wh<1200T; The FPGA configures the registers for the internal operating modes of the GM7121 via the I2C interface. Specifically, the registers that need to be configured are: 0x3A: Master-slave mode for the image encoder, configured as 03h (slave mode); 0x5B: U component gain control, configured as 21h; 0x5C: V component gain control, configured as AFh; 0x5D: Black level gain control, configured as 0x0E; 0x61: Image encoder output video standard, configured as 06h (PAL standard); 0x63~0x66: Subcarrier frequency selection, configured as CBh, 8Ah, 09h, 2Ah; 0x6B: RCV port configuration, configured as 60h; 7121 receives horizontal synchronization (hsync) and field flag (field) signals; 0x6C, 0x6D, 0x75: Horizontal and vertical trigger positions for the image, all configured as 00h. The BT.656 timing driven by the FPGA in the external synchronization mode generated by the finite state machine refers to the FPGA issuing timing signals consistent with the image encoding protocol to enable the GM7121 to reliably receive data and achieve the expected DAC conversion effect; for standard definition PAL format encoding, the resolution is 720.

576. Each pixel is described by two luminance components Y1 and Y2 and a chrominance component CbCr. That is, the Cb-Y1-Cr-Y2 pixel group signal is generated within 4 pixel clock cycles (pclk). Therefore, each row needs to provide 1440 chrominance and luminance pixel information. Including the time occupied by line blanking, encoding one row of image requires a total of 1728 PCLK cycles. The variable Pixels is used to count the pclk index in the current row, which is used as the column index for the current encoding. However, the scan of a frame of PAL image consists of: the number of even field scan rows + the number of odd field scan rows + the number of field blanking rows. Therefore, the variable Lines is used as the row index for the current encoding. The three variables START_PIXEL, LINE_1ST, and LINE_313TH, generated by the CSYNC synchronization timing signal through the internal logic processing of the FPGA, are used to determine the row encoding start point, the odd and even field encoding start point, and their respective encoding end points of the encoder state machine. At the same time, the GM7121 is driven by the synchronization code to achieve strict timing synchronization with the analog video signal given by the airborne display and control system. The encoder state machine needs to encode the following states: (1) IDLE state: Complete the initialization of pixel row and column pointers, the initialization of default values ​​for all pixels in the image, the configuration of GM7121, the synchronization processing of CSYNC generated by EL1883, de-scratching, filtering and initialization; (2) WORK state: detect the line coding start point START_PIXEL, the first line coding flag LINE_1ST, the 313th line coding flag LINE_313TH and the line pointer increment trigger condition; (3) When pixel pointer Pixels<=4, it is EAV state: end of synchronization code state, which includes: Output the end synchronization code EAV1 = 8'hB6 for the trailing shoulder of even field blanking; Output the end synchronization code EAV2 = 8'h9D for even field data; Output the end synchronization code EAV3 = 8'hB6 for the leading shoulder of even field blanking; Output the end synchronization code EAV4 = 8'hF1 for the trailing shoulder of odd field blanking; Output the end synchronization code EAV5 = 8'hDA for odd field data; Output the end synchronization code EAV6 = 8'hF1 for the leading shoulder of odd field blanking; (4) When pixel pointer 4 < Pixels <= 284, it is VBLANKING state: line blanking state, which includes: Output the fill code BLANK_ODD = 8'h10 for odd pixel positions in the line blanking area; Output the fill code BLANK_EVEN = 8'h80 for even pixel positions in the line blanking area; (5) When pixel pointer 284 < Pixels <= 288, it is SAV state: start of synchronization code state, which includes: The start synchronization code SAV1 = 8'hAB for the trailing shoulder of even field blanking; The start synchronization code SAV2 = 8'h80 for even field data; The start synchronization code SAV3 = 8'hAB for the leading shoulder of even field blanking; The start synchronization code SAV4 = 8'hEC for the trailing shoulder of odd field blanking; The start synchronization code SAV5 = 8'hC7 for odd field data; The start synchronization code SAV6 = 8'hEC for the leading shoulder of odd field blanking; (6) When pixel pointer 288 < Pixels <= 1728, it is DATA state: picture data coding state, which includes: Chrominance component Cb coding state: EVEN; Luminance component Y1 coding state: Y_DATA1; Chrominance component Cr coding state: ODD; Luminance component Y2 coding state: Y_DATA2; (7) END state: the scanning end state after completing 1 frame with 2 fields of the picture, which will jump back to the WORK state and continuously cycle to refresh the coded picture; When the 27M pixel clock pclk generated by the internal PLL of FPGA is locked, and the I2C configuration timing for GM7121 has been completed, the START_ENCODING flag signal is pulled high to trigger GM7121 to work, and the specific process is as follows: Step 1: the encoder state machine implemented in FPGA is in IDLE state, initialize pixel pointer Pixels=0, line pointer Lines=0, the default data state of GM7121 is the blanking end code state EAV, when START_ENCODING=1, jump to step 2; Step 2: The encoder state machine is in the WORK state. When START_PIXEL=1 is detected, the pixel column pointer Pixels is set to 11'd1, and the first pixel data 8'hFF is printed. In addition, within the same clock cycle of pclk, the first row flag LINE_1ST is checked to see if it is pulled high. If it is not pulled high, it means that the external analog source input state is abnormal or the EL1883 parsing is abnormal. At this time, the row pointer remains unchanged, and the GM7121 is driven to give blanking black level data 8'h10. If LINE_1ST is already pulled high, the row pointer is set to 1. The pixel pointer Pixels is continuously incremented by 1 on the falling edge of pclk. When Pixels<=4, the EAV state generates preambles: 8'hff, 8'h00, 8'h00, and EAVx respectively. When the pixel pointer Pixels>4, the process jumps to step 3. Step 3: The encoder state machine enters the line blanking region. When the pixel pointer satisfies 5 <= Pixels <= 283, the padding code 8'h10 is generated when the value of the Pixels pointer is odd, and the padding code 8'h80 is generated when the value of the Pixels pointer is even. When the pixel pointer satisfies Pixels >= 284, jump to step 4. Step 4: The encoder state machine enters the SAV state and, based on the number of lines currently encoded, enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, and odd field data start SAV5 states respectively, generating preambles: 8'hff, 8'h00, 8'h00, and SAVx. When the pixel indicator Pixels > 288, it jumps to step 5. Step 5: The encoder state machine enters the data encoding DATA state. According to the YCbCr422 encoding format, it sequentially enters the EVEN state, Y_DATA1 state, ODD state, and Y_DATA2 state. When the pixel pointer Pixels >= 1728 is detected, the data state transitions to EAV, the line index Lines is incremented by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When the current encoding line number is detected to be 625, the encoding of one frame of image has been completed. The data state datadone is pulled high, and the process jumps to step 2 to determine whether the line pointer should remain or be set to 2 in the next cycle. This cycle continues, continuously refreshing the image to produce a video effect.

2. The method as described in claim 1, characterized in that, The FPGA only receives the CSYNC synchronization timing signal and compares the phase and period of the CSYNC synchronization timing signal with the CVBS analog synchronization signal input to the EL1883 from the external airborne display and control system. When the phase difference between the two is constant and the period is consistent, it proves that the EL1883 has successfully separated the external synchronization signal required by the FPGA.

3. The method as described in claim 1, characterized in that, The FPGA uses a 27MHz clock cycle for 5-step filtering: if the CSYNC synchronization signal is 1 within 5 steps, then the effective level of the CSYNC synchronization signal is determined to be 1; if the CSYNC synchronization signal is logic 0 within 5 steps, then the effective value of the current CSYNC synchronization signal is determined to be 0; if the CSYNC synchronization signal experiences level fluctuations within 5 steps, they are treated as glitches, i.e., the logic value of the CSYNC synchronization signal in the previous state is maintained.

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