Manufacturing method of memory device

Abstract

The invention discloses a manufacturing method of a memory device, and the method comprises the steps: providing a substrate which comprises a first region, a second region and a third region, forming a first polycrystalline silicon layer on a pad oxide layer of the first region, forming a second polycrystalline silicon layer above the first polycrystalline silicon layer, forming a third polycrystalline silicon layer on the pad oxide layer of the second region, and forming a second polycrystalline silicon layer above the third polycrystalline silicon layer; a fourth polycrystalline silicon layer is formed on the pad oxide layer in the third region; sequentially forming an etching protection layer and a cap layer on the second polycrystalline silicon layer, the third polycrystalline silicon layer and the fourth polycrystalline silicon layer; removing the etching protection layer and the cap layer in the second region and the third region; forming a first groove in the first region, forming a second groove in the second region, and forming a third groove in the third region; forming an isolation layer on the peripheral sides of the storage unit, the grid electrode of the first logic device and the grid electrode of the second logic device; forming an interlayer dielectric layer; and forming a through hole of the contact hole.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for manufacturing a memory device. Background Art

[0002] Non-volatile memory (NVM) is a widely used information storage device that stores 0 / 1 information by storing charges on a floating gate (FG). It also has good resistance to magnetic interference when there is no power maintenance.

[0003] In NVM memory, the NOR flash memory is developed based on the ETOX structure proposed by Intel. It is a voltage-controlled device that uses hot electron injection to write data and erases data based on the tunnel effect. Its notable feature is that it has a fast random read speed. As a NVM memory, NOR flash memory has the characteristics of high device density, low power consumption and electrical rewritability. It is widely used in electronic products with storage functions such as smart phones, tablet computers, digital cameras, and universal serial bus flash disks (USB flash disks, referred to as "U disks")

[0004] Typically, an array of memory cell devices and a peripheral circuit of logic devices are integrated on a substrate for integrating NOR flash memory. During the manufacturing process of NOR flash memory, during the etching process of self-aligned contact holes (SAC), a high etching selectivity ratio of nitride / oxide is required. If the etching selectivity of nitride / oxide is relatively low, it is easy to cause the nitride cap layer above the control gate (CG) of the memory cell to be chamfered, thereby causing a bridge between the contact hole and the control gate formed subsequently; if the etching selectivity of nitride / oxide is relatively high, it will lead to incomplete etching, affecting subsequent filling. Summary of the invention

[0005] The present application provides a method for manufacturing a memory device, which can solve the problem that the method for manufacturing a memory device provided in the related art is easy to cause the control gate to be exposed during the through-hole etching process of the contact hole, thereby affecting the reliability and yield. The method comprises:

[0006] A substrate is provided, wherein the region of the substrate used for forming a semiconductor device comprises a first region, a second region and a third region, the first region is used for forming a memory cell device, the second region is used for forming a first logic device, and the third region is used for forming a second logic device, a pad oxide layer is formed on the substrate, a first polysilicon layer is formed on the pad oxide layer of the first region, a second polysilicon layer is formed above the first polysilicon layer, a first isolation layer is formed between the first polysilicon layer and the second polysilicon layer, a third polysilicon layer is formed on the pad oxide layer of the second region, and a fourth polysilicon layer is formed on the pad oxide layer of the third region;

[0007] forming an etching protection layer on the second polysilicon layer, the third polysilicon layer and the fourth polysilicon layer;

[0008] forming a cap layer on the etching protection layer;

[0009] Removing the etching protection layer and the cap layer from the second region and the third region;

[0010] Performing etching to form a first trench in the first region, a second trench in the second region, and a third trench in the third region, wherein the substrate at the bottom of the first trench is exposed, the substrate at the bottom of the second trench is exposed, and the substrate at the bottom of the third trench is exposed, and the remaining first polysilicon layer forms a floating gate of a memory cell, the remaining second polysilicon layer forms a control gate of the memory cell, the remaining third polysilicon layer forms a gate of a first logic device, and the remaining fourth polysilicon layer forms a gate of a second logic device;

[0011] forming a second isolation layer on the periphery of the memory cell, forming a third isolation layer on the periphery of the gate of the first logic device, and forming a fourth isolation layer on the periphery of the gate of the second logic device;

[0012] forming an interlayer dielectric layer, wherein the height of the interlayer dielectric layer is higher than the second isolation layer, the third isolation layer and the fourth isolation layer;

[0013] Etching is performed to form a first through hole in the first trench, a second through hole in the second trench, and a third through hole in the third trench, the substrate at the bottom of the first through hole is exposed, the substrate at the bottom of the second through hole is exposed, and the substrate at the bottom of the third through hole is exposed, and the first through hole, the second through hole and the third through hole are used to form a contact hole.

[0014] In some embodiments, the etch protection layer includes an oxide layer.

[0015] In some embodiments, the cap layer includes a nitride layer.

[0016] In some embodiments, a thickness of the liner oxide layer in the second region is greater than a thickness of the liner oxide layer in the first region and a thickness of the liner oxide layer in the third region.

[0017] In some embodiments, before forming the interlayer dielectric layer, the method further includes:

[0018] A fifth isolation layer is formed, the fifth isolation layer covering the memory cell, the first logic device, and the second logic device.

[0019] The technical solution of this application has at least the following advantages:

[0020] In the process of manufacturing the memory device, before forming the cap layer of the memory cell device, an etching protection layer is formed on the control gate polysilicon layer, and then subsequent gate etching, isolation layer formation, interlayer dielectric layer filling and contact hole etching are carried out. Since the etching protection layer is formed on the control gate, the probability of corner cutting can be reduced while ensuring a high etching selectivity, thereby improving the reliability and yield of the device to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 is a flow chart of a method for manufacturing a memory device provided by an exemplary embodiment of the present application;

[0023] Figures 2 to 7 It is a schematic diagram of a manufacturing process of a memory device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0026] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0027] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0028] Step S1, providing a substrate, the substrate including a first region, a second region and a third region for forming a semiconductor device, the first region for forming a storage unit device, the second region for forming a first logic device, and the third region for forming a second logic device, a pad oxide layer is formed on the substrate, a first polysilicon layer is formed on the pad oxide layer of the first region, a second polysilicon layer is formed above the first polysilicon layer, a first isolation layer is formed between the first polysilicon layer and the second polysilicon layer, a third polysilicon layer is formed on the pad oxide layer of the second region, and a fourth polysilicon layer is formed on the pad oxide layer of the third region.

[0029] Step S2, forming an etching protection layer on the second polysilicon layer, the third polysilicon layer and the fourth polysilicon layer.

[0030] Step S3, forming a cap layer on the etching protection layer.

[0031] refer to Figure 2 , which shows a cross-sectional schematic diagram after the cap layer is formed. Figure 2As shown, the region of the substrate 210 used to form the semiconductor device includes a first region 201, a second region 202 and a third region 203. The first region 201 is used to form a memory cell device, the second region 202 is used to form a first logic device, and the third region 203 is used to form a second logic device. The first logic device and the second logic device can be devices with different operating voltages. A pad oxide (pad oxide) is formed on the substrate 210. The first region 201 has a first polysilicon layer 2311 formed on the pad oxide layer 221, a second polysilicon layer 232 formed on the first polysilicon layer 2311, a first isolation layer (the isolation layer may be an oxide-nitride-oxide (ONO) layer, which includes an oxide layer 2221, a nitride layer 2222 and an oxide layer 2223 from bottom to top) is formed between the first polysilicon layer 2311 and the second polysilicon layer 232, a third polysilicon layer 2312 is formed on the pad oxide layer 222 of the second region 202, and a fourth polysilicon layer 2313 is formed on the pad oxide layer 223 of the third region 203. The second polysilicon layer 232, the third polysilicon layer 2312 and the fourth polysilicon layer 2313 are thin film layers of the same level formed by the same deposition process.

[0032] The etching protection layer 230 includes an oxide layer, and the cap layer 240 includes a nitride layer; the thickness of the pad oxide layer 222 of the second region 202 is greater than the thickness of the pad oxide layer 223 of the third region 203. A first doping region 2011 (which can be used as a well region of a memory cell device) is formed in the substrate 210 of the first region 201, a second doping region 2012 (which can be used as a well region of a memory cell device) is formed in the first doping region 2011, and a third doping region 2013 (which can be used as a cell voltage (CVT) region) is formed in the second doping region 2012; a fourth doping region 2021 (which can be used as a well region of a first logic device) is formed in the substrate 210 of the second region 201; and a fifth doping region 2031 (which can be used as a well region of a second logic device) is formed in the substrate 210 of the third region 203.

[0033] Step S4, removing the etching protection layer and the cap layer in the second area and the third area.

[0034] refer to Figure 3 , which shows a cross-sectional schematic diagram after removing the etching protection layer and the cap layer in the second region and the third region. Figure 3 As shown, the etching protection layer 230 and the cap layer 240 in the second region 202 and the third region 203 may be removed by dry etching and / or wet etching.

[0035] In step S5, etching is performed to form a first trench in the first area, a second trench in the second area, and a third trench in the third area. The substrate at the bottom of the first trench is exposed, the substrate at the bottom of the second trench is exposed, and the substrate at the bottom of the third trench is exposed. The remaining first polysilicon layer forms a floating gate of the memory cell, the remaining second polysilicon layer forms a control gate of the memory cell, the remaining third polysilicon layer forms a gate of the first logic device, and the remaining fourth polysilicon layer forms a gate of the second logic device.

[0036] refer to Figure 4 , which shows a cross-sectional schematic diagram after forming the first trench, the second trench and the third trench. Figure 4 As shown, the substrate 210 can be covered with photoresist, and the photoresist of the target area (the area corresponding to the first trench 301, the second trench 302 and the third trench 303) can be removed by exposure and development, and etching is performed to form the first trench 301 in the first area 201, the second trench 302 in the second area 202, and the third trench 303 in the third area 203. The substrate 210 at the bottom of the first trench 301 is exposed, the substrate 210 at the bottom of the second trench 302 is exposed, and the substrate 210 at the bottom of the third trench 303 is exposed. The remaining first polysilicon layer 2311 forms the floating gate of the storage unit, the remaining second polysilicon layer 232 forms the control gate of the storage unit, the remaining third polysilicon layer 2312 forms the gate of the first logic device, and the remaining fourth polysilicon layer 2313 forms the gate of the second logic device. Among them, a group of adjacent floating gates and control gates can be used as a storage unit.

[0037] Step S6, forming a second isolation layer around the memory cell, forming a third isolation layer around the gate of the first logic device, and forming a fourth isolation layer around the gate of the second logic device.

[0038] refer to Figure 5 , which shows a cross-sectional schematic diagram after forming the second isolation layer, the third isolation layer and the fourth isolation layer. Figure 5 As shown, the second isolation layer includes an oxide layer 251, a nitride layer 252 and an oxide layer 253 from the inside to the outside, and the outermost oxide layer 253 of the storage unit can be removed by etching. The third isolation layer includes an oxide layer 251, a nitride layer 252 and an oxide layer 253 from the inside to the outside, and the fourth isolation layer includes an oxide layer 251, a nitride layer 252 and an oxide layer 253 from the inside to the outside.

[0039] Exemplarily, before forming the second isolation layer, the third isolation layer and the fourth isolation layer, a lightly doped drain (LDD) region 2014 may be formed in the substrate 210 on both sides of the memory device and in the substrate 210 between two columns of floating gates in the memory device, a sixth doping region 2016 and a seventh doping region 2015 may be formed in the substrate 210 between two columns of floating gates in the memory device, and the LDD region 2014 is located in the seventh doping region 2015, and a heavily doped region 2020 may be formed in the substrate 210 on both sides of the memory device, the first logic device and the second logic device, and the impurity concentration doped in the heavily doped region 2020 is greater than the impurity concentration of other doping regions. Optionally, a metal silicide layer 260 may be formed in the heavily doped region 2020 and in the gate of the first logic device and the gate of the second logic device.

[0040] Step S7, forming an interlayer dielectric layer, wherein the height of the interlayer dielectric layer is higher than the second isolation layer, the third isolation layer and the fourth isolation layer.

[0041] Exemplarily, after forming the second isolation layer, the third isolation layer and the fourth isolation layer, a fifth isolation layer may be formed to cover the second isolation layer, the third isolation layer and the fourth isolation layer, referring to Figure 6 , which shows a cross-sectional schematic diagram after forming a fifth isolation layer and an interlayer dielectric (ILD) layer 270, as shown Figure 6 As shown, the fifth isolation layer includes an oxynitride layer 254 and a nitride layer 255 from bottom to top. The nitride layer 255 between the memory cells and the logic devices can be removed by etching, and the interlayer dielectric layer 270 may include an oxide layer.

[0042] In step S8, etching is performed to form a first through hole in the first trench, a second through hole in the second trench, and a third through hole in the third trench. The substrate at the bottom of the first through hole is exposed, the substrate at the bottom of the second through hole is exposed, and the substrate at the bottom of the third through hole is exposed. The first through hole, the second through hole, and the third through hole are used to form a contact hole.

[0043] refer to Figure 7 , which shows a cross-sectional schematic diagram after forming the first through hole, the second through hole and the third through hole. Figure 7 As shown, after the first through hole 3011, the second through hole 3012 and the third through hole 3013 are formed, due to the presence of the etching protection layer 230, an etching process with a relatively large etching selection can be used for etching, while ensuring the etching completion, it can effectively avoid the corner defect that causes the control gate 232 to be exposed (such as Figure 7 (shown by the dashed line).

[0044] To summarize, in the embodiments of the present application, during the manufacturing process of the memory device, before forming the cap layer of the memory cell device, an etching protection layer is formed on the control gate polysilicon layer, and then subsequent gate etching, isolation layer formation, interlayer dielectric layer filling and contact hole etching are performed. Since the etching protection layer is formed on the control gate, the probability of corner cutting can be reduced while ensuring a high etching selectivity, thereby improving the reliability and yield of the device to a certain extent.

[0045] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a memory device, characterized in that: include: A substrate is provided, wherein the region of the substrate used for forming a semiconductor device comprises a first region, a second region and a third region, the first region is used for forming a memory cell device, the second region is used for forming a first logic device, and the third region is used for forming a second logic device, a pad oxide layer is formed on the substrate, a first polysilicon layer is formed on the pad oxide layer of the first region, a second polysilicon layer is formed above the first polysilicon layer, a first isolation layer is formed between the first polysilicon layer and the second polysilicon layer, a third polysilicon layer is formed on the pad oxide layer of the second region, and a fourth polysilicon layer is formed on the pad oxide layer of the third region; forming an etching protection layer on the second polysilicon layer, the third polysilicon layer and the fourth polysilicon layer; forming a cap layer on the etching protection layer; Removing the etching protection layer and the cap layer from the second region and the third region; Performing etching to form a first trench in the first region, a second trench in the second region, and a third trench in the third region, wherein the substrate at the bottom of the first trench is exposed, the substrate at the bottom of the second trench is exposed, and the substrate at the bottom of the third trench is exposed, and the remaining first polysilicon layer forms a floating gate of a memory cell, the remaining second polysilicon layer forms a control gate of the memory cell, the remaining third polysilicon layer forms a gate of a first logic device, and the remaining fourth polysilicon layer forms a gate of a second logic device; forming a second isolation layer on the periphery of the memory cell, forming a third isolation layer on the periphery of the gate of the first logic device, and forming a fourth isolation layer on the periphery of the gate of the second logic device; forming an interlayer dielectric layer, wherein the height of the interlayer dielectric layer is higher than the second isolation layer, the third isolation layer and the fourth isolation layer; Etching is performed to form a first through hole in the first trench, a second through hole in the second trench, and a third through hole in the third trench, the substrate at the bottom of the first through hole is exposed, the substrate at the bottom of the second through hole is exposed, and the substrate at the bottom of the third through hole is exposed, and the first through hole, the second through hole and the third through hole are used to form a contact hole.

2. The method according to claim 1, characterized in that The etching protection layer includes an oxide layer.

3. The method according to claim 2, characterized in that The cap layer includes a nitride layer.

4. The method according to claim 3, characterized in that The thickness of the pad oxide layer in the second region is greater than the thickness of the pad oxide layer in the first region and the thickness of the pad oxide layer in the third region.

5. The method according to any one of claims 1 to 4, characterized in that: Before forming the interlayer dielectric layer, the method further comprises: A fifth isolation layer is formed, the fifth isolation layer covering the memory cell, the first logic device, and the second logic device.

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