GaN HEMT (High Electron Mobility Transistor) with strong non-clamping inductive switching capability in irradiation scene and preparation method thereof

Abstract

The invention provides a GaN HEMT (High Electron Mobility Transistor) with strong non-clamping inductive switching capability in an irradiation scene and a preparation method thereof, and belongs to the technical field of semiconductors. Comprising a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and an electrode structure layer, the electrode structure layer comprises a grid electrode structure, a source electrode structure and a drain electrode structure, the source electrode structure and the drain electrode structure are arranged on the two sides of the grid electrode structure, the grid electrode structure is in a strip shape and arranged above the barrier layer in the first direction, and the source electrode structure and the drain electrode structure are connected with the channel layer; a plurality of rectangular P-type gallium nitride layers arranged in groups are arranged between the grid electrode structure and the drain electrode structure, the plurality of rectangular P-type gallium nitride layers arranged in groups are uniformly arranged at intervals along a first direction and are connected through a metal wire, the top of the metal wire is connected with a negative potential electrode, and an area between the potential barrier layer and the negative potential electrode is filled with a dielectric layer. The technical problems that the normal switching capability of a device is affected and the overvoltage robustness is degraded due to hole accumulation after irradiation of a traditional HEMT can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios and a preparation method thereof. Background Art

[0002] In recent years, GaN power electronic devices represented by high electron mobility transistors (HEMTs) and the power systems they constitute have been widely used in aerospace, nuclear detection, special military equipment, etc., due to the advantages of GaN materials such as high breakdown voltage, high critical breakdown field strength, high saturated carrier mobility, high thermal conductivity, high power quality factor, and good radiation tolerance. GaN HEMTs must achieve fast switching capabilities, and fast switching in power systems may lead to the generation of instantaneous strong voltage pulses, which requires power devices to have robustness under strong instantaneous overvoltage pulses.

[0003] Among the related technologies, the Unclamped Inductive Switching (UIS) test can effectively simulate the overvoltage conditions in actual switching scenarios and is currently a common test for the overvoltage robustness of power electronic devices. In addition, in extremely special working environments such as space stations and nuclear power plants, power electronic devices and electronic systems are exposed to radiation scenarios induced by space heavy ions, protons, neutrons, x-rays, gamma rays and other particles for a long time. The HEMT device is easily stimulated by radiation and generates a large number of excess carriers, which causes the normal switching capability of the device and its overvoltage robustness to be seriously affected and degraded, and even threatens the safe operation of the entire electronic system. Summary of the invention

[0004] The present invention provides a GaN HEMT with strong non-clamped inductive switching capability under irradiation and a preparation method thereof. The present invention can solve the technical problem in the prior art that the normal switching capability and overvoltage robustness degradation of the device are affected by hole accumulation after irradiation in the conventional HEMT. The technical solution is as follows: In the first aspect, the present invention provides a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios, comprising a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and an electrode structure layer arranged from bottom to top, the electrode structure layer comprising a gate structure and a source structure and a drain structure arranged on both sides of the gate structure, the gate structure is strip-shaped and arranged above the barrier layer along a first direction, the source structure and the drain structure are both connected to the channel layer, a plurality of rectangular P-type gallium nitride layers arranged in groups are arranged between the gate structure and the drain structure, the plurality of rectangular P-type gallium nitride layers arranged in groups are evenly spaced along the first direction and connected at the top by metal wires, a negative potential electrode is connected to the top of the metal wire, and a dielectric layer is filled in the area between the barrier layer and the negative potential electrode.

[0005] Optionally, multiple groups of the rectangular P-type gallium nitride layers are disposed between the gate structure and the drain structure, and the multiple groups of the rectangular P-type gallium nitride layers are arranged at uniform intervals in a second direction perpendicular to the first direction. Optionally, front metal and rear metal arranged in the second direction are respectively disposed at two ends of multiple groups of the rectangular P-type gallium nitride layers in the first direction, and the multiple groups of the rectangular P-type gallium nitride layers are respectively connected to the front metal and the rear metal through the metal wires to form an interdigital structure, and the front metal and the rear metal are connected to the negative potential electrode.

[0006] Optionally, between adjacent two groups of the rectangular P-type gallium nitride layers, a connection line between the rectangular center of any one of the rectangular P-type gallium nitride layers and the rectangular center of the rectangular P-type gallium nitride layer closest to it in the other group is arranged at an angle with the second direction. Optionally, the range of the length L of the rectangular P-type gallium nitride layer in the first direction is 0 < L < 100 μm, the range of the width W of the rectangular P-type gallium nitride layer in the second direction is 1 < W < 100 μm, and the range of the spacing Lp between adjacent rectangular P-type gallium nitride layers in each group of the rectangular P-type gallium nitride layers is L < Lp < 100 μm.

[0007] Optionally, the source structure includes a source ohmic metal layer, a source top metal layer, and a source arranged from bottom to top, the drain structure includes a drain ohmic metal layer, a drain top metal layer, and a drain arranged from bottom to top, and the top height of the metal wire is lower than the bottom height of the drain top metal layer.

[0008] Optionally, in the first direction, the front metal and the rear metal are respectively located on both sides of the drain top metal layer. Optionally, the width range of the front metal and the rear metal in the first direction is 10 to 50 μm.

[0009] Optionally, the dielectric layer is a silicon dioxide, silicon nitride, or aluminum oxide layer. In a second aspect, an embodiment of the present invention provides a preparation method for manufacturing the GaN HEMT with strong non-clamping inductive switching ability in the irradiation scenario described in the first aspect above, including: Step 1: The epitaxial wafer sequentially grows the substrate layer, the gallium nitride layer, the passivation layer, the channel layer, the barrier layer, and the dielectric layer from bottom to top; Step 2: Etch and deposit the source structure and the drain structure connected to the channel layer on the barrier layer; Step 3: etching and depositing the gate structure and the plurality of rectangular P-type gallium nitride layers between the gate structure and the drain structure on the dielectric layer; Step 4: depositing Schottky metal on the plurality of rectangular P-type gallium nitride layers to obtain the metal wires; Step 5: Continue to deposit a dielectric layer on the entire device, and etch and deposit a negative potential electrode connected to the metal wire above the multiple rectangular P-type gallium nitride layers. The beneficial effects brought about by the technical solution provided by the present invention include at least: The GaN HEMT with strong non-clamped inductive switching capability under irradiation scenario provided by the present invention is used. By distributing a plurality of orderly arranged rectangular P-type gallium nitride layers in the region between the drain structure and the gate structure, holes generated under irradiation, especially holes generated between the rectangular P-type gallium nitride layer and the drain structure, can flow through the gaps between the plurality of rectangular P-type gallium nitride layers, thereby avoiding damage to the conductive channel of the transistor after the region of the P-type gallium nitride material is added, ensuring good conduction characteristics of the device, and by applying a negative potential bias on the negative potential electrodes arranged above the plurality of rectangular P-type gallium nitride layers, holes can be effectively discharged through the discharge channel formed by the plurality of rectangular P-type gallium nitride layers, the metal wire and the negative potential electrode. Furthermore, by additionally arranging a channel layer and a passivation layer between the barrier layer and the gallium nitride layer, a two-dimensional hole gas is generated at the connection between the passivation layer and the channel layer due to polarization. When a negative potential bias is applied to the upper rectangular P-type gallium nitride layer region, holes can be simultaneously conducted from below the barrier layer, helping the excess induced holes collected in the two-dimensional hole gas to be discharged from the channel, further improving the efficiency of hole discharge. The increase in the local electric field peak and the generation of leakage channels caused by the accumulation of holes near the gate structure are avoided, and the non-clamped inductive switching capability of the HEMT under irradiation scenarios is effectively improved. The technical problem in the prior art that the normal switching capability and overvoltage robustness degradation of the conventional HEMT due to hole accumulation after irradiation is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 is a schematic diagram of a conventional GaN HEMT device structure in the related art; Figure 2It is a schematic diagram of the steps of preparing a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and a dielectric layer of a GaN HEMT with strong non-clamped inductive switching capability under an irradiation scenario provided in an embodiment of the present invention; Figure 3 It is a schematic diagram of steps for preparing a source structure and a drain structure of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios in an embodiment of the present invention; Figure 4 It is a schematic diagram of steps for preparing a gate structure and a rectangular P-type gallium nitride layer of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios in an embodiment of the present invention; Figure 5 It is a schematic diagram of the steps of preparing metal wires of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios in an embodiment of the present invention; Figure 6 It is a schematic diagram of the steps of further preparing a source structure, a drain structure and a gate structure of a GaN HEMT having a strong non-clamped inductive switching capability under an irradiation scenario provided by an embodiment of the present invention; Figure 7 Schematic diagram of the preparation and etching holes of the GaN HEMT with strong non-clamped inductive switching capability under the irradiation scenario provided in the embodiment of the present invention; Figure 8 is a schematic diagram of a three-dimensional structure of a GaN HEMT having a strong non-clamped inductive switching capability under an irradiation scenario provided in an embodiment of the present invention; Fig. 9 It is a flow chart of the preparation method provided in an embodiment of the present invention.

[0012] In the figure: 1-substrate layer; 2-gallium nitride layer; 3-passivation layer; 4-channel layer; 5-barrier layer; 6-electrode structure layer; 7-dielectric layer; 61-gate structure; 62-source structure; 63-drain structure; 64-rectangular P-type gallium nitride layer; 65-metal wire; 66-negative potential electrode; 71-etched hole; 611-gate gallium nitride layer; 612-gate metal layer; 613-gate; 621-source ohmic metal layer; 622-source top metal layer; 623-source; 631-drain ohmic metal layer; 632-drain top metal layer; 633-drain; 641-front metal; 642-rear metal; 64a-first rectangular P-type gallium nitride layer group; 64b-second rectangular P-type gallium nitride layer group; m-conventional drain; n-conventional source; o-conventional gate. DETAILED DESCRIPTION In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0013] Figure 1FIG. 1 is a schematic diagram of a conventional GaN HEMT device structure in the related art. Figure 1 As shown, when the existing GaN HEMT is in operation, the conventional drain m is usually positively biased. When the GaN HEMT generates excess carrier electron-hole pairs under the irradiation scenario, the electrons can be discharged from the conventional drain m under the positive bias of the conventional drain m. However, the holes cannot be discharged because they cannot cross the potential barrier or the dielectric layer. They will accumulate in the area near the conventional gate o between the conventional source n and the conventional drain m, affecting the electric field distribution in this area, and may even form a conductive path near the conventional gate o. When the device is in a fast switching state, its overvoltage robustness will also be greatly reduced, and in severe cases, it may cause the transistor to lose its switching ability or even burn out completely.

[0014] Figure 2 It is a schematic diagram of the steps of preparing a substrate layer, a gallium nitride layer, a passivation layer, a channel layer, a barrier layer and a dielectric layer of a GaN HEMT with strong non-clamped inductive switching capability under an irradiation scenario provided in an embodiment of the present invention; Figure 3 It is a schematic diagram of steps for preparing a source structure and a drain structure of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios in an embodiment of the present invention; Figure 4 It is a schematic diagram of steps for preparing a gate structure and a rectangular P-type gallium nitride layer of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios in an embodiment of the present invention; Figure 5 It is a schematic diagram of the steps of preparing metal wires of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios in an embodiment of the present invention; Figure 6 It is a schematic diagram of the steps of further preparing a source structure, a drain structure and a gate structure of a GaN HEMT having a strong non-clamped inductive switching capability under an irradiation scenario provided by an embodiment of the present invention; Figure 7 Schematic diagram of the preparation and etching holes of the GaN HEMT with strong non-clamped inductive switching capability under the irradiation scenario provided in the embodiment of the present invention; Figure 8 It is a schematic diagram of the three-dimensional structure of a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios provided in an embodiment of the present invention.

[0015] like Figures 2 to 8As shown, based on the above defects, an embodiment of the present invention provides a GaN HEMT with strong non-clamped inductive switching capability under irradiation scenario, comprising a substrate layer 1, a gallium nitride layer 2, a passivation layer 3, a channel layer 4, a barrier layer 5 and an electrode structure layer 6 arranged from bottom to top, the electrode structure layer 6 comprises a gate structure 61 and a source structure 62 and a drain structure 63 arranged on both sides of the gate structure 61, the gate structure 61 is strip-shaped and arranged above the barrier layer 5 along a first direction, the source structure 62 and the drain structure 63 are both connected to the channel layer 4, a plurality of rectangular P-type gallium nitride layers 64 arranged in groups are arranged between the gate structure 61 and the drain structure 63, the plurality of rectangular P-type gallium nitride layers 64 arranged in groups are evenly spaced along the first direction and connected at the top by metal wires 65, a negative potential electrode 66 is connected at the top of the metal wires 65, and a dielectric layer 7 is filled in the area between the barrier layer 5 and the negative potential electrode 66.

[0016] In the embodiment of the present invention, when manufacturing the GaN HEMT with strong non-clamped inductive switching capability under the irradiation scenario, Figure 2 As shown, first, a 0.65 mm thick substrate layer 1, a 300 μm thick gallium nitride layer 2, a 30 nm thick passivation layer 3, a 100 μm thick channel layer 4, and a 60 nm thick barrier layer 5 are grown sequentially from bottom to top on the epitaxial wafer, and a whole 20 μm thick dielectric layer 7 is deposited on the barrier layer 5. Among them, the material of the passivation layer 3 and the barrier layer 5 is AlGaN, the material of the channel layer 4 is Si-doped n-type gallium nitride, and the material of the dielectric layer 7 is any one of silicon dioxide, silicon nitride or aluminum oxide, or a combination of two or more thereof, which plays the role of electrical isolation of the transistor structure.

[0017] Afterwards, refer to Figure 3 , the dielectric layer 7 and part of the barrier layer 5 are etched by inductively coupled plasma dry etching to etch out a deposition area for depositing ohmic metal, and ohmic metal is deposited therein to obtain a source structure 62 and a drain structure 63. Exemplarily, in an embodiment of the present invention, the source structure 62 includes a source ohmic metal layer 621, a source top metal layer 622 and a source 623 arranged from bottom to top, and the drain structure 63 includes a drain ohmic metal layer 631, a drain top metal layer 632 and a drain 633 arranged from bottom to top. In this step diagram, only the source ohmic metal layer 621 and the drain ohmic metal layer 631 located at the bottom layer are deposited respectively, and the length of both in the first direction is 300μm and the width in the second direction is 20μm, and the source ohmic metal layer 621 and the drain ohmic metal layer 631 form ohmic contact with the gallium nitride of the channel layer 4.

[0018] Afterwards, refer to Figure 4, the dielectric layer 7 is etched by inductively coupled plasma dry etching to etch out a deposition area for depositing and growing p-type gallium nitride, and a gate structure 61 and a plurality of neatly arranged rectangular p-type gallium nitride layers 64 are deposited therein. Exemplarily, in an embodiment of the present invention, the gate structure 61 includes a gate gallium nitride layer 611, a gate metal layer 612 and a gate 613 arranged from bottom to top. In this step diagram, only the bottom gate gallium nitride layer 611 is formed by successively depositing 10nm of Schottky metal Ni metal and 5μm thick Schottky metal Al.

[0019] Afterwards, refer to Figure 5 , Schottky metal is deposited on the deposited gate gallium nitride layer 611 to form a gate metal layer 612, thereby obtaining a complete gate structure 61, and Schottky metals are respectively deposited on multiple rectangular P-type gallium nitride layers 64 arranged in groups to obtain metal wires 65 that connect the multiple rectangular P-type gallium nitride layers 64 in series in the same group.

[0020] Afterwards, refer to Figure 6 , a 5 μm thick dielectric layer 7 is further deposited on the entire device by plasma enhanced chemical vapor deposition, with a thickness ranging from 100 to 300 μm, and metal is deposited on the source ohmic metal layer 621 and the drain ohmic metal layer 631 to obtain a source top metal layer 622 and a drain top metal layer 632 extending to the gate structure 61 but not covering the gate structure 61, both with a thickness of 5 μm, to form a field plate structure. Among them, the metal line 65 above the rectangular P-type gallium nitride layer 64 does not contact the bottom of the drain top metal layer 632 in the height direction, and a gap of 2 μm is retained.

[0021] Afterwards, refer to Figure 7 By plasma enhanced chemical vapor deposition, the dielectric layer 7 is continuously deposited on the entire device, and the dielectric layer is etched in the source top metal layer 622, the drain top metal layer 632, the gate metal layer 612 of the gate structure 61, and the metal line 65 to obtain a longitudinal etched hole 71, into which metal Al is deposited to form an interconnection structure. The diameter of the etched hole 71 is about 2μm.

[0022] Finally, reference Figure 8 , 10μm thick metal electrodes are deposited on different areas of the top surface of the deposited dielectric layer 7, so that the source top metal layer 622 is connected to the deposited source 623 through the upper interconnection metal, the gate metal layer 612 is connected to the deposited gate 613 through the interconnection metal, the drain top metal layer 632 is connected to the deposited drain 633 through the upper interconnection metal, and the metal wire 65 is connected to the negative potential electrode 66 deposited above the multiple rectangular P-type gallium nitride layers 64 through the interconnection metal, completing the manufacture of the device structure.

[0023] The GaN HEMT with strong non-clamped inductive switching capability under irradiation scenario provided by the embodiment of the present invention is used. By distributing a plurality of orderly arranged rectangular P-type gallium nitride layers 64 in the region between the drain structure 63 and the gate structure 61, holes generated by irradiation, especially holes generated between the rectangular P-type gallium nitride layer 64 and the drain structure 63, can flow through the gaps between the plurality of rectangular P-type gallium nitride layers 64, thereby avoiding damage to the conductive channel of the transistor after the region of the P-type gallium nitride material is added, ensuring good conduction characteristics of the device, and applying a negative potential bias on the negative potential electrode 66 arranged above the plurality of rectangular P-type gallium nitride layers 64, so that the holes can be effectively discharged through the discharge channel formed by the plurality of rectangular P-type gallium nitride layers 64, the metal wire 65 and the negative potential electrode 66. Furthermore, by additionally arranging a channel layer 4 and a passivation layer 3 between the barrier layer 5 and the gallium nitride layer 2, a two-dimensional hole gas is generated at the connection between the passivation layer 3 and the channel layer 4 due to polarization. When a negative potential bias is applied to the upper rectangular P-type gallium nitride layer 64 region, holes can be simultaneously conducted from below the barrier layer, helping the redundant induced holes collected in the two-dimensional hole gas to be discharged from the channel, further improving the efficiency of hole discharge. The increase in the local electric field peak and the generation of leakage channels caused by the accumulation of holes near the gate structure 61 are avoided, and the non-clamped inductive switching capability of the HEMT under irradiation scenarios is effectively improved. The technical problem in the prior art that the normal switching capability and overvoltage robustness degradation of the device are affected by the accumulation of holes after irradiation in the conventional HEMT is solved.

[0024] Preferably, a plurality of rectangular P-type gallium nitride layers 64 are arranged between the gate structure 61 and the drain structure 63, and the plurality of rectangular P-type gallium nitride layers 64 are evenly spaced along the second direction, and the second direction is perpendicular to the first direction. Exemplarily, in the embodiment of the present invention, five rectangular P-type gallium nitride layers 64 arranged in groups and spaced along the first direction are arranged in columns. The column closest to the drain structure 63 is the first column, and the columns are arranged in parallel and spaced toward the gate structure 61 in the second direction. The odd columns (i.e., columns 1, 3, and 5) are the first rectangular P-type gallium nitride layer group 64a; the even columns (i.e., columns 2 and 4) are the second rectangular P-type gallium nitride layer group 64b. By providing a plurality of rectangular P-type gallium nitride layers 64, a plurality of entrances for collecting and discharging holes are formed in the gate structure 61 and the drain structure 63, thereby improving the discharge efficiency of holes. At the same time, the vacant distance between the gate structure 61 and the drain structure 63 is prevented from being too far, so as to prevent the increase of the device area from affecting the normal performance of the transistor.

[0025] Preferably, the two ends of the multiple rectangular P-type gallium nitride layers 64 in the first direction are respectively provided with a front metal 641 and a rear metal 642 arranged along the second direction, and the multiple rectangular P-type gallium nitride layers 64 are respectively connected to the front metal 641 and the rear metal 642 through metal wires 65 to form a forked structure, and the front metal 641 and the rear metal 642 are connected to the negative potential electrode 66. Exemplarily, in the embodiment of the present invention, the first rectangular P-type gallium nitride layer group 64a is connected to the front metal 641 through the metal wire 65 arranged on the top surface, and the second rectangular P-type gallium nitride layer group 64b is connected to the rear metal 642 on the other side of the first direction through the metal wire 65 arranged on the top surface to form a forked structure. The etched hole 71 structure for connecting to the upper negative potential electrode 66 can be concentrated on the front metal 641 and the rear metal 642, avoiding the need to respectively set the etched holes 71 above the metal wires 65 of the multiple rectangular P-type gallium nitride layers 64 to connect to the negative potential electrode 66, and reducing the manufacturing difficulty through reasonable arrangement planning.

[0026] Exemplarily, in the embodiment of the present invention, the width of the front metal 641 and the rear metal 642 in the first direction ranges from 10 to 50 μm.

[0027] Furthermore, in the first direction, the front metal 641 and the rear metal 642 are respectively located on both sides of the drain top metal layer 632. In this way, the front metal 641 and the rear metal 642 are connected to the top negative potential electrode 66 without affecting the performance of the device. There is no need to etch the hole 71 above the rectangular P-type gallium nitride layer 64 arranged in groups, so the negative potential electrode can be enlarged without increasing the device area too much. Enlarging the negative potential electrode is beneficial to the subsequent packaging and testing of the transistor. Reducing the size of the device further increases the layout utilization rate of the transistor structure graphic area, which is beneficial to improving the induced charge extraction capability of the gallium nitride p-GaN enhancement transistor in the irradiation scenario.

[0028] Preferably, between two adjacent groups of rectangular P-type gallium nitride layers 64, a line connecting any rectangular P-type gallium nitride layer 64 and the rectangular center of the closest rectangular P-type gallium nitride layer 64 in the other group is arranged at an angle to the second direction. Exemplarily, in an embodiment of the present invention, an angle of 45° is formed between a line connecting any rectangular P-type gallium nitride layer 64 and the rectangular center of the closest rectangular P-type gallium nitride layer 64 in the other group and the second direction, the first rectangular P-type gallium nitride layer group 64a is composed of 5 rectangular P-type gallium nitride layers 64, and the second rectangular P-type gallium nitride layer group 64b is composed of 4 rectangular P-type gallium nitride layers 64, and the staggered arrangement can further improve the hole discharge efficiency.

[0029] Optionally, the length L of the rectangular P-type gallium nitride layer 64 in the first direction ranges from 0 < L < 100 μm, the width W of the rectangular P-type gallium nitride layer 64 in the second direction ranges from 1 < W < 100 μm, and the spacing Lp between adjacent rectangular P-type gallium nitride layers 64 in each group of rectangular P-type gallium nitride layers 64 ranges from L < Lp < 100 μm. Exemplarily, in the embodiment of the present invention, the width of a single rectangular P-type gallium nitride layer 64 in the second direction is 20 μm, the length in the first direction is 20 μm, in the same group, the spacing between two adjacent rectangular P-type gallium nitride layers 64 in the first direction is 40 μm, the distance between the gate structure 61 and the drain structure 63 is 160 μm, and the spacing between the first rectangular P-type gallium nitride layer group 64a and the adjacent second rectangular P-type gallium nitride layer group 64b is 10 μm.

[0030] Fig. 9 is a flowchart of the preparation method provided by the embodiment of the present invention. As Fig. 9 shown, the embodiment of the present invention also provides a preparation method for fabricating a GaN HEMT with strong non-clamped inductive switching ability under the irradiation scenario as Figures 1 to 8 shown, and the method includes the following steps: S1: An epitaxial wafer is sequentially grown with a substrate layer 1, a gallium nitride layer 2, a passivation layer 3, a channel layer 4, a barrier layer 5, and a dielectric layer 7 from bottom to top.

[0031] Specifically, first, a 0.65 mm thick substrate layer 1, a 300 μm thick gallium nitride layer 2, a 30 nm thick passivation layer 3, a 100 μm thick channel layer 4, a 60 nm thick barrier layer 5 are sequentially grown on the epitaxial wafer from bottom to top, and a 20 μm thick dielectric layer 7 is deposited as a whole layer on the barrier layer 5. Among them, the materials of the passivation layer 3 and the barrier layer 5 are AlGaN, the material of the channel layer 4 is Si-doped n-type gallium nitride, and the material of the dielectric layer 7 is any one or a combination of two or more of silicon dioxide, silicon nitride, or aluminum oxide, which plays an electrical isolation role for transistor structural components. S2: The source structure 62 and the drain structure 63 connected to the channel layer 4 are etched and deposited on the barrier layer 5.

[0032] Specifically, the dielectric layer 7 and part of the barrier layer 5 are etched by inductively coupled plasma dry etching to etch out a deposition area for depositing ohmic metal, and ohmic metal is deposited therein to obtain a source structure 62 and a drain structure 63. Exemplarily, in an embodiment of the present invention, the source structure 62 includes a source ohmic metal layer 621, a source top metal layer 622 and a source 623 arranged from bottom to top, and the drain structure 63 includes a drain ohmic metal layer 631, a drain top metal layer 632 and a drain 633 arranged from bottom to top. In this step diagram, only the source ohmic metal layer 621 and the drain ohmic metal layer 631 located at the bottom layer are deposited respectively, and the length of both in the first direction is 300 μm and the width in the second direction is 20 μm, and the source ohmic metal layer 621 and the drain ohmic metal layer 631 form ohmic contact with the gallium nitride of the channel layer 4. S3 : etching and depositing a gate structure 61 and a plurality of rectangular P-type gallium nitride layers 64 between the gate structure 61 and the drain structure 63 on the dielectric layer 7 .

[0033] Specifically, the dielectric layer 7 is etched by inductively coupled plasma dry etching to etch out a deposition area for depositing and growing p-type gallium nitride, and a gate structure 61 and a plurality of neatly arranged rectangular p-type gallium nitride layers 64 are deposited therein. Exemplarily, in an embodiment of the present invention, the gate structure 61 includes a gate gallium nitride layer 611, a gate metal layer 612 and a gate 613 arranged from bottom to top. In this step diagram, only the bottom gate gallium nitride layer 611 is formed by successively depositing 10 nm of Schottky metal Ni metal and 5 μm thick Schottky metal Al. S4 : depositing Schottky metal on the plurality of rectangular P-type gallium nitride layers 64 to obtain metal lines 65 .

[0034] Specifically, Schottky metal is deposited on the deposited gate gallium nitride layer 611 to form a gate metal layer 612, thereby obtaining a complete gate structure 61, and Schottky metals are respectively deposited on multiple rectangular P-type gallium nitride layers 64 arranged in groups to obtain metal wires 65 that connect the multiple rectangular P-type gallium nitride layers 64 in series in the same group.

[0035] S5 : Continue to deposit the dielectric layer 7 on the entire device, and etch and deposit the negative potential electrode 66 connected to the metal line 65 above the plurality of rectangular P-type gallium nitride layers 64 .

[0036] Specifically, a 5 μm thick dielectric layer 7 is continuously deposited on the entire device by plasma enhanced chemical vapor deposition, with a thickness ranging from 100 to 300 μm, and metal is deposited on the source ohmic metal layer 621 and the drain ohmic metal layer 631 to obtain a source top metal layer 622 and a drain top metal layer 632 extending to the gate structure 61 but not covering the gate structure 61, both with a thickness of 5 μm, to form a field plate structure. Among them, the metal line 65 above the rectangular P-type gallium nitride layer 64 does not contact the bottom of the drain top metal layer 632 in the height direction, and a gap of 2 μm is retained.

[0037] Afterwards, the dielectric layer 7 is continuously deposited on the entire device by plasma enhanced chemical vapor deposition, and the dielectric layer is etched in the source top metal layer 622, the drain top metal layer 632, the gate metal layer 612 of the gate structure 61, and the metal line 65 to obtain a longitudinal etched hole 71, into which metal Al is deposited to form an interconnection structure. The diameter of the etched hole 71 is about 2μm. Finally, 10 μm thick metal electrodes are deposited on different areas of the top surface of the deposited dielectric layer 7, so that the source top metal layer 622 is connected to the deposited source 623 through the upper interconnection metal, the gate metal layer 612 is connected to the deposited gate 613 through the interconnection metal, the drain top metal layer 632 is connected to the deposited drain 633 through the upper interconnection metal, and the metal wire 65 is connected to the negative potential electrode 66 deposited above the multiple rectangular P-type gallium nitride layers 64 through the interconnection metal, thereby completing the manufacture of the device structure.

[0038] The GaN HEMT with strong non-clamped inductive switching capability under irradiation scenarios manufactured by the preparation method provided by the embodiment of the present invention, by distributing a plurality of orderly arranged rectangular P-type gallium nitride layers 64 in the region between the drain structure 63 and the gate structure 61, enables holes generated by irradiation, especially holes generated between the rectangular P-type gallium nitride layer 64 and the drain structure 63, to flow through the gaps between the plurality of rectangular P-type gallium nitride layers 64, thereby avoiding damage to the conductive channel of the transistor after the region of the P-type gallium nitride material is added, ensuring good conduction characteristics of the device, and by applying a negative potential bias on the negative potential electrode 66 arranged above the plurality of rectangular P-type gallium nitride layers 64, the holes can be effectively discharged through the discharge channel formed by the plurality of rectangular P-type gallium nitride layers 64, the metal wire 65 and the negative potential electrode 66. Furthermore, by additionally arranging a channel layer 4 and a passivation layer 3 between the barrier layer 5 and the gallium nitride layer 2, a two-dimensional hole gas is generated at the connection between the passivation layer 3 and the channel layer 4 due to polarization. When a negative potential bias is applied to the upper rectangular P-type gallium nitride layer 64 region, holes can be simultaneously conducted from below the barrier layer, helping the redundant induced holes collected in the two-dimensional hole gas to be discharged from the channel, further improving the efficiency of hole discharge. The increase in the local electric field peak and the generation of leakage channels caused by the accumulation of holes near the gate structure 61 are avoided, and the non-clamped inductive switching capability of the HEMT under irradiation scenarios is effectively improved. The technical problem in the prior art that the normal switching capability and overvoltage robustness degradation of the device are affected by the accumulation of holes after irradiation in the conventional HEMT is solved.

[0039] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar words used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] The above descriptions are merely optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios, characterized in that: It includes a substrate layer (1) arranged from bottom to top, a gallium nitride layer (2), a passivation layer (3), a channel layer (4), a barrier layer (5), and an electrode structure layer (6). The electrode structure layer (6) includes a gate structure (61), a source structure (62), and a drain structure (63) arranged on both sides of the gate structure (61). The gate structure (61) is strip-shaped and arranged above the barrier layer (5) along a first direction. The source structure (62) and the drain structure (63) are both connected to the channel layer (4). A plurality of rectangular P-type gallium nitride layers (64) arranged in groups are provided between the gate structure (61) and the drain structure (63). The plurality of rectangular P-type gallium nitride layers (64) arranged in groups are evenly spaced along the first direction and are connected at the top by a metal wire (65). A negative potential electrode (66) is connected to the top of the metal wire (65). The region between the barrier layer (5) and the negative potential electrode (66) is filled with a dielectric layer (7).

2. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios according to claim 1, characterized in that: A plurality of groups of the rectangular P-type gallium nitride layers (64) are provided between the gate structure (61) and the drain structure (63). The plurality of groups of the rectangular P-type gallium nitride layers (64) are evenly spaced along a second direction, and the second direction is perpendicular to the first direction.

3. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios according to claim 2, characterized in that: Front metals (641) and rear metals (642) arranged along the second direction are respectively provided at both ends of the plurality of groups of the rectangular P-type gallium nitride layers (64) in the first direction. The plurality of groups of the rectangular P-type gallium nitride layers (64) are respectively connected to the front metals (641) and the rear metals (642) through the metal wire (65) to form an interdigital structure, and the front metals (641) and the rear metals (642) are connected to the negative potential electrode (66).

4. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios according to claim 2, characterized in that: Between two adjacent groups of the rectangular P-type gallium nitride layers (64), the connection line between the rectangular center of any one of the rectangular P-type gallium nitride layers (64) and the rectangular center of the rectangular P-type gallium nitride layer (64) closest to it in the other group is arranged at an angle with the second direction.

5. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenario according to claim 2, characterized in that: The length L of the rectangular P-type gallium nitride layer (64) in the first direction ranges from 0 < L < 100 μm, the width W of the rectangular P-type gallium nitride layer (64) in the second direction ranges from 1 < W < 100 μm, and the spacing Lp between adjacent rectangular P-type gallium nitride layers (64) in each group of the rectangular P-type gallium nitride layers (64) ranges from L < Lp < 100 μm.

6. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenario according to claim 3, characterized in that: The source structure (62) includes a source ohmic metal layer (621), a source top metal layer (622), and a source (623) arranged from bottom to top. The drain structure (63) includes a drain ohmic metal layer (631), a drain top metal layer (632), and a drain (633) arranged from bottom to top. The top height of the metal wire (65) is lower than the bottom height of the drain top metal layer (632).

7. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios according to claim 6, characterized in that: In the first direction, the front metal (641) and the rear metal (642) are respectively located on both sides of the drain top metal layer (632).

8. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios according to claim 7, characterized in that: The width of the front metal (641) and the rear metal (642) in the first direction ranges from 10 to 50 μm.

9. The GaN HEMT with strong unclamped inductive switching capability under irradiation scenarios according to any one of claims 1 to 8, characterized in that: The dielectric layer (7) is a silicon dioxide, silicon nitride or aluminum oxide layer.

10. A method for manufacturing a GaN HEMT having a strong non-clamped inductive switching capability under irradiation scenarios as claimed in any one of claims 1 to 8, characterized in that: include: Step 1: growing the substrate layer (1), the gallium nitride layer (2), the passivation layer (3), the channel layer (4), the barrier layer (5) and the dielectric layer (7) in sequence from bottom to top on an epitaxial wafer; Step 2: etching and depositing the source structure (62) and the drain structure (63) connected to the channel layer (4) on the barrier layer (5); Step 3: etching and depositing the gate structure (61) and the plurality of rectangular P-type gallium nitride layers (64) located between the gate structure (61) and the drain structure (63) on the dielectric layer (7); Step 4: depositing Schottky metal on the plurality of rectangular P-type gallium nitride layers (64) to obtain the metal wire (65); Step 5: Continue to deposit a dielectric layer (7) on the entire device, and etch and deposit a negative potential electrode (66) connected to the metal line (65) above the plurality of rectangular P-type gallium nitride layers (64).

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