Shield gate MOSFET device and preparation method thereof

Abstract

The invention discloses a shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof. The device comprises a substrate; a semiconductor body; the semiconductor body comprises a drift region, a body region and a first active region; first grooves are formed in the two sides of the semiconductor body in the thickness direction perpendicular to the substrate; a source structure; the source structure is in contact with the first active region; a barrier dielectric layer, a shield gate dielectric layer and a shield gate; the upper surface of the barrier dielectric layer is flush with the upper surface of the isolation dielectric layer in the thickness direction of the substrate; and a control gate structure and a drain. The shield gate MOSFET device can effectively prevent hot carriers from being injected into the shield gate dielectric layer under the action of an electric field between the shield gate and the drift region when the shield gate MOSFET device is reversely broken down.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shielded gate MOSFET device and a preparation method thereof. Background Art

[0002] Shielded gate power metal oxide semiconductor field effect transistor (MOSFET) uses its shield gate as an "internal field plate" to reduce the electric field in the drift region, which can obtain a good compromise between the on-resistance and breakdown voltage of the shielded gate MOSFET device. In addition, the shielded gate electrode connected to the source potential can also reduce the gate-drain capacitance Cgd of the device and increase the switching speed of the device. Therefore, shielded gate MOSFET devices have gradually become the mainstream devices in the field of low-voltage power MOSFET devices.

[0003] During reverse breakdown, there is a high electric field in the drift region of the shielded gate MOSFET device, especially near the bottom of the drift region, which is prone to generate hot carriers. Since there is a potential difference between the shielded gate electrode and the drift region, the hot carriers will be injected into the shielded gate dielectric layer under the action of the electric field between the shielded gate electrode and the drift region, thereby changing the potential of the shielded gate dielectric layer, and then affecting the lateral depletion of the drift region by the shielding gate, resulting in poor reliability problems such as reduced breakdown voltage or unstable breakdown voltage of the shielded gate MOSFET device. Summary of the invention

[0004] The present invention provides a shielded gate MOSFET device and a preparation method thereof, so as to solve the problem of poor reliability of the shielded gate MOSFET device, such as reduced breakdown voltage or unstable breakdown voltage, caused by hot carrier injection into the shielded gate dielectric layer.

[0005] In a first aspect, the present invention provides a shielded gate MOSFET device, wherein the shielded gate MOSFET device comprises:

[0006] substrate;

[0007] A semiconductor body; the semiconductor body is located on one side of the substrate, and the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; first grooves are provided on both sides of the semiconductor body in a thickness direction perpendicular to the substrate;

[0008] A source structure, the source structure is located at a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region;

[0009] A blocking dielectric layer, a shielding gate dielectric layer and a shielding gate, wherein the blocking dielectric layer is located at the bottom and sidewalls of a first groove, the shielding gate dielectric layer is located in the first groove and is located on a side of the blocking dielectric layer away from the substrate, the shielding gate dielectric layer is provided with a second groove, and the shielding gate is located in the second groove; the interface hole barrier height between the blocking dielectric layer and the drift region is greater than the interface hole barrier height between the shielding gate dielectric layer and the drift region; and / or the interface electron barrier height between the blocking dielectric layer and the drift region is greater than the interface electron barrier height between the shielding gate dielectric layer and the drift region;

[0010] An isolation dielectric layer, the isolation dielectric layer is located in the first groove and on a side of the shielding gate dielectric layer away from the substrate; in a thickness direction of the substrate, an upper surface of the blocking dielectric layer is flush with an upper surface of the isolation dielectric layer;

[0011] A control gate structure, the control gate structure is located in the first groove and on a side of the isolation dielectric layer away from the substrate;

[0012] The drain is located at a side of the substrate away from the semiconductor body.

[0013] Optionally, in the thickness direction of the substrate, the thickness of the blocking dielectric layer at the bottom of the first groove ranges from 10 to 100 nm; in the thickness direction perpendicular to the substrate, the thickness of the blocking dielectric layer at the sidewall of the first groove ranges from 10 to 100 nm.

[0014] Optionally, the bandgap width of the blocking dielectric layer is equal to or greater than the bandgap width of the shielding gate dielectric layer.

[0015] Optionally, the conductivity type of the substrate, the drift region and the first active region is N-type, and the conductivity type of the body region is P-type;

[0016] Alternatively, the conductivity types of the substrate, the drift region and the first active region are P type, and the conductivity type of the body region is N type.

[0017] Optionally, when the conductivity types of the substrate, the drift region and the first active region are N-type and the conductivity type of the body region is P-type, the interface hole barrier height between the blocking dielectric layer and the drift region is greater than 4.8 eV.

[0018] Optionally, when the conductivity types of the substrate, the drift region and the first active region are P-type and the conductivity type of the body region is N-type, the interface electron barrier height between the blocking dielectric layer and the drift region is greater than 3.1 eV.

[0019] Optionally, when the conductivity types of the substrate, the drift region and the first active region are N-type, and the conductivity type of the body region is P-type, the blocking dielectric layer includes an aluminum oxide blocking dielectric layer.

[0020] Optionally, the semiconductor body further includes a second active region;

[0021] The second active region is located on a side of the body region away from the substrate, and in a thickness direction perpendicular to the substrate, the first active region is located on both sides of the second active region; the conductivity type of the second active region is the same as that of the body region.

[0022] Optionally, the substrate includes a silicon substrate, a silicon carbide substrate or a gallium nitride substrate; and the semiconductor body includes a silicon semiconductor body, a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0023] In a second aspect, the present invention provides a method for preparing a shielded gate MOSFET device, wherein the preparation method comprises:

[0024] providing a substrate;

[0025] A semiconductor body is formed on one side of the substrate; the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; first grooves are provided on both sides of the semiconductor body in a thickness direction perpendicular to the substrate;

[0026] A blocking dielectric layer is formed at the bottom and sidewall of the first groove, a shielding gate dielectric layer is formed in the first groove and on a side of the blocking dielectric layer away from the substrate, the shielding gate dielectric layer is provided with a second groove, and a shielding gate is formed in the second groove; the interface hole barrier height between the blocking dielectric layer and the drift region is greater than the interface hole barrier height between the shielding gate dielectric layer and the drift region; and / or the interface electron barrier height between the blocking dielectric layer and the drift region is greater than the interface electron barrier height between the shielding gate dielectric layer and the drift region;

[0027] An isolation dielectric layer is formed in the first groove and on a side of the shielding gate dielectric layer away from the substrate; in the thickness direction of the substrate, the upper surface of the blocking dielectric layer is flush with the upper surface of the isolation dielectric layer;

[0028] forming a control gate structure in the first groove and on a side of the isolation dielectric layer away from the substrate;

[0029] A source structure is formed on a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region;

[0030] A drain is formed on a side of the substrate away from the semiconductor body.

[0031] According to the technical solution of the present invention, the bottom and side walls of the shielding gate dielectric layer and the side walls of the isolation dielectric layer are provided with a blocking dielectric layer, and the blocking dielectric layer has good insulation. At the same time, when the shielding gate MOSFET device is an N-channel shielding gate MOSFET device, the interface hole barrier height between the blocking dielectric layer and the drift region is greater than the interface hole barrier height between the shielding gate dielectric layer and the drift region. It is prevented that hot holes are injected into the shielding gate dielectric layer under the action of the electric field between the drift region and the shielding gate. When the shielding gate MOSFET device is a P-channel shielding gate MOSFET device, the interface electron barrier height between the blocking dielectric layer and the drift region is greater than the interface electron barrier height between the shielding gate dielectric layer and the drift region. It is prevented that hot electrons are injected into the shielding gate dielectric layer under the action of the electric field between the drift region and the shielding gate. The technical solution of the present invention can effectively prevent hot carriers from being injected into the shield gate dielectric layer under the action of the electric field between the shield gate and the drift region during reverse breakdown of the shield gate MOSFET device. The hot carriers will not affect the potential of the shield gate dielectric layer and the lateral depletion of the drift region by the shield gate, effectively solving the poor reliability problems of the shield gate MOSFET device such as reduced breakdown voltage or unstable breakdown voltage during reverse breakdown.

[0032] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 It is a structural schematic diagram of a shielded gate MOSFET device provided by the related technology;

[0035] Figure 2 It is a schematic structural diagram of a shielded gate MOSFET device provided by an embodiment of the present invention;

[0036] Figure 3 is an energy band comparison diagram of a drift region and a shielding gate dielectric layer provided by an embodiment of the present invention;

[0037] Figure 4 is a comparison diagram of energy bands of a drift region and a blocking dielectric layer provided by an embodiment of the present invention;

[0038] Figure 5is another energy band comparison diagram of the drift region and the blocking dielectric layer provided by an embodiment of the present invention;

[0039] Figure 6 It is a flow chart of a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention;

[0040] Figure 7-Figure 12 It is a structural diagram corresponding to each step in a method for preparing a shielded gate MOSFET device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Figure 1 It is a structural schematic diagram of a shielded gate MOSFET device provided by the related technology, such as Figure 1 As shown, the shielded gate MOSFET device includes a first conductive type substrate 40, a first conductive type drift region 41, a second conductive type body region 42, a first conductive type active region 43, a second conductive type active region 44, a source electrode 45, a first dielectric layer 46, a second dielectric layer 47, a shielding gate electrode 48, a third dielectric layer 49, a control gate electrode 50, a fourth dielectric layer 51 and a drain electrode 52. Figure 1The shielded gate MOSFET device is exemplarily shown as an N-channel MOSFET device, that is, the first conductivity type is N-type and the second conductivity type is P-type. During reverse breakdown, a high electric field exists in the first conductivity type drift region 41, especially near the side of the first conductivity type drift region 41 close to the first conductivity type substrate 40, which is easy to generate hot carriers. Since the potential of the shielded gate electrode 48 is lower than the potential of the first conductivity type drift region 41, there is an electric field pointing to the shielded gate electrode 48 in the second dielectric layer 47. If the energy of the hot holes is higher than the interface hole barrier height between the first conductivity type drift region 41 and the second dielectric layer 47, the hot holes are injected into the second dielectric layer 47 under the action of the electric field, thereby changing the potential of the second dielectric layer 47, and further affecting the lateral depletion of the first conductivity type drift region 41 by the shielded gate electrode 48, resulting in poor reliability problems such as reduced breakdown voltage or unstable breakdown voltage of the shielded gate MOSFET device.

[0044] In order to solve the above problems, the technical solutions of the embodiments of the present invention are as follows:

[0045] Figure 2 is a schematic diagram of the structure of a shielded gate MOSFET device provided by an embodiment of the present invention, such as Figure 2 As shown, the shielded gate MOSFET device includes: a substrate 1. A semiconductor body 2; the semiconductor body 2 is located on one side of the substrate 1, and the semiconductor body 2 includes a drift region 21, a body region 22, and a first active region 23. The drift region 21 is located on the side of the semiconductor body 2 close to the substrate 1; the body region 22 is located on the side of the drift region 21 away from the substrate 1, and the first active region 23 is located on the side of the body region 22 away from the substrate 1. In the thickness direction perpendicular to the substrate 1, first grooves are provided on both sides of the semiconductor body 2. A source structure 3, the source structure 3 is located on the side of the semiconductor body 2 away from the substrate 1. The source structure 3 is in contact with the first active region 23. A blocking dielectric layer 4, a shielding gate dielectric layer 5, and a shielding gate 6, the blocking dielectric layer 4 is located at the bottom and sidewall of the first groove, the shielding gate dielectric layer 5 is located in the first groove, and is located on the side of the blocking dielectric layer 4 away from the substrate 1, the shielding gate dielectric layer 5 is provided with a second groove, and the shielding gate 6 is located in the second groove. The interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface hole barrier height between the shielding gate dielectric layer 5 and the drift region 21; and / or, the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface electron barrier height between the shielding gate dielectric layer 5 and the drift region 21. Isolation dielectric layer 7, the isolation dielectric layer 7 is located in the first groove and is located on the side of the shielding gate dielectric layer 5 away from the substrate 1. In the thickness direction of the substrate 1, the upper surface of the blocking dielectric layer 4 is flush with the upper surface of the isolation dielectric layer 7. Control gate structure 8, the control gate structure 8 is located in the first groove and is located on the side of the isolation dielectric layer 7 away from the substrate 1. Drain 9, the drain 9 is located on the side of the substrate 1 away from the semiconductor body 2.

[0046] Specifically, the shielded gate MOSFET device includes an N-channel shielded gate MOSFET device and a P-channel shielded gate MOSFET device. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the substrate 1 is an N-substrate, the drift region 21 is an N-drift region, the body region 22 is a P-type body region, and the first active region 23 is an N++ active region. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate, the drift region 21 is a P-drift region, the body region 22 is an N-type body region, and the first active region 23 is a P++ active region.

[0047] The source structure 3 includes a source 31 and a gate-source dielectric layer 32. In a thickness direction perpendicular to the substrate 1, the gate-source dielectric layer 32 is located on both sides of the source 31. The source 31 is in contact with the first active region 23. The control gate structure 8 includes a control gate 81 and a control gate dielectric layer 82. The control gate 81 is located inside the control gate dielectric layer 82.

[0048] The blocking dielectric layer 4 is arranged around the bottom and sidewalls of the shielding gate dielectric layer 5 and the sidewalls of the isolation dielectric layer 7, and the blocking dielectric layer 4 has good insulation. When the shielding gate MOSFET device is an N-channel shielding gate MOSFET device, the interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface hole barrier height between the shielding gate dielectric layer 5 and the drift region 21, so as to prevent hot holes from being injected into the shielding gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielding gate 6 during reverse breakdown. At this time, the direction of the electric field between the drift region 21 and the shielding gate 6 is directed from the drift region 21 to the shielding gate 6. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface electron barrier height between the shielded gate dielectric layer 5 and the drift region 21, thereby preventing hot electrons from being injected into the shielded gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielding gate 6 during reverse breakdown. At this time, the direction of the electric field between the drift region 21 and the shielding gate 6 is from the shielding gate 6 to the drift region 21.

[0049] According to the technical solution of the embodiment of the present invention, a blocking dielectric layer is provided on the bottom and sidewalls of the shielding gate dielectric layer and the sidewalls of the isolation dielectric layer, and the blocking dielectric layer has good insulation. At the same time, when the shielding gate MOSFET device is an N-channel shielding gate MOSFET device, the interface hole barrier height between the blocking dielectric layer and the drift region is greater than the interface hole barrier height between the shielding gate dielectric layer and the drift region. Avoid hot holes from being injected into the shielding gate dielectric layer under the action of the electric field between the drift region and the shielding gate. When the shielding gate MOSFET device is a P-channel shielding gate MOSFET device, the interface electron barrier height between the blocking dielectric layer and the drift region is greater than the interface electron barrier height between the shielding gate dielectric layer and the drift region. Avoid hot electrons from being injected into the shielding gate dielectric layer under the action of the electric field between the drift region and the shielding gate. The technical solution of the embodiment of the present invention can effectively prevent hot carriers from being injected into the shield gate dielectric layer under the action of the electric field between the shield gate and the drift region during reverse breakdown of the shield gate MOSFET device. The hot carriers will not affect the potential of the shield gate dielectric layer and the lateral depletion of the drift region by the shield gate, effectively solving the poor reliability problem of the shield gate MOSFET device such as reduced breakdown voltage or unstable breakdown voltage during reverse breakdown.

[0050] Optionally, based on the above embodiments, continue to refer to Figure 2 For N-channel shielded gate MOSFET devices and P-channel shielded gate MOSFET devices, the thickness of the blocking dielectric layer 5 at the bottom of the first groove in the thickness direction of the substrate 1 is in the range of 10-100 nm. In the thickness direction perpendicular to the substrate 1, the thickness of the blocking dielectric layer 5 at the sidewall of the first groove is in the range of 10-100 nm.

[0051] Specifically, the thickness of the blocking dielectric layer 4 below the shielding gate dielectric layer 5 is in the range of 10-100 nm, and the thickness of the blocking dielectric layer 4 on both sides of the shielding gate dielectric layer 5 and on both sides of the isolation dielectric layer 7 is in the range of 10-100 nm. That is, the overall thickness of the blocking dielectric layer 4 is in the range of 10-100 nm. If the thickness of the blocking dielectric layer 4 is set too thin, for an N-channel shielded gate MOSFET device, hot holes will tunnel through the blocking dielectric layer 4 and enter the shielding gate dielectric layer 5. For a P-channel shielded gate MOSFET device, hot electrons will tunnel through the blocking dielectric layer 4 and enter the shielding gate dielectric layer 5. If the thickness of the blocking dielectric layer 4 is set too thick, the control of the electric field of the drift region 21 by the shielding gate 6 will be weakened, thereby affecting the performance and reliability of the shielded gate MOSFET device.

[0052] Optionally, based on the above embodiments, continue to refer to Figure 2For N-channel shielded gate MOSFET devices and P-channel shielded gate MOSFET devices, the bandgap width of the blocking dielectric layer 4 is equal to or greater than the bandgap width of the shielding gate dielectric layer 5 .

[0053] Specifically, the bandgap width of the blocking dielectric layer 4 needs to be equal to or greater than the bandgap width of the shielding gate dielectric layer 5, ensuring that the insulation performance of the blocking dielectric layer 4 is equal to or greater than the insulation performance of the shielding gate dielectric layer 5, and achieving a good insulation effect. Exemplarily, the shielding gate dielectric layer 5 can be a silicon dioxide shielding gate dielectric layer, and the bandgap width of the silicon dioxide shielding gate dielectric layer is 9eV. At this time, the bandgap width of the blocking dielectric layer 4 needs to be equal to or greater than 9eV.

[0054] Optionally, based on the above embodiments, continue to refer to Figure 2 For an N-channel shielded gate MOSFET device, the conductivity type of the substrate 1, the drift region 21 and the first active region 23 is N-type, and the conductivity type of the body region 22 is P-type. Alternatively, for a P-channel shielded gate MOSFET device, the conductivity type of the substrate 1, the drift region 21 and the first active region 23 is P-type, and the conductivity type of the body region 22 is N-type.

[0055] Specifically, for an N-channel shielded gate MOSFET device, the substrate 1 is an N-substrate, the drift region 21 is an N-drift region, the body region 22 is a P-type body region, and the first active region 23 is an N++ active region. For a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate, the drift region 21 is a P-drift region, the body region 22 is an N-type body region, and the first active region 23 is a P++ active region.

[0056] When the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface hole barrier height between the shielded gate dielectric layer 5 and the drift region 21, so as to prevent hot holes from being injected into the shielded gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielded gate 6, and at this time, the direction of the electric field between the drift region 21 and the shielded gate 6 is directed from the drift region 21 to the shielded gate 6. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface electron barrier height between the shielded gate dielectric layer 5 and the drift region 21, so as to prevent hot electrons from being injected into the shielded gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielded gate 6, and at this time, the direction of the electric field between the drift region 21 and the shielded gate 6 is directed from the shielded gate 6 to the drift region 21.

[0057] Optionally, based on the above embodiments, continue to refer to Figure 2For an N-channel shielded gate MOSFET device, that is, when the conductivity types of the substrate 1, the drift region 21 and the first active region 23 are N-type and the conductivity type of the body region 22 is P-type, the interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than 4.8 eV.

[0058] Specifically, Figure 3 is a comparison diagram of energy bands of a drift region and a shielding gate dielectric layer provided by an embodiment of the present invention, Figure 4 This is an energy band comparison diagram of a drift region and a blocking dielectric layer provided by an embodiment of the present invention. Figure 3 The drift region 21 is exemplarily shown as a silicon drift region, and the shielding gate dielectric layer 5 is a silicon dioxide shielding gate dielectric layer. Figure 4 The drift region 21 is exemplarily shown to be a silicon drift region. In any other embodiment of the present invention, the drift region 21 may also include a silicon carbide drift region or a gallium nitride drift region, etc., and the shielding gate dielectric layer 5 may also include a silicon nitride shielding gate dielectric layer or a high-K material shielding gate dielectric layer, which is not specifically limited here.

[0059] like Figure 2-Figure 4 As shown, for an N-channel shielded gate MOSFET device, when the drift region 21 is a silicon drift region, the shielding gate dielectric layer 5 is a silicon dioxide shielding gate dielectric layer, the bandgap width of the drift region 21 is 1.1 eV, the bandgap width of the shielding gate dielectric layer 5 is 9 eV, the interface hole barrier height ΔEv1 between the shielding gate dielectric layer 5 and the drift region 21 is 4.8 eV, and the interface electron barrier height ΔEc1 between the shielding gate dielectric layer 5 and the drift region 21 is 3.1 eV.

[0060] The bandgap width of the blocking dielectric layer 4 needs to be equal to or greater than the bandgap width of the shielding gate dielectric layer 5, ensuring that the insulation performance of the blocking dielectric layer 4 is equal to or greater than the insulation performance of the shielding gate dielectric layer 5, and achieving a good insulation effect. That is, at this time, the bandgap width of the blocking dielectric layer 4 needs to be equal to or greater than 9eV. For N-channel shielded gate MOSFET devices, the interface hole barrier height ΔEv2 between the blocking dielectric layer 4 and the drift region 21 needs to be greater than the interface hole barrier height ΔEv1 between the shielding gate dielectric layer 5 and the drift region 21, to prevent hot holes from being injected into the shielding gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielding gate 6. At this time, the direction of the electric field between the drift region 21 and the shielding gate 6 is from the drift region 21 to the shielding gate 6. Therefore, it is necessary to ensure that the interface hole barrier height ΔEv2 between the blocking dielectric layer 4 and the drift region 21 is greater than 4.8eV.

[0061] Exemplarily, the drift region 21 may also include a silicon carbide drift region, in which case the interface hole barrier height between the blocking dielectric layer 4 and the silicon carbide drift region needs to be greater than the interface hole barrier height between the shielding gate dielectric layer 5 and the silicon carbide drift region. The drift region 21 may also include a gallium nitride drift region, in which case the interface hole barrier height between the blocking dielectric layer 4 and the gallium nitride drift region needs to be greater than the interface hole barrier height between the shielding gate dielectric layer 5 and the gallium nitride drift region.

[0062] The shielding gate dielectric layer 5 may also include a silicon nitride shielding gate dielectric layer, in which case the interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 needs to be greater than the interface hole barrier height between the silicon nitride shielding gate dielectric layer and the drift region 21. The shielding gate dielectric layer 5 may also include a high-K material shielding gate dielectric layer, in which case the interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 needs to be greater than the interface hole barrier height between the high-K material shielding gate dielectric layer and the drift region 21.

[0063] Optionally, based on the above embodiments, continue to refer to Figure 2 For a P-channel shielded gate MOSFET device, that is, when the conductivity types of the substrate 1, the drift region 21 and the first active region 23 are P-type and the conductivity type of the body region 22 is N-type, the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than 3.1 eV.

[0064] Specifically, Figure 5 is another energy band comparison diagram of the drift region and the blocking dielectric layer provided by an embodiment of the present invention, Figure 5 The drift region 21 is exemplarily shown to be a silicon drift region. In any other embodiment of the present invention, the drift region 21 may also include a silicon carbide drift region or a gallium nitride drift region, etc., and the shielding gate dielectric layer 5 may also include a silicon nitride shielding gate dielectric layer or a high-K material shielding gate dielectric layer, which is not specifically limited here.

[0065] like Figure 2 , Figure 3 and Figure 5 As shown, for a P-channel shielded gate MOSFET device, when the drift region 21 is a silicon drift region, the shielding gate dielectric layer 5 is a silicon dioxide shielding gate dielectric layer, the bandgap width of the drift region 21 is 1.1 eV, the bandgap width of the shielding gate dielectric layer 5 is 9 eV, the interface hole barrier height ΔEv1 between the shielding gate dielectric layer 5 and the drift region 21 is 4.8 eV, and the interface electron barrier height ΔEc1 between the shielding gate dielectric layer 5 and the drift region 21 is 3.1 eV.

[0066] The bandgap width of the blocking dielectric layer 4 needs to be equal to or greater than the bandgap width of the shielding gate dielectric layer 5, ensuring that the insulation performance of the blocking dielectric layer 4 is equal to or greater than the insulation performance of the shielding gate dielectric layer 5, and achieving a good insulation effect. That is, at this time, the bandgap width of the blocking dielectric layer 4 needs to be equal to or greater than 9eV. For P-channel shielded gate MOSFET devices, the interface electron barrier height ΔEc2 between the blocking dielectric layer 4 and the drift region 21 needs to be greater than the interface electron barrier height ΔEc1 between the shielding gate dielectric layer 5 and the drift region 21, to prevent hot electrons from being injected into the shielding gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielding gate 6. At this time, the direction of the electric field between the drift region 21 and the shielding gate 6 is from the shielding gate 6 to the drift region 21. Therefore, it is necessary to ensure that the interface electron barrier height ΔEc2 between the blocking dielectric layer 4 and the drift region 21 is greater than 3.1eV.

[0067] Exemplarily, the drift region 21 may also include a silicon carbide drift region, in which case the interface electron barrier height between the blocking dielectric layer 4 and the silicon carbide drift region needs to be greater than the interface electron barrier height between the shielding gate dielectric layer 5 and the silicon carbide drift region. The drift region 21 may also include a gallium nitride drift region, in which case the interface electron barrier height between the blocking dielectric layer 4 and the gallium nitride drift region needs to be greater than the interface electron barrier height between the shielding gate dielectric layer 5 and the gallium nitride drift region.

[0068] The shielding gate dielectric layer 5 may also include a silicon nitride shielding gate dielectric layer, in which case the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 needs to be greater than the interface electron barrier height between the silicon nitride shielding gate dielectric layer and the drift region 21. The shielding gate dielectric layer 5 may also include a high-K material shielding gate dielectric layer, in which case the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 needs to be greater than the interface electron barrier height between the high-K material shielding gate dielectric layer and the drift region 21.

[0069] Optionally, based on the above embodiments, continue to refer to Figure 2-Figure 4 For an N-channel shielded gate MOSFET device, that is, when the conductivity types of the substrate 1, the drift region 21 and the first active region 23 are N-type and the conductivity type of the body region 22 is P-type, the blocking dielectric layer 4 includes an aluminum oxide blocking dielectric layer.

[0070] Specifically, for an N-channel shielded gate MOSFET device, when the drift region 21 is a silicon drift region, the shielded gate dielectric layer 5 is a silicon dioxide shielded gate dielectric layer, the bandgap width of the drift region 21 is 1.1 eV, the bandgap width of the shielded gate dielectric layer 5 is 9 eV, the interface hole barrier height ΔEv1 between the shielded gate dielectric layer 5 and the drift region 21 is 4.8 eV, and the interface electron barrier height ΔEc1 between the shielded gate dielectric layer 5 and the drift region 21 is 3.1 eV. The bandgap width of the aluminum oxide blocking dielectric layer is equivalent to the bandgap width of the shielded gate dielectric layer 5, and the aluminum oxide blocking dielectric layer can play a good insulating effect. And the interface hole barrier height between the aluminum oxide blocking dielectric layer and the drift region 21 is 4.9 eV, which is greater than the interface hole barrier height ΔEv1 between the shielded gate dielectric layer 5 and the drift region 21, so the aluminum oxide blocking dielectric layer can effectively prevent hot holes from being injected into the shielded gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielding gate 6.

[0071] Optionally, based on the above embodiments, continue to refer to Figure 2 The semiconductor body 2 further includes a second active region 24. The second active region 24 is located on a side of the body region 22 away from the substrate 1, and in a thickness direction perpendicular to the substrate 1, the first active region 23 is located on both sides of the second active region 24; the conductivity type of the second active region 24 is the same as that of the body region 22.

[0072] Specifically, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the second active region 24 is a P++ active region. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the second active region 24 is an N++ active region. The doping concentration of the second active region 24 is greater than the doping concentration of the body region 22, and can form a good ohmic contact with the source 31.

[0073] Optionally, based on the above embodiments, continue to refer to Figure 2 For N-channel shielded gate MOSFET devices and P-channel shielded gate MOSFET devices, substrate 1 includes a silicon substrate, a silicon carbide substrate or a gallium nitride substrate; the semiconductor body includes a silicon semiconductor body, a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0074] Specifically, the substrate 1 may be a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate. The semiconductor body 2 may be a silicon semiconductor body, a silicon carbide semiconductor body, or a gallium nitride semiconductor body. When the materials of the substrate 1 and the semiconductor body 2 are silicon carbide or gallium nitride, the shielded gate MOSFET device has the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of the power device.

[0075] Figure 6is a flow chart of a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, Figure 7-Figure 12 is a structural diagram corresponding to each step in a method for preparing a shielded gate MOSFET device provided by an embodiment of the present invention, such as Figure 6 As shown, the preparation method comprises:

[0076] S100: providing a substrate.

[0077] Specifically, Figure 7 As shown, a substrate 1 is first provided, and the semiconductor material of the substrate 1 can be silicon, silicon carbide or gallium nitride. The shielded gate MOSFET device includes an N-channel shielded gate MOSFET device and a P-channel shielded gate MOSFET device. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the substrate 1 is an N-substrate, and when the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate.

[0078] S110: A semiconductor body is formed on one side of a substrate; the semiconductor body includes a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; first grooves are provided on both sides of the semiconductor body in a thickness direction perpendicular to the substrate.

[0079] Specifically, Figure 8 As shown, a semiconductor body 2 is formed on one side of a substrate 1, and the semiconductor body 2 includes a drift region 21 located on a side of the semiconductor body 2 close to the substrate 1, a body region 22 located on a side of the drift region 21 away from the substrate 1, and a first active region 23 located on a side of the body region 22 away from the substrate 1. The semiconductor body 2 may further include a second active region 24 located in the middle of the first active region 23. First grooves 25 are provided on both sides of the semiconductor body 2.

[0080] The material of the semiconductor body 2 includes silicon, silicon carbide or gallium nitride. Exemplarily, when the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the drift region 21 is an N-drift region, the body region 22 is a P-type body region, the first active region 23 is an N++ active region, and the second active region 24 is a P++ active region. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the substrate 1 is a P-substrate, the drift region 21 is a P-drift region, the body region 22 is an N-type body region, the first active region 23 is a P++ active region, and the second active region 24 is an N++ active region.

[0081] Exemplarily, the semiconductor body 2 can be formed on one side of the substrate 1 by an epitaxial process such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) or atomic layer epitaxy (ALE), and then the body region 22, the first active region 23 and the second active region 24 are formed by processes such as ion implantation and annealing. After completing the above steps, the drift region 21 is formed, and the semiconductor material and doping type of the drift region 21 and the semiconductor body 2 are the same.

[0082] S120: A blocking dielectric layer is formed at the bottom and sidewall of the first groove, a shielding gate dielectric layer is formed in the first groove and on the side of the blocking dielectric layer away from the substrate, the shielding gate dielectric layer is provided with a second groove, and a shielding gate is formed in the second groove; the interface hole barrier height between the blocking dielectric layer and the drift region is greater than the interface hole barrier height between the shielding gate dielectric layer and the drift region; and / or, the interface electron barrier height between the blocking dielectric layer and the drift region is greater than the interface electron barrier height between the shielding gate dielectric layer and the drift region.

[0083] Specifically, Fig. 9 As shown, a blocking dielectric layer 4 is formed at the bottom and sidewall of the first groove 25, a shielding gate dielectric layer 5 is deposited in the first groove 25 and on the side of the blocking dielectric layer 4 away from the substrate 1, the shielding gate dielectric layer 5 is provided with a second groove, and a shielding gate 6 is deposited in the second groove. Exemplarily, silicon dioxide can be deposited in the first groove 25 and on the side of the blocking dielectric layer 4 away from the substrate 1 to form the shielding gate dielectric layer 5, and doped polysilicon can be deposited in the second groove to form the shielding gate 6.

[0084] When the shielded gate MOSFET device is an N-channel shielded gate MOSFET device, the interface hole barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface hole barrier height between the shielded gate dielectric layer 5 and the drift region 21, so as to avoid hot holes being injected into the shielded gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielded gate 6 during reverse breakdown, and at this time, the direction of the electric field between the drift region 21 and the shielded gate 6 is directed from the drift region 21 to the shielded gate 6. When the shielded gate MOSFET device is a P-channel shielded gate MOSFET device, the interface electron barrier height between the blocking dielectric layer 4 and the drift region 21 is greater than the interface electron barrier height between the shielded gate dielectric layer 5 and the drift region 21, so as to avoid hot electrons being injected into the shielded gate dielectric layer 5 under the action of the electric field between the drift region 21 and the shielded gate 6 during reverse breakdown, and at this time, the direction of the electric field between the drift region 21 and the shielded gate 6 is directed from the shielded gate 6 to the drift region 21.

[0085] S130: forming an isolation dielectric layer in the first groove and on a side of the shielding gate dielectric layer away from the substrate; in a thickness direction of the substrate, an upper surface of the blocking dielectric layer is flush with an upper surface of the isolation dielectric layer.

[0086] Specifically, Fig.10 As shown, an isolation dielectric layer 7 is formed in the first groove 25 and on the side of the shielding gate dielectric layer 5 away from the substrate 1. Exemplarily, silicon dioxide is deposited in the first groove 25 and on the side of the shielding gate dielectric layer 5 away from the substrate 1 to form the isolation dielectric layer 7.

[0087] S140: forming a control gate structure in the first groove and on a side of the isolation dielectric layer away from the substrate.

[0088] Specifically, Fig.11 As shown, a control gate dielectric layer 82 is formed on the side of the isolation dielectric layer 7 away from the substrate 1, and then a control gate 81 is formed in the control gate dielectric layer 82 by processes such as photolithography and etching. Exemplarily, silicon dioxide is deposited on the side of the isolation dielectric layer 7 away from the substrate 1 to form the control gate dielectric layer 82, and then doped polysilicon is deposited in the control gate dielectric layer 82 by processes such as photolithography and etching to form the control gate 81.

[0089] S150: forming a source structure on a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region.

[0090] Specifically, Fig.12 As shown, a gate-source dielectric layer 32 is first formed on the side of the semiconductor body 2 away from the substrate 1, and then a source electrode 31 is formed by processes such as photolithography and etching. Exemplarily, silicon dioxide is deposited on the side of the semiconductor body 2 away from the substrate 1 to first form the gate-source dielectric layer 32. The source electrode 31 may be a metal electrode.

[0091] S160: forming a drain on a side of the substrate away from the semiconductor body.

[0092] Specifically, Figure 2 As shown, a drain electrode 9 is formed on a side of the substrate 1 away from the semiconductor body 2. The drain electrode 9 may be a metal electrode.

[0093] The method for preparing the shielded gate MOSFET device provided in any of the above embodiments of the present invention is applicable to preparing any of the shielded gate MOSFET devices provided in any of the above embodiments of the present invention, and has the beneficial effects of any of the shielded gate MOSFET devices provided in any of the above embodiments of the present invention.

[0094] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shielded gate MOSFET device, characterized in that: include: substrate; A semiconductor body; the semiconductor body is located on one side of the substrate, the semiconductor body comprises a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; first grooves are provided on both sides of the semiconductor body in a thickness direction perpendicular to the substrate; A source structure, the source structure is located at a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region; A blocking dielectric layer, a shielding gate dielectric layer and a shielding gate, wherein the blocking dielectric layer is located at the bottom and sidewalls of the first groove, the shielding gate dielectric layer is located in the first groove and on a side of the blocking dielectric layer away from the substrate, the shielding gate dielectric layer is provided with a second groove, and the shielding gate is located in the second groove; an interface hole barrier height between the blocking dielectric layer and the drift region is greater than an interface hole barrier height between the shielding gate dielectric layer and the drift region; and / or, a height of an interface electron barrier between the blocking dielectric layer and the drift region is greater than a height of an interface electron barrier between the shielding gate dielectric layer and the drift region; an isolation dielectric layer, the isolation dielectric layer being located in the first groove and on a side of the shielding gate dielectric layer away from the substrate; in a thickness direction of the substrate, an upper surface of the blocking dielectric layer is flush with an upper surface of the isolation dielectric layer; a control gate structure, wherein the control gate structure is located in the first groove and on a side of the isolation dielectric layer away from the substrate; A drain is located at a side of the substrate away from the semiconductor body.

2. The shielded gate MOSFET device according to claim 1, characterized in that: In the thickness direction of the substrate, the thickness of the blocking dielectric layer at the bottom of the first groove ranges from 10 to 100 nm; in the thickness direction perpendicular to the substrate, the thickness of the blocking dielectric layer at the sidewall of the first groove ranges from 10 to 100 nm.

3. The shielded gate MOSFET device according to claim 1, characterized in that: The bandgap width of the blocking dielectric layer is equal to or greater than the bandgap width of the shielding gate dielectric layer.

4. The shielded gate MOSFET device according to claim 1, characterized in that: The conductivity type of the substrate, the drift region and the first active region is N-type, and the conductivity type of the body region is P-type; Alternatively, the conductivity type of the substrate, the drift region and the first active region is P type, and the conductivity type of the body region is N type.

5. The shielded gate MOSFET device according to claim 4, characterized in that: When the conductivity types of the substrate, the drift region and the first active region are N-type and the conductivity type of the body region is P-type, the interface hole barrier height between the blocking dielectric layer and the drift region is greater than 4.8 eV.

6. The shielded gate MOSFET device according to claim 4, characterized in that: When the conductivity types of the substrate, the drift region and the first active region are P-type and the conductivity type of the body region is N-type, the interface electron barrier height between the blocking dielectric layer and the drift region is greater than 3.1 eV.

7. The shielded gate MOSFET device according to claim 5, characterized in that: When the conductivity types of the substrate, the drift region and the first active region are N-type, and the conductivity type of the body region is P-type, the blocking dielectric layer includes an aluminum oxide blocking dielectric layer.

8. The shielded gate MOSFET device according to claim 1, characterized in that: The semiconductor body further comprises a second active region; The second active region is located on a side of the body region away from the substrate, and in a thickness direction perpendicular to the substrate, the first active region is located on both sides of the second active region; the conductivity type of the second active region is the same as that of the body region.

9. The shielded gate MOSFET device according to claim 1, characterized in that: The substrate includes a silicon substrate, a silicon carbide substrate or a gallium nitride substrate; the semiconductor body includes a silicon semiconductor body, a silicon carbide semiconductor body or a gallium nitride semiconductor body.

10. A method for preparing a shielded gate MOSFET device, characterized in that: include: providing a substrate; A semiconductor body is formed on one side of the substrate; the semiconductor body comprises a drift region, a body region and a first active region; the drift region is located on a side of the semiconductor body close to the substrate; the body region is located on a side of the drift region away from the substrate, and the first active region is located on a side of the body region away from the substrate; first grooves are provided on both sides of the semiconductor body in a thickness direction perpendicular to the substrate; A blocking dielectric layer is formed at the bottom and sidewall of the first groove, a shielding gate dielectric layer is formed in the first groove and on the side of the blocking dielectric layer away from the substrate, the shielding gate dielectric layer is provided with a second groove, and a shielding gate is formed in the second groove; the interface hole barrier height between the blocking dielectric layer and the drift region is greater than the interface hole barrier height between the shielding gate dielectric layer and the drift region; and / or the interface electron barrier height between the blocking dielectric layer and the drift region is greater than the interface electron barrier height between the shielding gate dielectric layer and the drift region; An isolation dielectric layer is formed in the first groove and on a side of the shielding gate dielectric layer away from the substrate; in the thickness direction of the substrate, the upper surface of the blocking dielectric layer is flush with the upper surface of the isolation dielectric layer; forming a control gate structure in the first groove and on a side of the isolation dielectric layer away from the substrate; A source structure is formed on a side of the semiconductor body away from the substrate; the source structure is in contact with the first active region; A drain is formed on a side of the substrate away from the semiconductor body.

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