Texturing method of silicon wafer, textured silicon wafer, crystalline silicon cell and preparation method of crystalline silicon cell

Abstract

The invention relates to a texturing method of a silicon wafer and a textured silicon wafer, and the texturing method comprises the steps: forming a pyramid textured surface on the silicon wafer, then carrying out the rounding treatment to form a rounded textured surface, and then forming pits in the rounded textured surface, thereby completing the texturing. Wherein the rounding treatment comprises the following steps: sequentially carrying out first treatment and second treatment in a first mixed solution and a second mixed solution, the first treatment and the second treatment form a cycle, at least two cycles are carried out, the first mixed solution comprises HNO3 and HF, the mass fraction of HNO3 is greater than that of HF, the second mixed solution comprises HNO3 and HF, the mass fraction of HNO3 is greater than that of HF, the mass fraction of HNO3 is greater than that of HF, and the mass fraction of HF is greater than that of HF. The mass fraction of HNO3 is smaller than that of HF, the time of the first treatment is longer than that of the second treatment, the number of the obtained pits is 10-100 / cm < 2 >, the width is 0.01-0.08 mu m, and the depth is 5-50 nm. The invention further provides a crystalline silicon cell and a preparation method thereof, and in the preparation method of the crystalline silicon cell, the conversion efficiency of the crystalline silicon cell can be effectively improved by adopting the texturing method.

Description

Technical Field

[0001] The invention relates to the technical field of solar cells, and in particular to a method for texturing a silicon wafer, the silicon wafer after texturing, a crystalline silicon cell and a preparation method thereof. Background Art

[0002] Texturing is to form a pyramid structure on the surface of silicon wafers, so as to achieve the purpose of reducing the reflectivity of silicon wafers. At present, the velvet surface grown by conventional texturing often has a sharp pyramid tip. Under the current velvet state, the passivation film deposition effect in the areas of the pyramid tip and the bottom of the pyramid will be different from that in other parts, and the deposition effect is poor, so the recombination rate and defect state density in this area will be large, affecting the quality of solar cells. Therefore, it is necessary to optimize the velvet surface, improve the quality of the passivation film deposition, and thus improve the passivation effect.

[0003] The existing velvet optimization technology mainly treats the pyramid velvet surface with a strong oxidizing acidic solution to achieve a rounding effect. The greater the degree of rounding, the better the deposition effect of the passivation film, and the better the passivation effect, and the open circuit voltage of the prepared battery will increase. However, the velvet rounding will correspondingly increase the reflectivity of the silicon wafer, thereby reducing the short-circuit current of the battery. Therefore, how to maintain a low reflectivity of the silicon wafer while improving the passivation effect has become a key factor limiting the high performance of solar cells. Summary of the invention

[0004] Based on this, it is necessary to provide a texturing method for silicon wafers and the silicon wafers after texturing, crystalline silicon cells and their preparation methods to address the above problems. The texturing method can effectively improve the conversion efficiency of crystalline silicon cells.

[0005] A method for texturing a silicon wafer comprises the following steps:

[0006] Forming a pyramid velvet surface on a silicon wafer;

[0007] The pyramid velvet surface is subjected to rounding treatment to form a rounded velvet surface, comprising: placing a silicon wafer with the pyramid velvet surface in a first mixed solution for a first treatment, and then placing the silicon wafer in a second mixed solution for a second treatment, wherein the first treatment and the second treatment constitute a cycle, and the cycle is performed at least twice, wherein the first mixed solution and the second mixed solution both comprise HNO3 and HF, the mass fraction of HNO3 in the first mixed solution is greater than the mass fraction of HF, the mass fraction of HNO3 in the second mixed solution is less than the mass fraction of HF, and the time of the first treatment is greater than the time of the second treatment;

[0008] Form pits on the rounded pile surface to complete the pile making, wherein the number of the pits is 10 / cm 2 ~100 pieces / cm2 The width of the pit is 0.01 μm to 0.08 μm, and the depth is 5 nm to 50 nm.

[0009] In one embodiment, the number of cycles is 5 to 20 times.

[0010] In one embodiment, the first treatment step lasts for 15s to 20s;

[0011] And / or, in the step of the second treatment, the time is 5s to 10s.

[0012] In one embodiment, the concentration of HNO3 in the first mixed solution is 40wt% to 80wt%, and the concentration of HF is 10wt% to 20wt%;

[0013] And / or, the concentration of HNO3 in the second mixed solution is 10wt% to 20wt%, and the concentration of HF is 40wt% to 80wt%.

[0014] In one of the embodiments, pits are formed on the rounded suede surface by metal etching.

[0015] In one embodiment, the rounded velvet surface is treated for the third time and the fourth time with a third mixed solution and a fourth mixed solution, respectively, wherein the third mixed solution comprises copper ions and HF, and the concentration of the copper ions is 1wt% to 5wt%, the concentration of the HF is 40wt% to 60wt%, the time of the third treatment is 100s to 200s, the fourth mixed solution comprises HCl and H2O2, and the concentration of the HCl is 2wt% to 10wt%, the concentration of the H2O2 is 5wt% to 20wt%, and the time of the fourth treatment is 50s to 200s.

[0016] In one embodiment, the size of the base of a single pyramid velvet surface is 1 μm-2.5 μm.

[0017] A texturized silicon wafer obtained by adopting the texturizing method for a silicon wafer.

[0018] A method for preparing a crystalline silicon cell comprises adopting the aforementioned method for texturing a silicon wafer.

[0019] A crystalline silicon cell obtained by adopting the crystalline silicon cell preparation method.

[0020] In the silicon wafer texturing method provided by the present invention, the pyramid velvet surface is cyclically treated with a first mixed solution and a second mixed solution in a specific ratio, and the time distribution relationship when the two mixed solutions are used for treatment in each cycle is controlled, so that the purpose of uniformly rounding the entire area of ​​the pyramid velvet surface and quickly rounding the entire area of ​​the pyramid velvet surface can be achieved. Furthermore, a number of 10 / cm 2 ~100 pieces / cm 2 The pits with a width of 0.01 μm to 0.08 μm and a depth of 5 nm to 50 nm will not affect the deposition effect of the passivation film, but can also increase the specific surface area of ​​the velvet surface, so that the reflectivity is kept below 5%. Therefore, in the preparation method of crystalline silicon cells, the velvet method of the present invention can effectively improve the conversion efficiency of crystalline silicon cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the pyramid velvet surface after velveting;

[0022] Figure 2 It is a schematic diagram of rounded velvet surface;

[0023] Figure 3 A schematic diagram of the principle of forming pits by metal etching on a rounded velvet surface;

[0024] Figure 4 Schematic diagram of a rounded suede surface with pits. DETAILED DESCRIPTION

[0025] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.

[0027] The present invention provides a method for texturing a silicon wafer, comprising the following steps:

[0028] S1, forming a pyramid velvet surface on a silicon wafer;

[0029] S2, rounding the pyramid velvet surface to form a rounded velvet surface, comprising: placing a silicon wafer with the pyramid velvet surface in a first mixed solution for a first treatment, and then placing it in a second mixed solution for a second treatment, wherein the first treatment and the second treatment constitute a cycle, and the cycle is performed at least twice, wherein the first mixed solution and the second mixed solution both comprise HNO3 and HF, the mass fraction of HNO3 in the first mixed solution is greater than the mass fraction of HF, the mass fraction of HNO3 in the second mixed solution is less than the mass fraction of HF, and the time of the first treatment is greater than the time of the second treatment;

[0030] S3, forming pits on the rounded pile surface to complete the pile making, wherein the number of the pits is 10 / cm 2 ~100 pieces / cm 2 The width of the pit is 0.01 μm to 0.08 μm, and the depth is 5 nm to 50 nm.

[0031] In step S1, the steps of forming the pyramid velvet surface on the silicon wafer are not limited. Preferably, the steps include: first performing a pre-cleaning treatment, and then performing a velvet treatment to obtain the pyramid velvet surface.

[0032] Optionally, in the pre-cleaning step, a pre-cleaning solution is prepared using NaOH and H2O2 to remove oil stains and cutting marks on the surface of the silicon wafer. In the pre-cleaning solution, the concentration of NaOH is preferably 0.05wt% to 0.2wt%, the concentration of H2O2 is preferably 1wt% to 5wt%, the pre-cleaning time is preferably 50s to 150s, and the temperature is preferably 60°C to 65°C; after the pre-cleaning step, deionized water can also be used for cleaning, and the time is preferably 50s to 100s.

[0033] In the texturing step, an alkaline texturing solution is prepared using NaOH and a texturing additive, and the silicon wafer is etched in the alkaline texturing solution to form a pyramid texturing surface, wherein in the formed pyramid texturing surface, the size of the bottom edge of a single pyramid texturing surface is 1μm-2.5μm, specifically, the size of the diagonal line of the bottom edge of a single pyramid texturing surface. Such a setting is conducive to forming the pits described in the present invention on the rounded texturing surface after rounding treatment.

[0034] Optionally, in the alkaline texturing solution, the concentration of NaOH is preferably 0.5wt% to 5wt%, the concentration of the texturing additive is preferably 0.3wt% to 1wt%, the texturing time is preferably 200s to 300s, and the temperature is preferably 65℃ to 75℃, so as to form a pyramid velvet surface of the above size; after texturing, it is preferably washed with deionized water, and the time is preferably 50s to 100s. The schematic diagram of the pyramid velvet surface after texturing is as follows Figure 1 shown.

[0035] In the rounding process, HNO3 can oxidize the sharp areas of the velvet surface to form silicon oxide, and HF can remove the oxidized silicon oxide, that is, the two have different functions, one is oxidation, and the other is removal of silicon oxide, so as to achieve the purpose of flattening the sharp areas. If the silicon oxide formed by HNO3 oxidation cannot be effectively removed immediately, then the silicon oxide will block the subsequent HNO3 and the inner silicon reaction, greatly affecting the degree of rounding. Therefore, how to balance the formation and removal of silicon oxide is the key to improving the rounding effect.

[0036] To this end, in step S2 of the present invention, a first treatment is performed using a first mixed solution composed of a high concentration of HNO3 and a low concentration of HF, and then a second treatment is performed using a second mixed solution of a low concentration of HNO3 and a high concentration of HF, and this is used as a cycle, and multiple cycles are performed to round the velvet surface, and the time distribution relationship between the first treatment and the second treatment in each cycle is controlled, so that the formation and removal of silicon oxide can be balanced, thereby achieving the purpose of uniformly rounding and quickly rounding the entire area of ​​the pyramid velvet surface. The schematic diagram of the rounded velvet surface is shown in Figure 2 shown.

[0037] Optionally, the concentration of HNO3 in the first mixed solution is preferably 40wt% to 80wt%, the concentration of HF is preferably 10wt% to 20wt%, and / or, the concentration of HNO3 in the second mixed solution is preferably 10wt% to 20wt%, and the concentration of HF is preferably 40wt% to 80wt%; the time for the first treatment is preferably 15s to 20s, and / or, the time for the second treatment is preferably 5s to 10s, and the number of cycles is preferably 5 to 20 times, so that the effect of uniform rounding and rapid rounding of the entire area can be further achieved during the rounding process.

[0038] Optionally, during each cycle, the first treatment time may be the same or different, and the second treatment time may be the same or different. For example, during each cycle, the first treatment time and the second treatment time are kept the same; or, during each cycle, the first treatment time and the second treatment time are gradually reduced as the number of cycles increases, thereby avoiding excessive rounding and increasing reflectivity; or, during each cycle, the first treatment time and the second treatment time are gradually increased as the number of cycles increases.

[0039] Then, in step S3, 10 pieces / cm 2 ~100 pieces / cm 2The pits with a width of 0.01μm to 0.08μm and a depth of 5nm to 50nm will not affect the deposition effect of the passivation film, but can also increase the specific surface area of ​​the suede and keep the reflectivity below 5%.

[0040] Preferably, the number of pits is 40 / cm 2 ~80 pieces / cm 2 , which is conducive to obtaining a suede surface with better reflectivity and passivation effect, effectively improving the conversion efficiency of crystalline silicon cells.

[0041] In step S3, the method of forming the pits on the rounded suede surface is not specifically limited. Preferably, the pits are formed on the rounded suede surface by metal etching. The steps include:

[0042] The rounded velvet surface is treated for the third time and the fourth time with a third mixed solution and a fourth mixed solution, respectively, wherein the third mixed solution includes copper ions and HF, and the concentration of the copper ions is 1wt% to 5wt%, the concentration of the HF is 40wt% to 60wt%, the time of the third treatment is 100s to 200s, the fourth mixed solution includes HCl and H2O2, and the concentration of the HCl is 2wt% to 10wt%, the concentration of the H2O2 is 5wt% to 20wt%, and the time of the fourth treatment is 50s to 200s. In the third mixed solution, the copper ions are derived from at least one of copper chloride or copper nitrate.

[0043] Its main principles are as follows Figure 3 As shown, in the third treatment process, the Cu 2+ It reacts with Si to form copper particles to form copper cores, and the electrode potential of Cu is greater than that of silicon. 2 + It will continuously react with Si on the rounded velvet surface to generate copper particles, and silicon will undergo oxidation reaction to generate silicon oxide, so that the copper particles will aggregate and grow, and a thicker layer of silicon oxide aggregates will form underneath them; then the HF in the solution will react with the silicon oxide aggregates to generate SiF6 2- After the silicon oxide aggregates are removed, pits are formed below. Finally, a fourth mixed solution of HCl and H2O2 is used for the fourth treatment to remove the copper particles gathered above, thereby forming pits on the rounded velvet surface. The rounded velvet surface with pits is shown in FIG. Figure 4 shown.

[0044] The present invention also provides a texturized silicon wafer, which is obtained by adopting the texturizing method of the silicon wafer.

[0045] The present invention also provides a method for preparing a crystalline silicon cell. In the preparation method, the texturing process adopts the texturing method of the silicon wafer described in the present invention, and then the texturized silicon wafer is diffused, cleaned, coated, printed and sintered to prepare the crystalline silicon cell.

[0046] The present invention also provides a crystalline silicon cell, which is obtained by using the preparation method of the crystalline silicon cell. The crystalline silicon cell can be a TOPCon cell, a PERC cell, etc.

[0047] In the preparation method of crystalline silicon cells, the texturing method of the present invention is used to improve the passivation effect while maintaining the low reflectivity of the silicon wafer, thereby improving the open circuit voltage and short circuit current of the cell, thereby effectively improving the conversion efficiency of the crystalline silicon cell.

[0048] Hereinafter, the texturing method of the silicon wafer, the silicon wafer, the crystalline silicon cell and the preparation method thereof will be further described through the following specific embodiments.

[0049] Example 1

[0050] A pre-cleaning solution was prepared using NaOH and H2O2, wherein the concentration of NaOH in the pre-cleaning solution was 0.1wt%, and the concentration of H2O2 was 3wt%. The silicon wafer was placed in the pre-cleaning solution at 65°C for 100s, and then cleaned with deionized water for 80s.

[0051] An alkaline texturing solution is prepared using NaOH and texturing additives. The concentration of NaOH in the alkaline texturing solution is 2wt%, and the concentration of the texturing additive is 0.5wt%. At 70°C, the pre-cleaned silicon wafer is placed in the alkaline texturing solution for 250s to form a pyramid texturing surface, and then the silicon wafer is cleaned with deionized water for 80s.

[0052] A first mixed solution and a second mixed solution are prepared using HNO3 and HF respectively, wherein the concentration of HNO3 in the first mixed solution is 60wt%, and the concentration of HF is 15wt%, and the concentration of HNO3 in the second mixed solution is 15wt%, and the concentration of HF is 60wt%; the silicon wafer forming a pyramid velvet surface is immersed in the first mixed solution for 15s, and then immersed in the second mixed solution for 5s, and 10 cycles are performed in sequence to form a rounded velvet surface.

[0053] The third mixed solution is prepared by using CuCl2 and HF. 2+ The concentration of is 3wt%, the concentration of HF is 50wt%, the rounded suede surface is etched and immersed in the third mixed solution for 150s, and pits with copper particles gathered on the rounded suede surface are formed by point-induced etching.

[0054] A fourth mixed solution is prepared using HCl and H2O2, wherein the concentration of HCl in the fourth mixed solution is 2wt%, and the concentration of H2O2 is 5wt%. The aggregated copper particles are removed by soaking in the fourth mixed solution for 50s, leaving pits, thereby completing the texturing process.

[0055] After testing, the number of pits formed in this embodiment is 50 / cm 2 The width of the pit is 0.05 μm and the depth is 25 nm.

[0056] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0057] The electrical performance results of the battery cell formed in this embodiment are shown in Table 1.

[0058] Example 2

[0059] The difference between Example 2 and Example 1 is that: HNO3 and HF are used to respectively configure the first mixed solution and the second mixed solution, wherein the concentration of HNO3 in the first mixed solution is 80wt%, and the concentration of HF is 10wt%, and the concentration of HNO3 in the second mixed solution is 10wt%, and the concentration of HF is 80wt%; the silicon wafer forming the pyramid velvet surface is immersed in the first mixed solution for 20s, and then immersed in the second mixed solution for 10s, and 15 cycles are performed in sequence to form a rounded velvet surface.

[0060] After testing, the number of pits in the rounded suede formed in this embodiment is 60 / cm 2 The width of the pit is 0.06μm and the depth is 30nm.

[0061] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0062] The electrical performance results of the battery cell formed in this embodiment are shown in Table 1.

[0063] Example 3

[0064] The difference between Example 3 and Example 1 is that: CuCl2 and HF are used to prepare the third mixed solution, and the Cu 2+ The concentration of is 5wt%, the concentration of HF is 60wt%, the rounded suede surface is etched and immersed in the third mixed solution for 200s, and pits with copper particles gathered on the rounded suede surface are formed by point-induced etching.

[0065] After testing, the number of pits in the rounded suede formed in this embodiment is 80 / cm 2 The width of the pit is 0.07 μm and the depth is 40 nm.

[0066] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0067] The electrical performance results of the battery cell formed in this embodiment are shown in Table 1.

[0068] Comparative Example 1

[0069] A pre-cleaning solution was prepared using NaOH and H2O2, wherein the concentration of NaOH in the pre-cleaning solution was 0.1wt%, and the concentration of H2O2 was 3wt%. The silicon wafer was placed in the pre-cleaning solution at 65°C for 100s, and then cleaned with deionized water for 80s.

[0070] An alkaline texturing solution is prepared using NaOH and texturing additives. The concentration of NaOH in the alkaline texturing solution is 2wt%, and the concentration of the texturing additive is 0.5wt%. At 70°C, the pre-cleaned silicon wafer is placed in the alkaline texturing solution for 250s to form a pyramid texturing surface, and then the silicon wafer is cleaned with deionized water for 80s.

[0071] A first mixed solution and a second mixed solution are prepared using HNO3 and HF respectively, wherein the concentration of HNO3 in the first mixed solution is 60wt%, and the concentration of HF is 15wt%, and the concentration of HNO3 in the second mixed solution is 15wt%, and the concentration of HF is 60wt%; the silicon wafer forming a pyramid velvet surface is immersed in the first mixed solution for 15s, and then immersed in the second mixed solution for 5s, and 10 cycles are performed in sequence to form a rounded velvet surface.

[0072] The silicon wafer with a rounded velvet surface is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0073] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0074] Comparative Example 2

[0075] A pre-cleaning solution was prepared using NaOH and H2O2, wherein the concentration of NaOH in the pre-cleaning solution was 0.1wt%, and the concentration of H2O2 was 3wt%. The silicon wafer was placed in the pre-cleaning solution at 65°C for 100s, and then cleaned with deionized water for 80s.

[0076] An alkaline texturing solution is prepared using NaOH and texturing additives. The concentration of NaOH in the alkaline texturing solution is 2wt%, and the concentration of the texturing additive is 0.5wt%. At 70°C, the pre-cleaned silicon wafer is placed in the alkaline texturing solution for 250s to form a pyramid texturing surface, and then the silicon wafer is cleaned with deionized water for 80s.

[0077] The silicon wafer with pyramid velvet surface is formed into a battery cell structure through boron diffusion, cleaning, coating, printing and sintering processes.

[0078] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0079] Comparative Example 3

[0080] The difference between Comparative Example 3 and Example 1 is that: a mixed solution is prepared using HNO3 and HF, wherein the concentration of HNO3 in the mixed solution is 40wt%, and the concentration of HF is 40wt%; the silicon wafer forming the pyramid velvet surface is immersed in the mixed solution for 200s to form a rounded velvet surface.

[0081] After testing, the number of pits on the rounded suede surface formed in this comparative example is 5 / cm 2 , the width of the pit is 0.01μm and the depth is 2nm.

[0082] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0083] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0084] Comparative Example 4

[0085] The difference between Comparative Example 4 and Example 1 is that the first mixed solution and the second mixed solution are respectively prepared using HNO3 and HF, wherein the concentration of HNO3 in the first mixed solution is 15wt%, and the concentration of HF is 60wt%, and the concentration of HNO3 in the second mixed solution is 60wt%, and the concentration of HF is 15wt%.

[0086] After testing, the number of pits in the rounded suede formed in this comparative example is 20 / cm 2 , the width of the pit is 0.02μm and the depth is 4nm.

[0087] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0088] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0089] Comparative Example 5

[0090] The difference between Comparative Example 5 and Example 1 is that the silicon wafer with the pyramid velvet surface is immersed in the first mixed solution for 5 seconds, and then immersed in the second mixed solution for 15 seconds, and 10 cycles are performed in sequence to form a rounded velvet surface.

[0091] After testing, the number of pits in the rounded suede formed in this comparative example is 20 / cm2 , the width of the pit is 0.1μm and the depth is 10nm.

[0092] The silicon wafer with a rounded textured surface and pits is subjected to boron diffusion, cleaning, coating, printing and sintering processes to form a cell structure.

[0093] The electrical performance results of the battery cell formed in this comparative example are shown in Table 1.

[0094] Table 1

[0095] Uoc(V) Isc(A) FF(%) Eta(%) Suede reflectivity (%) Example 1 0.7196 11.619 82.75 25.24 3.29 Example 2 0.7201 11.621 82.88 25.35 3.16 Example 3 0.7198 11.620 82.79 25.29 3.25 Comparative Example 1 0.7193 11.530 82.56 24.98 11.2 Comparative Example 2 0.714 11.540 82.70 24.86 9.5 Comparative Example 3 0.715 11.545 82.60 25.00 8.8 Comparative Example 4 0.714 11.547 82.55 25.02 8.6 Comparative Example 5 0.714 11.548 82.59 15.04 8.5

[0096] In Table 1: Uoc represents open circuit voltage; Isc represents short circuit current; FF represents fill factor; Eta represents battery conversion efficiency.

[0097] It can be seen from Comparative Example 1 and Comparative Example 2 in Table 1 that since Comparative Example 1 only rounded the pyramid velvet surface, the passivation effect is enhanced and the open circuit voltage is increased, but the rounding loses part of the reflectivity, resulting in a decrease in the short-circuit current. This shows that only rounding the pyramid velvet surface can only improve the passivation effect but cannot achieve low reflectivity, and the battery conversion efficiency of the battery cell is low.

[0098] It can be seen from Example 1 and Comparative Example 1 in Table 1 that, since Example 1 performs metal etching on the rounded velvet surface to form nano-scale pits, the specific surface area of ​​the rounded pyramid velvet surface is increased, thereby reducing the reflectivity of the rounded velvet surface from 11.2% to 3.29%, so that the prepared battery cell can take into account both high passivation effect and low reflection performance, so that both the open circuit voltage and the short circuit current are improved, and the battery conversion efficiency of the battery cell is increased from 24.98% to 25.24%.

[0099] It can be seen from Example 1 and Comparative Example 3 in Table 1 that the velvet surface is rounded once with a mixed solution of hydrofluoric acid and nitric acid, and the relationship between the concentrations of hydrofluoric acid and nitric acid is not restricted, resulting in that silicon oxide cannot be well formed and removed during the rounding process, resulting in a poor rounding effect and affecting the subsequent effect of forming pits on the rounded velvet surface, thereby increasing the reflectivity of the battery and decreasing both the short-circuit current and the open-circuit voltage.

[0100] It can be seen from Example 1 and Comparative Example 4 in Table 1 that the nitric acid concentration of the first treatment is lower than the hydrofluoric acid concentration, and the nitric acid concentration of the second treatment is higher than the hydrofluoric acid concentration, resulting in incomplete removal of the sharp areas, resulting in poor rounding effect, and both the short-circuit current and the open-circuit voltage decreased.

[0101] It can be seen from Example 1 and Comparative Example 5 in Table 1 that the time of the first treatment is shorter than that of the second treatment, resulting in poor oxidation effect and thus poor rounding effect. The pits formed on the rounded velvet surface are also poor, and both the open circuit voltage and the short circuit current decrease.

[0102] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for texturing a silicon wafer, characterized in that: The following steps are involved: Forming pyramid velvet on silicon wafer; The pyramid velvet surface is subjected to rounding treatment to form a rounded velvet surface, comprising: placing a silicon wafer with the pyramid velvet surface in a first mixed solution for a first treatment, and then placing the silicon wafer in a second mixed solution for a second treatment, wherein the first treatment and the second treatment constitute a cycle, and the cycle is performed at least twice, wherein the first mixed solution and the second mixed solution both comprise HNO3 and HF, the mass fraction of HNO3 in the first mixed solution is greater than the mass fraction of HF, the mass fraction of HNO3 in the second mixed solution is less than the mass fraction of HF, and the time of the first treatment is greater than the time of the second treatment; Form pits on the rounded pile surface to complete the pile making, wherein the number of the pits is 10 / cm 2 ~100 pieces / cm 2 The width of the pit is 0.01 μm to 0.08 μm, and the depth is 5 nm to 50 nm.

2. The method for texturing a silicon wafer according to claim 1, characterized in that: The number of cycles is 5 to 20 times.

3. The method for texturing a silicon wafer according to claim 1, characterized in that: In the step of the first treatment, the time is 15s to 20s; And / or, in the step of the second treatment, the time is 5s to 10s.

4. The method for texturing a silicon wafer according to claim 1, characterized in that: The concentration of HNO3 in the first mixed solution is 40wt% to 80wt%, and the concentration of HF is 10wt% to 20wt%; And / or, the concentration of HNO3 in the second mixed solution is 10wt% to 20wt%, and the concentration of HF is 40wt% to 80wt%.

5. The method for texturing a silicon wafer according to any one of claims 1 to 4, characterized in that: Pits are formed on the rounded suede surface by metal etching.

6. The method for texturing a silicon wafer according to claim 5, characterized in that: The step of forming pits on the rounded velvet surface by metal etching includes: sequentially treating the rounded velvet surface for a third time and a fourth time with a third mixed solution, wherein the third mixed solution includes copper ions and HF, and the concentration of the copper ions is 1wt% to 5wt%, the concentration of the HF is 40wt% to 60wt%, the time of the third treatment is 100s to 200s, the fourth mixed solution includes HCl and H2O2, and the concentration of the HCl is 2wt% to 10wt%, the concentration of the H2O2 is 5wt% to 20wt%, and the time of the fourth treatment is 50s to 200s.

7. The method for texturing a silicon wafer according to any one of claims 1 to 4, characterized in that: The size of the base of a single pyramid velvet surface is 1μm-2.5μm.

8. A texturized silicon wafer obtained by the texturizing method for a silicon wafer as described in any one of claims 1 to 7.

9. A method for preparing a crystalline silicon battery, characterized in that: The invention comprises a method for texturing a silicon wafer using the method as described in any one of claims 1 to 7.

10. A crystalline silicon cell obtained by the method for preparing a crystalline silicon cell according to claim 9.

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