TBC battery with locally doped back surface and preparation method of TBC battery

Abstract

The invention discloses a TBC battery with a locally doped back surface and a preparation method of the TBC battery, and belongs to the field of TBC batteries. Wherein a P + + heavily-doped polycrystalline silicon layer and a P + lightly-doped polycrystalline silicon layer are arranged in the P + region or an N + + heavily-doped polycrystalline silicon layer and an N + lightly-doped polycrystalline silicon layer are arranged in the N + region to form a heavily-doped region and a lightly-doped region, so that the photoelectric conversion efficiency of the TBC battery can be effectively improved, the process is relatively simple, the cost increase is less, and the control difficulty is low.

Description

Technical Field

[0001] The present invention relates to the field of TBC batteries, and in particular to a TBC battery with local back doping and a preparation method thereof. Background Art

[0002] At present, a new generation of battery technology is emerging rapidly. Among them, back-contact cells (BC cells) are widely recognized by the industry for their significant efficiency advantages. Through continuous evolution and improvement, they have been recognized as the main path for high-efficiency photovoltaic cell technology.

[0003] The front of the BC battery structure has no grid lines blocking it, which increases the light-receiving area and improves the utilization rate of the incident light. Therefore, in the past 50 years, BC batteries have always maintained a clear advantage in conversion efficiency. In terms of process compatibility, the BC process is an open and highly scalable process that can be combined with TOPCon, HJT and other processes to further optimize the passivation structure, while making full use of the front side, and continuously improving the conversion efficiency of the battery. Among them, the TBC battery combines the high short-circuit current of IBC and the excellent passivation contact characteristics of TOPCon, improving the conversion efficiency through a good passivation structure, and opening up a new path for the future development of BC batteries.

[0004] The diffusion of the P and N regions of the current TBC cells is mostly carried out in a diffusion furnace. The principle of thermal diffusion is used to make the impurity atoms diffuse into the crystalline silicon body under heat. However, the diffusion furnace heats the entire surface of the cell and cannot heat the specified local area, so the doping concentration and diffusion depth of the entire plane of the cell are the same. However, for photovoltaic cells, at the contact point between the metal electrode and the doped layer, a high impurity concentration can reduce the contact resistance, but the battery Auger recombination rate increases, reducing the battery efficiency. Too low impurity concentration will cause the contact resistance between the metal and the doped layer to be too large, increasing electrical losses. Therefore, the ideal situation is to heavily dope the area where the metal contacts the doped layer, and lightly dope other areas, that is, selective doping (SE). Lasers not only have high-energy beams, which can promote the diffusion of impurity particles into the crystalline silicon by heating the impurity source, but can also accurately locate, apply different energies to different areas, control the impurity concentration and diffusion depth, and achieve selective doping. In order to further improve the conversion efficiency of batteries, the industry has proposed a variety of advanced laser technologies, such as laser SE and laser induced sintering (LIF). Therefore, the present invention adjusts the battery structure by combining laser SE with BC batteries, which can further improve the conversion efficiency of TBC batteries.

[0005] In view of this, the inventor conducted in-depth research on this demand, and thus the present case was produced. Summary of the invention

[0006] In order to improve the photoelectric conversion efficiency of TBC cells, the present invention provides a TBC cell with local back-doping and a preparation method thereof. On the basis of the existing BC cell structure and equipment, SE technology is added to form a heavily doped area, and the other areas are lightly doped areas. While improving the efficiency, the process is relatively simple, the cost increase is small, and the control difficulty is low. The SE technology is effectively applied to the back of the BC cell to improve the cell efficiency.

[0007] In order to achieve the purpose of the present invention, the following technical scheme is adopted:

[0008] The present invention provides a TBC cell with local back doping, comprising a crystalline silicon substrate, wherein the front side of the crystalline silicon substrate includes a front passivation layer and a front anti-reflection layer in sequence from the inside to the outside; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, and there is a spacing region between the P+ region and the N+ region, the P+ region includes a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer and a first electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate, and the N+ region includes a dielectric layer, an N+ region doped polysilicon layer, a back anti-reflection layer and a second electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate; the N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer and an N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than the surface concentration of the N+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the P+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the N++ heavily doped polysilicon layer.

[0009] Preferably, the N++ heavily doped polysilicon layer is inside the N+ lightly doped polysilicon layer, and the volume of the N++ heavily doped polysilicon layer accounts for 2% to 70% of the N+ lightly doped polysilicon layer.

[0010] More preferably, the volume of the N++ heavily doped polysilicon layer accounts for 2% to 55% of the volume of the N+ lightly doped polysilicon layer.

[0011] Preferably, the junction depth of the N+ region is 0.05-0.5 μm; the ECV surface concentration of the N+ lightly doped polysilicon layer is 2E19-4E20 cm -3 , the square resistance is 30-400Ω; the ECV surface concentration of the N++ heavily doped polysilicon layer is 2E20-1E21cm -3 , the square resistance is 20~60Ω.

[0012] Preferably, the junction depth of the P+ region is 0.1-0.5 μm; the ECV surface concentration of the P+ doped polysilicon layer is 2E19-5E20 cm -3 , the square resistance is 20~400Ω.

[0013] Preferably, the N+ region includes, from the inside to the outside, on the back surface of the crystalline silicon substrate, the dielectric layer, the N+ region doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode in sequence; the N+ region doped polysilicon layer includes the N+ lightly doped polysilicon layer and the N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than the surface concentration of the N+ lightly doped polysilicon layer; the second electrode penetrates the back anti-reflection layer and the back passivation layer to form an ohmic contact with the N++ heavily doped polysilicon layer.

[0014] Preferably, the thickness of the front passivation layer and the back passivation layer is 1-10 nm.

[0015] Preferably, the thickness of the front anti-reflection layer and the back anti-reflection layer is 20-200 nm.

[0016] The present invention also provides a method for preparing the above-mentioned back-side locally doped TBC battery, comprising the following steps:

[0017] Step 1, placing the N / P type silicon wafer into a tank-type alkaline solution for polishing;

[0018] Step 2, forming the P+ region: first forming the dielectric layer on the back of the silicon wafer, then forming an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon on the dielectric layer, and then performing boron doping to obtain the P+ doped polycrystalline silicon layer;

[0019] Step 3, partially removing the P+ region;

[0020] Step 4, the N+ region is formed: first, the dielectric layer is formed on the back of the silicon wafer, then an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer, and then phosphorus doping is performed to obtain the N+ lightly doped polycrystalline silicon layer; then, the PSG on the surface of the N+ lightly doped polycrystalline silicon layer is used as a doping source, the phosphorus source is secondary promoted, and the N++ heavily doped polycrystalline silicon layer is formed inside the N+ lightly doped polycrystalline silicon layer under local heat treatment;

[0021] Step 5: Partially remove the N+ region above the P+ region and part of the N+ region adjacent to the P+ region;

[0022] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0023] Step 7, depositing the front passivation layer on the front side of the silicon wafer or depositing the front passivation layer and the back passivation layer on the front and back sides of the silicon wafer respectively;

[0024] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer respectively;

[0025] Step nine: prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0026] Preferably, the local heat treatment in step 4 includes two methods. The first method is to use laser to perform local laser heating on the PSG on the surface of the N+ lightly doped polysilicon layer, and then perform heat treatment at a temperature of 850-960°C for 10-60 minutes to form the N++ heavily doped polysilicon layer inside the N+ lightly doped polysilicon layer. The second method is to locally clean and remove part of the PSG on the surface of the N+ lightly doped polysilicon layer, and use the unremoved PSG as a doping source to perform heat treatment at a temperature of 850-960°C for 10-60 minutes to form the N++ heavily doped polysilicon layer inside the N+ lightly doped polysilicon layer.

[0027] Preferably, in the laser doping technology in step 4, the power of the laser is 1-70 W, the wavelength is 300-700 nm, the scanning speed is 5000-60000 mm / s, and the frequency is 200-2000 kHz.

[0028] The present invention also provides a TBC cell with local back doping, comprising a crystalline silicon substrate, wherein the front surface of the crystalline silicon substrate includes a front passivation layer and a front anti-reflection layer in sequence from the inside to the outside; the back surface of the crystalline silicon substrate is provided with an alternating P+ region and an N+ region, and there is a spacing region between the P+ region and the N+ region, the N+ region includes a dielectric layer, an N+ doped polysilicon layer, a back anti-reflection layer and a first electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate, and the P+ region includes a dielectric layer, a P+ region doped polysilicon layer, a back anti-reflection layer and a second electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate; the P+ region doped polysilicon layer includes a P+ lightly doped polysilicon layer and a P++ heavily doped polysilicon layer, and the surface concentration of the P++ heavily doped polysilicon layer is greater than the surface concentration of the P+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the N+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the P++ heavily doped polysilicon layer.

[0029] Preferably, the P++ heavily doped polysilicon layer is inside the P+ lightly doped polysilicon layer, and the volume of the P++ heavily doped polysilicon layer accounts for 2% to 70% of the volume of the P+ lightly doped polysilicon layer.

[0030] More preferably, the volume of the P++ heavily doped polysilicon layer accounts for 2% to 55% of the volume of the P+ lightly doped polysilicon layer.

[0031] Preferably, the junction depth of the P+ region is 0.05-0.5 μm; the ECV surface concentration of the P+ lightly doped polysilicon layer is 2E19-5E20 cm -3 , the square resistance is 20~400Ω; the ECV surface concentration of the P++ heavily doped polysilicon layer is 2E20~8E20cm -3 , the square resistance is 20~80Ω.

[0032] Preferably, the junction depth of the N+ region is 0.1-0.5 μm, and the ECV surface concentration of the N+ doped polysilicon layer is 2E19-4E20 cm -3 , the square resistance is 30~400Ω.

[0033] Preferably, the P+ region is provided with the dielectric layer, the P+ region doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate; the P+ region doped polysilicon layer includes the P+ lightly doped polysilicon layer and the P++ heavily doped polysilicon layer, and the surface concentration of the P++ heavily doped polysilicon layer is greater than the surface concentration of the P+ lightly doped polysilicon layer; the second electrode penetrates the back anti-reflection layer and the back passivation layer to form an ohmic contact with the P++ heavily doped polysilicon layer.

[0034] Preferably, the thickness of the front passivation layer and the back passivation layer is 1-10 nm.

[0035] Preferably, the thickness of the front anti-reflection layer and the back anti-reflection layer is 20-200 nm.

[0036] The present invention also provides a method for preparing the above-mentioned back-side locally doped TBC battery, comprising the following steps:

[0037] Step 1, placing the N / P type silicon wafer into a tank-type alkaline solution for polishing;

[0038] Step 2, the N+ region is formed: firstly, the dielectric layer is formed on the back of the silicon wafer, then an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer, and then phosphorus is doped to obtain the N+ doped polycrystalline silicon layer;

[0039] Step 3, partially removing the N+ region;

[0040] Step 4, the P+ region is formed: first, the dielectric layer is formed on the back of the silicon wafer, and an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer, and then boron doping is performed to obtain the P+ lightly doped polycrystalline silicon layer; then, the BSG on the surface of the P+ lightly doped polycrystalline silicon layer is used as a doping source, and the boron source is secondary promoted, and the P++ heavily doped polycrystalline silicon layer is formed inside the P+ lightly doped polycrystalline silicon layer under local heat treatment;

[0041] Step 5, partially removing the P+ region above the N+ region and part of the p+ region adjacent to the N+ region;

[0042] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0043] Step 7, depositing the front passivation layer on the front side of the silicon wafer or depositing the front passivation layer and the back passivation layer on the front and back sides of the silicon wafer respectively;

[0044] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer respectively;

[0045] Step nine: prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0046] Preferably, the local heat treatment in step four includes two methods. The first method is to use laser to perform local laser heating on the BSG on the surface of the P+ lightly doped polysilicon layer, and then perform heat treatment at a temperature of 850-960°C and a time of 10-60 minutes to form the P++ heavily doped polysilicon layer inside the P+ lightly doped polysilicon layer. The second method is to locally clean and remove part of the BSG on the surface of the P+ lightly doped polysilicon layer, and use the unremoved BSG as a doping source to perform heat treatment at a temperature of 850-960°C and a time of 10-60 minutes to form the P++ heavily doped polysilicon layer inside the P+ lightly doped polysilicon layer.

[0047] Preferably, in the laser doping technology in step 4, the power of the laser is 1-70 W, the wavelength is 300-700 nm, the scanning speed is 5000-60000 mm / s, and the frequency is 200-2000 kHz.

[0048] The beneficial effects produced by the technical solution of the present invention are as follows:

[0049] (1) The present invention sets an N++ heavily doped polysilicon layer and an N+ lightly doped polysilicon layer in the N+ region, so that the P+ region and the N++ heavily doped polysilicon layer are separated more widely, and when the concentration of the N+ lightly doped polysilicon layer is lower, leakage can be reduced, the parallel resistance is higher, the fill factor is improved, and the open circuit voltage is increased. Similarly, by setting a P++ heavily doped polysilicon layer and a P+ lightly doped polysilicon layer in the P+ region, the N+ region and the P++ heavily doped polysilicon layer are separated more widely, and when the concentration of the P+ lightly doped polysilicon layer is lower, leakage can be reduced, the parallel resistance is higher, the fill factor is improved, and the open circuit voltage is increased.

[0050] (2) The present invention forms a P++ / P+ or N++ / N+ high-low junction by providing a P++ heavily doped polysilicon layer or an N++ heavily doped polysilicon layer, which contacts the metal electrode, thereby reducing the contact resistance between the back metal electrode and the doped polysilicon, which is beneficial to the collection of carriers, further increases the opening voltage, improves the conversion efficiency of the TBC battery, and helps solve the problem of burn-through damage to ultra-thin passivation contacts caused by high-temperature metal slurry. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 This is one of the schematic diagrams of the TBC battery structure in the present invention;

[0053] Figure 2 This is the second schematic diagram of the TBC battery structure in the present invention.

[0054] In the figure, 1. crystalline silicon substrate; 2. front passivation layer; 3. front anti-reflection layer; 4. dielectric layer; 5. P+ doped polysilicon layer; 6. back anti-reflection layer; 7. first electrode; 8. second electrode; 9. N+ lightly doped polysilicon layer; 10. N++ heavily doped polysilicon layer; 11. back passivation layer; 12. N+ doped polysilicon layer; 13. P+ lightly doped polysilicon layer; 14. P++ heavily doped polysilicon layer. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In order to improve the photoelectric conversion efficiency of TBC cells, this embodiment provides a TBC cell with local back doping and a preparation method thereof. Based on the existing BC cell structure and equipment, a heavily doped area is formed, and other areas are lightly doped areas. While improving the efficiency, the process is relatively simple, the cost increase is small, and the control difficulty is low. SE technology is effectively applied to the back of the BC cell to improve the cell efficiency. The specific implementation methods are as follows:

[0057] like Figure 1 As shown, a TBC cell with local back doping, the TBC cell comprises a crystalline silicon substrate 1, the front side of the crystalline silicon substrate 1 comprises a front passivation layer 2 and a front anti-reflection layer 3 in sequence from the inside to the outside; the back side surface of the crystalline silicon substrate 1 is provided with a P+ region and an N+ region arranged alternately, and there is a spacing region between the P+ region and the N+ region, the P+ region comprises a dielectric layer 4, a P+ doped polysilicon layer 5, a back anti-reflection layer 6 and a first electrode 7 in sequence from the inside to the outside of the back side surface of the crystalline silicon substrate 1, and the N+ region is arranged on the back side surface of the crystalline silicon substrate 1. The back surface includes, from the inside to the outside, a dielectric layer 4, an N+ region doped polysilicon layer, a back anti-reflection layer 6 and a second electrode 8; the N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer 9 and an N++ heavily doped polysilicon layer 10, and the surface concentration of the N++ heavily doped polysilicon layer 10 is greater than the surface concentration of the N+ lightly doped polysilicon layer 9; the first electrode 7 penetrates the back anti-reflection layer 6 to form an ohmic contact with the P+ doped polysilicon layer 5, and the second electrode 8 penetrates the back anti-reflection layer 6 to form an ohmic contact with the N++ heavily doped polysilicon layer 10.

[0058] As a preferred implementation, the N++ heavily doped polysilicon layer 10 is inside the N+ lightly doped polysilicon layer 9 , and the volume of the N++ heavily doped polysilicon layer 10 accounts for 2% to 70% of the volume of the N+ lightly doped polysilicon layer 9 .

[0059] As a more preferred implementation, the volume of the N++ heavily doped polysilicon layer 10 accounts for 2% to 55% of the volume of the N+ lightly doped polysilicon layer 9 .

[0060] As a preferred embodiment, the junction depth of the N+ region is 0.05-0.5 μm; the ECV surface concentration of the N+ lightly doped polysilicon layer 9 is 2E19-4E20 cm -3 , the square resistance is 30~400Ω; the ECV surface concentration of the N++ heavily doped polysilicon layer 10 is 2E20~1E21cm -3 , the square resistance is 20~60Ω.

[0061] As a preferred embodiment, the junction depth of the P+ region is 0.1-0.5 μm; the ECV surface concentration of the P+ doped polysilicon layer 5 is 2E19-5E20 cm -3 , the square resistance is 20~400Ω.

[0062] As a preferred embodiment, the N+ region includes a dielectric layer 4, the N+ region doped polysilicon layer, a back passivation layer 11, a back anti-reflection layer 6 and a second electrode 8 in sequence from the inside to the outside on the back surface of the crystalline silicon substrate 1; the N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer 9 and an N++ heavily doped polysilicon layer 10, and the surface concentration of the N++ heavily doped polysilicon layer 10 is greater than the surface concentration of the N+ lightly doped polysilicon layer 9; the second electrode 8 penetrates the back anti-reflection layer 6 and the back passivation layer 11 to form an ohmic contact with the N++ heavily doped polysilicon layer 10.

[0063] As a preferred embodiment, the thickness of the front passivation layer 2 and the back passivation layer 11 is 1-10 nm.

[0064] As a preferred embodiment, the thickness of the front anti-reflection layer 3 and the back anti-reflection layer 6 is 20-200 nm.

[0065] The present invention also provides a method for preparing the above-mentioned back-side locally doped TBC battery, comprising the following steps:

[0066] Step 1, placing the N / P type silicon wafer into a tank-type alkaline solution for polishing;

[0067] Step 2, forming the P+ region: first forming a dielectric layer 4 on the back of the silicon wafer, then forming an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon on the dielectric layer 4, and then performing boron doping to obtain the P+ doped polycrystalline silicon layer 5;

[0068] Step 3, partially removing the P+ region;

[0069] Step 4, the N+ region is formed: first, a dielectric layer 4 is formed on the back of the silicon wafer, then an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer 4, and then phosphorus doping is performed to obtain an N+ lightly doped polycrystalline silicon layer 9; then, the PSG on the surface of the N+ lightly doped polycrystalline silicon layer 9 is used as a doping source, and the phosphorus source is secondary promoted, and under local heat treatment, an N++ heavily doped polycrystalline silicon layer 10 is formed inside the N+ lightly doped polycrystalline silicon layer 9;

[0070] Step 5, partially removing the N+ region above the P+ region and part of the N+ region adjacent to the p+ region;

[0071] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0072] Step 7, depositing a front passivation layer 2 on the front side of the silicon wafer or depositing a front passivation layer 2 and a back passivation layer 11 on the front and back sides of the silicon wafer respectively;

[0073] Step eight, depositing a front anti-reflection layer 3 and a back anti-reflection layer 6 on the front and back surfaces of the silicon wafer respectively;

[0074] Step nine: prepare a first electrode 7 and a second electrode 8 on the P+ region and the N+ region respectively.

[0075] As a preferred embodiment, the local heat treatment in the step 4 includes two methods. The first method is to use a laser to perform local laser heating on the PSG on the surface of the N+ lightly doped polysilicon layer 9, and then perform heat treatment at a temperature of 850-960°C for 10-60 minutes to form an N++ heavily doped polysilicon layer 10 inside the N+ lightly doped polysilicon layer 9; the second method is to locally clean and remove part of the PSG on the surface of the N+ lightly doped polysilicon layer 9, and use the unremoved PSG as a doping source to perform heat treatment at a temperature of 850-960°C for 10-60 minutes to form an N++ heavily doped polysilicon layer 10 inside the N+ lightly doped polysilicon layer 9.

[0076] As a preferred implementation, in the laser doping technology described in step 4, the power of the laser is 1-70 W, the wavelength is 300-700 nm, the scanning speed is 5000-60000 mm / s, and the frequency is 200-2000 kHz.

[0077] The present invention also provides a TBC cell with local back doping, comprising a crystalline silicon substrate 1, wherein the front surface of the crystalline silicon substrate 1 includes a front passivation layer 2 and a front anti-reflection layer 3 in sequence from the inside to the outside; the back surface of the crystalline silicon substrate 1 is provided with a P+ region and an N+ region arranged alternately, and there is a spacing region between the P+ region and the N+ region, wherein the N+ region includes a dielectric layer 4, an N+ doped polycrystalline silicon layer 12, a back anti-reflection layer 6 and a first electrode 7 in sequence from the inside to the outside of the back surface of the crystalline silicon substrate 1, and the P+ region is arranged on the back surface of the crystalline silicon substrate 1. The surface of the surface includes a dielectric layer 4, a P+ region doped polysilicon layer, a back anti-reflection layer 6 and a second electrode 8 from the inside to the outside; the P+ region doped polysilicon layer includes a P+ lightly doped polysilicon layer 13 and a P++ heavily doped polysilicon layer 14, and the surface concentration of the P++ heavily doped polysilicon layer 14 is greater than the surface concentration of the P+ lightly doped polysilicon layer 13; the first electrode 7 penetrates the back anti-reflection layer 6 to form an ohmic contact with the N+ doped polysilicon layer 12, and the second electrode 8 penetrates the back anti-reflection layer 6 to form an ohmic contact with the P++ heavily doped polysilicon layer 14.

[0078] As a preferred implementation, the P++ heavily doped polysilicon layer 14 is inside the P+ lightly doped polysilicon layer 13 , and the volume of the P++ heavily doped polysilicon layer 14 accounts for 2% to 70% of the volume of the P+ lightly doped polysilicon layer 13 .

[0079] As a more preferred implementation, the volume of the P++ heavily doped polysilicon layer 14 accounts for 2% to 55% of the volume of the P+ lightly doped polysilicon layer 13 .

[0080] As a preferred embodiment, the junction depth of the P+ region is 0.05-0.5 μm; the ECV surface concentration of the P+ lightly doped polysilicon layer 13 is 2E19-5E20 cm -3 , the square resistance is 20~400Ω; the ECV surface concentration of the P++ heavily doped polysilicon layer 14 is 2E20~8E20cm -3 , the square resistance is 20~80Ω.

[0081] As a preferred embodiment, the junction depth of the N+ region is 0.1-0.5 μm, and the ECV surface concentration of the N+ doped polysilicon layer 12 is 2E19-4E20 cm -3 , the square resistance is 30~400Ω.

[0082] As a preferred embodiment, the P+ region is provided with a dielectric layer 4, the P+ region doped polysilicon layer, a back passivation layer 11, a back anti-reflection layer 6 and a second electrode 8 in sequence from the inside to the outside on the back surface of the crystalline silicon substrate 1; the P+ region doped polysilicon layer includes a P+ lightly doped polysilicon layer 13 and a P++ heavily doped polysilicon layer 14, and the surface concentration of the P++ heavily doped polysilicon layer 14 is greater than the surface concentration of the P+ lightly doped polysilicon layer 13; the second electrode 8 penetrates the back anti-reflection layer 6 and the back passivation layer 11 to form an ohmic contact with the P++ heavily doped polysilicon layer 14.

[0083] As a preferred embodiment, the thickness of the front passivation layer 2 and the back passivation layer 11 is 1-10 nm.

[0084] As a preferred embodiment, the thickness of the front anti-reflection layer 3 and the back anti-reflection layer 6 is 20-200 nm.

[0085] The present invention also provides a method for preparing the above-mentioned back-side locally doped TBC battery, comprising the following steps:

[0086] Step 1, placing the N / P type silicon wafer into a tank-type alkaline solution for polishing;

[0087] Step 2, the N+ region is formed: a dielectric layer 4 is first formed on the back of the silicon wafer, and then an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer 4, and then phosphorus is doped to obtain an N+ doped polycrystalline silicon layer 12;

[0088] Step 3, partially removing the N+ region;

[0089] Step 4, the P+ region is formed: first, a dielectric layer 4 is formed on the back of the silicon wafer, and an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer 4, and then boron doping is performed to obtain a P+ lightly doped polycrystalline silicon layer 13; then, BSG on the surface of the P+ lightly doped polycrystalline silicon layer 13 is used as a doping source, and the boron source is secondary promoted, and a P++ heavily doped polycrystalline silicon layer 14 is formed inside the P+ lightly doped polycrystalline silicon layer 13 under local heat treatment;

[0090] Step 5: Partially remove the p+ region above the N+ region and part of the P+ region adjacent to the N+ region;

[0091] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0092] Step 7, depositing a front passivation layer 2 on the front side of the silicon wafer or depositing a front passivation layer 2 and a back passivation layer 11 on the front and back sides of the silicon wafer respectively;

[0093] Step eight, depositing a front anti-reflection layer 3 and a back anti-reflection layer 6 on the front and back surfaces of the silicon wafer respectively;

[0094] Step nine: prepare a first electrode 7 and a second electrode 8 on the P+ region and the N+ region respectively.

[0095] As a preferred embodiment, the local heat treatment in step four includes two methods. The first method is to use a laser to perform local laser heating on the BSG on the surface of the P+ lightly doped polysilicon layer 13, and then perform heat treatment at a temperature of 850-960°C for 10-60 minutes to form a P++ heavily doped polysilicon layer 14 inside the P+ lightly doped polysilicon layer 13; the second method is to locally clean and remove part of the BSG on the surface of the P+ lightly doped polysilicon layer 13, and use the unremoved BSG as a doping source to perform heat treatment at a temperature of 850-960°C for 10-60 minutes to form a P++ heavily doped polysilicon layer 14 inside the P+ lightly doped polysilicon layer 13.

[0096] Preferably, in the laser doping technology in step 4, the power of the laser is 1-70 W, the wavelength is 300-700 nm, the scanning speed is 5000-60000 mm / s, and the frequency is 200-2000 kHz.

[0097] The beneficial effects of a back-locally doped TBC battery and a preparation method thereof in the present invention are further reviewed through several groups of embodiments.

[0098] Embodiment 1:

[0099] A method for preparing a TBC battery with local back-side doping in this embodiment 1 comprises the following steps:

[0100] Step 1, placing the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0101] Step 2: Formation of the N+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then an amorphous silicon layer is formed on the dielectric layer, and then boron doping is performed to obtain the N+ doped polysilicon layer, and the ECV surface concentration is 2E19cm -3 , junction depth is 0.1μm, square resistance is 400Ω;

[0102] Step 3, after laser patterning on the back side of the silicon wafer, alkali etching is performed to partially remove the N+ region;

[0103] Step 4: Formation of the P+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then an amorphous silicon layer is formed on the dielectric layer, and then boron doping is performed to obtain the P+ lightly doped polysilicon layer, with an ECV surface concentration of 2E19cm -3, square resistance 400Ω; then the BSG on the surface of the P+ lightly doped polysilicon layer is used as a doping source, and through laser doping technology, the laser power is 35W, the wavelength is 500nm, the scanning speed is 32500mm / s, the frequency is 1100kHz, the phosphorus source is secondary promoted, and then heat treatment is performed at a temperature of 850℃ for 10min to form the P++ heavily doped polysilicon layer inside the P+ lightly doped polysilicon layer, and the ECV surface concentration is 2E20cm -3 , square resistance 80Ω, the junction depth of the P+ region is 0.05μm, and the volume of the P++ heavily doped polysilicon layer accounts for 2% of the P+ lightly doped polysilicon layer;

[0104] Step 5: Partially remove the p+ region above the N+ region and part of the P+ region adjacent to the N+ region;

[0105] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0106] Step 7, depositing the front passivation layer on the front side of the silicon wafer with a thickness of 1 nm;

[0107] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 20 nm;

[0108] Step nine: prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0109] Comparative Example 1:

[0110] The preparation method in this comparative example 1, except step 4, is to first form the dielectric layer on the back of the silicon wafer, then form an amorphous silicon layer on the dielectric layer, and then perform boron doping to obtain the P+ lightly doped polycrystalline silicon layer, and the ECV surface concentration is 2E19cm -3 , square resistance 400Ω.

[0111] The other steps are the same as in Example 1.

[0112] Embodiment 2:

[0113] A method for preparing a TBC battery with local back-side doping in this embodiment 2 comprises the following steps:

[0114] Step 1, placing the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0115] Step 2: Formation of the P+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then a polysilicon layer is formed on the dielectric layer, and then boron doping is performed to obtain the P+ doped polysilicon layer, and the ECV surface concentration is 2E19cm -3, junction depth is 0.1μm, square resistance is 400Ω;

[0116] Step 3, after laser patterning on the back side of the silicon wafer, alkali etching is performed to partially remove the P+ region;

[0117] Step 4: Formation of the N+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then a polysilicon layer is formed on the dielectric layer, and then boron doping is performed to obtain the N+ lightly doped polysilicon layer, and the ECV surface concentration is 2E19cm -3 , square resistance 400Ω; then the BSG on the surface of the N+ lightly doped polysilicon layer is used as a doping source, and the laser doping technology is used. The power of the laser is 35W, the wavelength is 500nm, the scanning speed is 32500mm / s, the frequency is 1100kHz, the phosphorus source is secondary promoted, and then the heat treatment is promoted at a temperature of 960℃ for 60min to form the N++ heavily doped polysilicon layer inside the N+ lightly doped polysilicon layer. The ECV surface concentration is 2E20cm -3 , square resistance 60Ω, the junction depth of the N+ region is 0.05μm, and the volume of the N++ heavily doped polysilicon layer accounts for 55% of the volume of the N+ lightly doped polysilicon layer;

[0118] Step 5: Partially remove the N+ region above the P+ region and part of the N+ region adjacent to the P+ region;

[0119] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0120] Step 7, depositing the front passivation layer and the back passivation layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 1 nm;

[0121] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 20 nm;

[0122] Step nine: prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0123] Comparative Example 2:

[0124] The preparation method in this comparative example 2, except step 4, is to first form the dielectric layer on the back of the silicon wafer, then form a polysilicon layer on the dielectric layer, and then perform phosphorus doping to obtain the N+ lightly doped polysilicon layer, and the ECV surface concentration is 2E19cm -3 , square resistance 400Ω.

[0125] The other steps are the same as in Example 2.

[0126] Embodiment 3:

[0127] A method for preparing a TBC battery with local back-side doping in this embodiment 3 comprises the following steps:

[0128] Step 1, placing the P-type silicon wafer in a tank-type alkaline solution for polishing;

[0129] Step 2: Formation of the N+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then a layer of amorphous silicon and polycrystalline silicon mixed layer is formed on the dielectric layer, and then boron doping is performed to obtain the N+ doped polycrystalline silicon layer, and the ECV surface concentration is 4E20cm -3 , junction depth is 0.5μm, square resistance is 30Ω;

[0130] Step 3, after laser patterning on the back side of the silicon wafer, alkali etching is performed to partially remove the N+ region;

[0131] Step 4: Formation of the P+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then a layer of amorphous silicon and polysilicon mixed layer is formed on the dielectric layer, and then boron doping is performed to obtain the P+ lightly doped polysilicon layer, and the ECV surface concentration is 5E20cm -3 , square resistance 40Ω; then the BSG on the surface of the P+ lightly doped polysilicon layer is used as a doping source, and the laser doping technology is used. The power of the laser is 35W, the wavelength is 500nm, the scanning speed is 32500mm / s, and the frequency is 1100kHz. The phosphorus source is secondary promoted, and then the heat treatment is promoted at a temperature of 900℃ for 35min. The P++ heavily doped polysilicon layer is formed inside the P+ lightly doped polysilicon layer, and the ECV surface concentration is 8E20cm -3 , square resistance 20Ω, the junction depth of the P+ region is 0.5μm, and the volume of the P++ heavily doped polysilicon layer accounts for 55% of the volume of the P+ lightly doped polysilicon layer;

[0132] Step 5: Partially remove the p+ region above the N+ region and part of the P+ region adjacent to the N+ region;

[0133] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0134] Step 7, depositing the front passivation layer and the back passivation layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 10 nm;

[0135] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 200 nm;

[0136] Step nine: prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0137] Comparative Example 3:

[0138] The preparation method in this comparative example 3, except step 4, is to first form the dielectric layer on the back of the silicon wafer, then form a layer of amorphous silicon and polycrystalline silicon mixed layer on the dielectric layer, and then perform boron doping to obtain the P+ lightly doped polycrystalline silicon layer, and the ECV surface concentration is 5E20cm -3 , square resistance 40Ω.

[0139] The other steps are the same as in Example 3.

[0140] Embodiment 4:

[0141] A method for preparing a TBC battery with local back-side doping in this embodiment 4 comprises the following steps:

[0142] Step 1, placing the P-type silicon wafer in a tank-type alkaline solution for polishing;

[0143] Step 2: Formation of the P+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then a polysilicon layer is formed on the dielectric layer, and then boron doping is performed to obtain the P+ doped polysilicon layer, and the ECV surface concentration is 5E20cm -3 , junction depth is 0.5μm, square resistance is 40Ω;

[0144] Step 3, after laser patterning on the back side of the silicon wafer, alkali etching is performed to partially remove the P+ region;

[0145] Step 4: Formation of the N+ region: First, the dielectric layer is formed on the back of the silicon wafer, and then a polysilicon layer is formed on the dielectric layer, and then boron doping is performed to obtain the N+ lightly doped polysilicon layer, with an ECV surface concentration of 4E20cm -3 , square resistance 30Ω; then the BSG on the surface of the N+ lightly doped polysilicon layer is used as a doping source, and the laser doping technology is used. The power of the laser is 35W, the wavelength is 500nm, the scanning speed is 32500mm / s, the frequency is 1100kHz, the phosphorus source is secondary promoted, and then the heat treatment is promoted at a temperature of 930℃ for 50min. The N++ heavily doped polysilicon layer is formed inside the N+ lightly doped polysilicon layer, and the ECV surface concentration is 1E21cm -3 , square resistance 20Ω, the junction depth of the N+ region is 0.5μm, and the volume of the N++ heavily doped polysilicon layer accounts for 70% of the N+ lightly doped polysilicon layer;

[0146] Step 5: Partially remove the N+ region above the P+ region and part of the N+ region adjacent to the P+ region;

[0147] Step six, texturing the front side of the silicon wafer to form a pyramid structure;

[0148] Step 7, depositing the front passivation layer and the back passivation layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 5 nm;

[0149] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 100 nm;

[0150] Step nine: prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0151] Comparative Example 4:

[0152] The preparation method in this comparative example 4, except that step 4 is only to form a dielectric layer on the back of the silicon wafer, and then form an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon on the dielectric layer, and then perform phosphorus doping to obtain the N+ lightly doped polycrystalline silicon layer, the ECV surface concentration is 4E20cm -3 , square resistance 30Ω.

[0153] The other steps are the same as in Example 4.

[0154] The performance of the TBC batteries obtained in the above four groups of embodiments and comparative examples is tested, and the results are as follows:

[0155] Table 1 TBC battery performance test results of Examples 1 to 4 and Comparative Examples 1 to 4

[0156]

[0157]

[0158] It can be seen from Table 1 that the TBC cells prepared in Examples 1 to 4 of the present application have higher conversion efficiency, larger open circuit voltage, short circuit current and fill factor compared with their comparative examples 1 to 4, respectively, by forming a P++ heavily doped polysilicon layer on the surface of the P+ lightly doped polysilicon layer or forming an N++ heavily doped polysilicon layer on the surface of the N+ lightly doped polysilicon layer. In addition, when the volume of the heavily doped layer in the TBC cells prepared in Examples 1 to 4 accounts for 2 to 55% of the volume of the lightly doped layer, the conversion efficiency of the TBC cell is higher.

[0159] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A TBC battery with local back doping, characterized in that: The invention comprises a crystalline silicon substrate, wherein the front surface of the crystalline silicon substrate comprises a front passivation layer and a front anti-reflection layer in sequence from the inside to the outside; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, and there is a spacing region between the P+ region and the N+ region, wherein the P+ region comprises a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer and a first electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate, and the N+ region comprises a dielectric layer, an N+ region doped polysilicon layer, a back anti-reflection layer and a second electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate; The N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer and an N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than the surface concentration of the N+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the P+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the N++ heavily doped polysilicon layer.

2. A TBC cell with local back doping according to claim 1, characterized in that: The N++ heavily doped polysilicon layer is inside the N+ lightly doped polysilicon layer, and the volume of the N++ heavily doped polysilicon layer accounts for 2% to 70% of the N+ lightly doped polysilicon layer.

3. A TBC cell with local back doping according to claim 1, characterized in that: The junction depth of the N+ region is 0.05-0.5 μm; the ECV surface concentration of the N+ lightly doped polysilicon layer is 2E19-4E20 cm -3 , the square resistance is 30-400Ω; the ECV surface concentration of the N++ heavily doped polysilicon layer is 2E20-1E21cm -3 , the square resistance is 20~60Ω.

4. A TBC cell with local back doping according to claim 1, characterized in that: The junction depth of the P+ region is 0.1-0.5 μm, and the ECV surface concentration of the P+ doped polysilicon layer is 2E19-5E20 cm -3 , the square resistance is 20~400Ω.

5. A TBC battery with local back doping, characterized in that: A crystalline silicon substrate is included, wherein the front surface of the crystalline silicon substrate includes a front passivation layer and a front anti-reflection layer in sequence from the inside to the outside; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, and there is a spacing region between the P+ region and the N+ region, the N+ region includes a dielectric layer, an N+ doped polysilicon layer, a back anti-reflection layer and a first electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate, and the P+ region includes a dielectric layer, a P+ region doped polysilicon layer, a back anti-reflection layer and a second electrode in sequence from the inside to the outside on the back surface of the crystalline silicon substrate; The P+ region doped polysilicon layer includes a P+ lightly doped polysilicon layer and a P++ heavily doped polysilicon layer, and the surface concentration of the P++ heavily doped polysilicon layer is greater than the surface concentration of the P+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the N+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the P++ heavily doped polysilicon layer.

6. A TBC cell with local back doping according to claim 5, characterized in that: The P++ heavily doped polysilicon layer is inside the P+ lightly doped polysilicon layer, and the volume of the P++ heavily doped polysilicon layer accounts for 2% to 70% of the P+ lightly doped polysilicon layer.

7. A TBC cell with local back doping according to claim 5, characterized in that: The junction depth of the P+ region is 0.05-0.5 μm; the ECV surface concentration of the P+ lightly doped polysilicon layer is 2E19-5E20 cm -3 , the square resistance is 20~400Ω; the ECV surface concentration of the P++ heavily doped polysilicon layer is 2E20~8E20cm -3 , the square resistance is 20~80Ω.

8. A TBC cell with local back doping according to claim 5, characterized in that: The junction depth of the P+ region is 0.1-0.5 μm, and the ECV surface concentration of the N+ doped polysilicon layer is 2E19-4E20 cm -3 , the square resistance is 30~400Ω.

9. A method for preparing a TBC battery with local back doping according to any one of claims 1 to 4, characterized in that: The steps include: Step 1, placing the N / P type silicon wafer in a tank-type alkaline solution for polishing; Step 2, forming the P+ region: first forming the dielectric layer on the back of the silicon wafer, then forming an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon on the dielectric layer, and then performing boron doping to obtain the P+ doped polycrystalline silicon layer; Step 3, partially removing the P+ region; Step 4, the N+ region is formed: first, the dielectric layer is formed on the back of the silicon wafer, then an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer, and then phosphorus doping is performed to obtain the N+ lightly doped polycrystalline silicon layer; then, the PSG on the surface of the N+ lightly doped polycrystalline silicon layer is used as a doping source, the phosphorus source is secondary promoted, and the N++ heavily doped polycrystalline silicon layer is formed inside the N+ lightly doped polycrystalline silicon layer under local heat treatment; Step 5: Texturing the front side of the silicon wafer to form a pyramid structure; Step 6, depositing the front passivation layer on the front side of the silicon wafer or depositing the front passivation layer and the back passivation layer on the front and back sides of the silicon wafer respectively; Step 7, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer respectively; Step eight, preparing the first electrode and the second electrode on the P+ region and the N+ region respectively.

10. A method for preparing a TBC battery with local back doping according to any one of claims 5 to 8, characterized in that: The steps include: Step 1, placing the N / P type silicon wafer in a tank-type alkaline solution for polishing; Step 2, the N+ region is formed: firstly, the dielectric layer is formed on the back of the silicon wafer, then an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer, and then phosphorus is doped to obtain the N+ doped polycrystalline silicon layer; Step 3, partially removing the N+ region; Step 4, the P+ region is formed: first, the dielectric layer is formed on the back of the silicon wafer, and an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer, and then boron doping is performed to obtain the P+ lightly doped polycrystalline silicon layer; then, the BSG on the surface of the P+ lightly doped polycrystalline silicon layer is used as a doping source, and the boron source is secondary promoted, and the P++ heavily doped polycrystalline silicon layer is formed inside the P+ lightly doped polycrystalline silicon layer under local heat treatment; Step 5: Texturing the front side of the silicon wafer to form a pyramid structure; Step 6, depositing the front passivation layer on the front side of the silicon wafer or depositing the front passivation layer and the back passivation layer on the front and back sides of the silicon wafer respectively; Step 7, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer respectively; Step eight, preparing the first electrode and the second electrode on the P+ region and the N+ region respectively.

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