Wafer hybrid bonding surface planarization process method and chemical mechanical polishing equipment

Abstract

The invention provides a mixed bonding surface planarization process method of a wafer and chemical mechanical polishing equipment. The method comprises the following steps: controlling a grinding head to adsorb a first wafer to be subjected to surface planarization treatment, and grinding the first wafer on a first grinding pad to remove a copper film above a groove of the first wafer so as to obtain a second wafer; controlling the grinding head to move to a second grinding pad, and grinding the second wafer on the second grinding pad so as to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer and copper with the same thickness as the dielectric layer in the groove, and obtaining a third wafer with an exposed interface layer; controlling the grinding head to move to a third grinding pad, and grinding the third wafer on the third grinding pad, so that the surface height of the interface layer is the same as the surface height of the copper in the groove, and obtaining the wafer with the flattened surface; wherein the hardness of the third polishing pad is smaller than the hardness of the first polishing pad and the hardness of the second polishing pad. According to the invention, the wafer with a flat and smooth surface can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a hybrid bonding surface planarization process method for a wafer. Background Art

[0002] During wafer-level hybrid bonding, the large surface height difference (dishing) on ​​the wafer will form bonding bubble defects after the hybrid bonding process, affecting the yield of the chip. Therefore, the surface of the wafer needs to be treated with chemical mechanical planarization (CMP) to obtain a flat and smooth surface.

[0003] In the related technology, the copper layer and the dielectric layer are mainly ground, but large copper depressions may be formed during the grinding process, resulting in large surface height differences on the wafer surface, affecting the hybrid bonding of the wafer and the yield of the chip. Summary of the invention

[0004] The embodiment of the present invention provides a hybrid bonding surface planarization process method and chemical mechanical polishing equipment for a wafer, so as to repair copper depressions on the surface of the wafer, reduce the surface height difference, and obtain a flat and smooth surface.

[0005] In a first aspect, an embodiment of the present invention provides a hybrid bonding surface planarization process method for a wafer, comprising:

[0006] Controlling the grinding head to absorb the first wafer to be surface-planarized, and grinding the first wafer on a first grinding pad to remove the copper film above the groove of the first wafer, thereby obtaining a second wafer;

[0007] Controlling the grinding head to move to a second grinding pad, and grinding the second wafer on the second grinding pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the groove with the same thickness as the dielectric layer, to obtain a third wafer with an exposed interface layer;

[0008] The grinding head is controlled to move to a third grinding pad, and the third wafer is ground on the third grinding pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than the hardness of the first grinding pad and the hardness of the second grinding pad.

[0009] In a possible implementation, controlling a grinding head to adsorb a first wafer to be planarized, and grinding the first wafer on a first grinding pad to remove a copper film above a groove of the first wafer to obtain a second wafer includes:

[0010] Controlling the grinding head to absorb the first wafer to be processed for surface flattening;

[0011] Pre-flowing a first polishing liquid on the first polishing pad; wherein the first polishing liquid is a polishing liquid for removing a copper thin film;

[0012] Grinding the surface of the first wafer for the first time on a first grinding pad, and monitoring the thickness of the copper film on the surface of the first wafer;

[0013] When the thickness of the copper film reaches a first preset thickness, grinding the surface of the first wafer for a second time, and monitoring the thickness of the copper film;

[0014] When the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the groove to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

[0015] In a possible implementation, before controlling the grinding head to move to the second grinding pad and grinding the second wafer on the second grinding pad, the method further includes:

[0016] Determining a second polishing liquid according to a preset first selection ratio of the removal rate of the dielectric layer and the removal rate of copper;

[0017] pre-flowing the second polishing liquid on the second polishing pad;

[0018] Before controlling the grinding head to move to the third grinding pad and grinding the third wafer on the third grinding pad, the method further includes:

[0019] Determining a third polishing liquid according to a preset second selection ratio of the interface layer removal rate and the copper removal rate;

[0020] The third polishing liquid is pre-flowed on the third polishing pad.

[0021] In a possible implementation, the removal rate of the copper film in the third grinding is lower than that in the first grinding, and the removal rate of the copper film in the third grinding is lower than that in the second grinding.

[0022] In a possible implementation, the first polishing pad and the second polishing pad are hard polishing pads, and the hardness of the first polishing pad is the same as the hardness of the second polishing pad;

[0023] The third polishing pad is a soft polishing pad.

[0024] In a possible implementation, the first selection ratio ranges from 2.6 to 3.2;

[0025] The second selection ratio ranges from 2.0 to 2.5.

[0026] In a possible implementation, the flow rates of the second polishing liquid and the third polishing liquid range from 200 mL / min to 300 mL / min.

[0027] In a possible implementation, a grinding pressure for grinding the first wafer on the first grinding pad ranges from 1.2 psi to 2.5 psi;

[0028] The grinding pressure of grinding the second wafer on the second grinding pad is in the range of 1.3 psi to 2.0 psi;

[0029] The grinding pressure of grinding the third wafer on the third grinding pad ranges from 1.2 psi to 1.6 psi.

[0030] In a second aspect, an embodiment of the present invention provides another hybrid bonding surface planarization process method for a wafer, comprising:

[0031] Controlling the grinding head to absorb the first wafer to be surface-planarized, and grinding the first wafer on a first grinding pad to remove the copper film of a preset thickness above the groove of the first wafer, to obtain a fourth wafer;

[0032] Controlling the grinding head to move to the second grinding pad, and grinding the fourth wafer on the second grinding pad to remove the remaining thickness of the copper film above the groove of the fourth wafer to obtain a fifth wafer;

[0033] The grinding head is controlled to move onto the third grinding pad, and the fifth wafer is ground on the third grinding pad so that the interface layer of the fifth wafer is exposed, and the surface height of the interface layer is the same as the surface height of the copper in the groove, so as to obtain a wafer with a flattened surface.

[0034] In a third aspect, an embodiment of the present invention provides a chemical mechanical polishing device, comprising a grinding head, a first grinding pad, a second grinding pad, a third grinding pad, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the method described in the first aspect or any possible implementation of the first aspect are implemented, or, when the processor executes the computer program, the steps of the method described in the second aspect are implemented.

[0035] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect or any possible implementation method of the first aspect are implemented.

[0036] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0037] The embodiment of the present invention grinds the wafer surface three times, and the surface height difference can be repaired to maintain it within a stable range, thereby reducing the impact on hybrid bonding. The copper film above the groove can be removed by the first grinding, and a larger copper depression will be formed at this time; the dielectric layer, the barrier layer, and the copper in the groove with the same thickness as the dielectric layer are removed by the second grinding, and the amount of copper removed during the grinding process can be reduced, and the copper depression can be repaired, so that the height difference between the surface of the exposed interface layer and the surface of the copper in the groove is reduced; and the third grinding is performed to remove part of the interface layer and part of the copper in the groove, and the amount of copper removed during the grinding process can also be reduced, and the copper depression can be further repaired, so that the surface height of the interface layer is the same as the surface height of the copper in the groove, and the surface height difference of the wafer is reduced, thereby obtaining a flat and smooth surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 This is an application scenario diagram of a hybrid bonding surface planarization process method for a wafer provided by an embodiment of the present invention;

[0040] Figure 2 is a schematic structural diagram of a first wafer to be subjected to surface planarization treatment provided by an embodiment of the present invention;

[0041] Figure 3 It is a flow chart of a wafer hybrid bonding surface planarization process method provided by an embodiment of the present invention;

[0042] Figure 4 It is a schematic flow chart of a hybrid bonding surface planarization process method for a wafer provided by an embodiment of the present invention;

[0043] Figure 5 It is a flow chart of another wafer hybrid bonding surface planarization process method provided by an embodiment of the present invention;

[0044] Figure 6 It is a schematic flow chart of a hybrid bonding surface planarization process method for a wafer provided by an embodiment of the present invention;

[0045] Figure 7 is a schematic structural diagram of a wafer after wafer-level hybrid bonding provided by an embodiment of the present invention;

[0046] Figure 8 It is a structural schematic diagram of a hybrid bonding surface planarization process device for a wafer provided in an embodiment of the present invention;

[0047] Fig. 9 Schematic diagram of a chemical mechanical polishing device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0049] The inventors have found that in order to perform wafer-level hybrid bonding, it is usually necessary to maintain a small surface height difference on the wafer surface. However, during the process of grinding and flattening the wafer, a large copper depression (Cudishing) may be formed on the wafer surface, resulting in the formation of bonding bubble defects after the hybrid bonding process, thereby affecting the yield of the chip. Therefore, it is necessary to consider a new hybrid bonding surface flattening process method for wafers.

[0050] In order to reduce the height difference of the wafer surface, in an embodiment of the present invention, the wafer surface is grinded multiple times. The copper film on the wafer surface is first removed by grinding, and then the dielectric layer and the interface layer on the wafer surface are grinded to repair the copper depressions formed when the copper film is removed, thereby reducing the height difference of the wafer surface and obtaining a flat and smooth surface.

[0051] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0052] See also Figure 1 The application scenario diagram of the hybrid bonding surface planarization process method for wafers shown in the figure, Figure 1, a partial structure of a chemical mechanical polishing device is shown, which includes a first polishing pad, a second polishing pad, a third polishing pad and at least one polishing head, wherein the polishing head can move, such as rotating along the axis where the polishing head is located, and can be set according to the placement of the polishing pads. The polishing head can also absorb the wafer, and when the polishing head moves, it can drive the absorbed wafer to move together.

[0053] Here, the grinding pad can be Figure 1 As shown, they are sequentially placed on three grinding discs, and can be selected according to actual needs. For example, only the first grinding disc and the second grinding disc can be used for grinding, and they can be set according to specific process requirements.

[0054] In addition, four grinding heads can be provided, three of which correspond to one grinding disk respectively, so that the wafer adsorbed on the grinding head can be ground on the corresponding grinding disk, so that three wafers can be ground at the same time, and as the grinding head rotates, each wafer can be ground on three grinding disks in turn, thereby improving the efficiency of planarizing the hybrid bonding surface of the wafer.

[0055] Figure 2 A schematic structural diagram of a first wafer to be planarized is shown, wherein an interface layer (the material of the interface layer here may be SiCN) is formed on the surface of the first wafer, a dielectric layer (Dielectric) is formed on the interface layer, a groove is also formed on the surface of the first wafer, a barrier layer (Barrier) is formed on the dielectric layer and the groove; the groove is filled with copper (Cu), and the copper is higher than the groove, forming a copper film on the surface of the first wafer.

[0056] See also Figure 3 The implementation flow chart of a hybrid bonding surface planarization process method for a wafer provided by an embodiment of the present invention is shown, and is described in detail as follows:

[0057] Step S301, controlling the grinding head to adsorb the first wafer to be planarized, and grinding the first wafer on the first grinding pad to remove the copper film of a preset thickness above the groove of the first wafer, to obtain a fourth wafer.

[0058] In this embodiment, the grinding head can adsorb the first wafer in the area to be processed. The area to be processed is where the first wafer to be processed for surface flattening is placed, and can be a fixed area or an area with a conveyor belt.

[0059] The grinding head can be moved to the first grinding pad by moving or rotating, and the first round of grinding is performed on the first grinding pad.

[0060] See also Figure 4The schematic flow chart of a hybrid bonding surface planarization process method for a wafer is shown. After the first round of grinding, the thickness of the copper film on the surface of the fourth wafer is reduced.

[0061] Step S302, controlling the grinding head to move to the second grinding pad, and grinding the fourth wafer on the second grinding pad to remove the remaining thickness of the copper film above the groove of the fourth wafer, to obtain a fifth wafer.

[0062] In this embodiment, after the first round of grinding is completed, the grinding head can be further moved or rotated so that the grinding head is located on the second grinding pad and a second round of grinding is performed to remove the copper film above the groove. Figure 4 The schematic diagram of a process flow of a hybrid bonding surface planarization process for a wafer is shown. After the second round of grinding, the surface of the fifth wafer obtained has no copper film. In addition, due to the grinding of copper, part of the copper in the groove is also removed, resulting in copper depressions on the surface of the fifth wafer, that is, the surface of the copper in the groove is lower than the surface of the surrounding barrier layer.

[0063] Step S303, control the grinding head to move to the third grinding pad, and grind the fifth wafer on the third grinding pad to expose the interface layer of the fifth wafer, and the surface height of the interface layer is the same as the surface height of the copper in the groove, to obtain a wafer with a flat surface.

[0064] In this embodiment, after the second round of grinding is completed, considering the copper depression, in order to achieve the flatness of the wafer surface, the copper depression can be repaired to reduce the surface height difference.

[0065] Here, the third round of grinding is continued on the fifth wafer. During the grinding process, more dielectric layers and interface layers can be removed, thereby reducing the surface height difference of the wafer and obtaining a wafer with a flat surface.

[0066] See also Figure 4 The flow chart of a hybrid bonding surface planarization process method for a wafer is shown. After the third round of grinding, the surface height difference of the wafer after surface planarization is significantly reduced, which can meet the requirements of wafer-level hybrid bonding.

[0067] Optionally, the polishing pressure and polishing liquid may be selected so that the removal rate of the dielectric layer and the interface layer is greater than the removal rate of copper, thereby achieving more removal of the dielectric layer and the interface layer.

[0068] Optionally, the first polishing pad, the second polishing pad and the third polishing pad can all be hard polishing pads, wherein the third polishing pad has the smallest hardness, the hardness of the first polishing pad and the second polishing pad can be the same or different, and the hardness of the first polishing pad and the second polishing pad is not less than the hardness of the third polishing pad.

[0069] The wafer after surface flattening obtained by the method provided in the above embodiment can reduce Cu dishing to the range of 1nm-5nm, and the surface roughness is less than 1nm. However, Cu dishing in large-size and high-density copper wire pattern areas may still be large. On this basis, the present invention further improves the method provided in the above embodiment and provides another hybrid bonding surface flattening process method for wafers to improve the effect of wafer surface flattening.

[0070] Figure 5 The implementation flow chart of the hybrid bonding surface planarization process method for wafers provided in the embodiment of the present invention is described in detail as follows:

[0071] Step S501, controlling the grinding head to absorb the first wafer to be planarized, and grinding the first wafer on the first grinding pad to remove the copper film above the groove of the first wafer, to obtain a second wafer.

[0072] In this embodiment, when the first round of grinding is performed on the first grinding pad, the copper film above the groove of the first wafer is directly removed completely, and the generated Cu dishing is repaired by the next two rounds of grinding to further reduce the surface height difference of the wafer.

[0073] See also Figure 6 The schematic flow chart of another hybrid bonding surface planarization process method for wafers shows that after the first round of grinding, a larger copper depression is generated on the surface of the second wafer.

[0074] Optionally, the first polishing pad may be a hard polishing pad to quickly remove the copper film.

[0075] Optionally, the grinding pressure for grinding the first wafer on the first grinding pad may be in the range of 1.2 psi to 2.5 psi. The copper film may be removed quickly through the combination of the hard grinding pad and the grinding pressure.

[0076] Step S502, control the grinding head to move to the second grinding pad, and grind the second wafer on the second grinding pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the groove with the same thickness as the dielectric layer, to obtain a third wafer with the interface layer exposed.

[0077] In this embodiment, the second round of grinding is performed on the second wafer on the second grinding pad, and only the dielectric layer, the barrier layer above the dielectric layer, and the copper in the groove with the same thickness as the dielectric layer are completely removed, and the interface layer is not ground temporarily. Through the second round of grinding, more dielectric layer and barrier layer can be removed, and less copper can be removed, thereby achieving the repair of Cu dishing.

[0078] Here, grinding can be performed in a fixed grinding time manner. The amount of film removal caused by this method is controllable within a certain range, and the barrier layer, the dielectric layer and a very small amount of the interface layer can be removed.

[0079] In the second round of grinding, the repair effect of Cu dishing will be different for different copper wire pattern sizes and pattern density areas. For wider and denser areas, since the copper dishing formed by the first round of grinding is deeper, after the second round of grinding, the dishing may still exist and can be further repaired in the third round of grinding. For smaller and less dense areas, since the copper dishing formed by the first round of grinding is relatively shallow, after the second round of grinding, the dishing may completely disappear or even turn from concave to convex and become a protrusion layer.

[0080] See also Figure 6 The schematic diagram of the process flow of another hybrid bonding surface planarization process method for wafers shows that after the second round of grinding, the surface height difference of the wafer after surface planarization is significantly reduced.

[0081] Optionally, the second polishing pad may be a hard polishing pad so as to quickly remove the dielectric layer and the barrier layer.

[0082] Here, the hardness of the second polishing pad may be the same as the hardness of the first polishing pad.

[0083] Optionally, the grinding pressure for grinding the second wafer on the second grinding pad may be in the range of 1.3 psi to 2.0 psi. The dielectric layer, the barrier layer and the copper may be removed quickly through the coordination of the hard grinding pad, the grinding liquid and the grinding pressure.

[0084] Step S503, control the grinding head to move to the third grinding pad, and grind the third wafer on the third grinding pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, to obtain a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than the hardness of the first grinding pad and the hardness of the second grinding pad.

[0085] In this embodiment, the third wafer is ground for the third time on the third grinding pad to remove part of the interface layer and part of the copper in the groove so that the surface of the interface layer is at the same height as the surface of the copper, further repairing the Cu dishing, flattening the wafer surface, and reducing the height difference and roughness of the wafer surface.

[0086] Here, a fixed grinding time is used for grinding. Since the amount removed by the third round of grinding is small, a shorter fixed grinding time can be used to achieve the repair of Cu dishing.

[0087] See also Figure 6The flowchart of another wafer hybrid bonding surface planarization process method is shown. After the third round of grinding, the surface height difference of the wafer after surface planarization is further reduced, which can fully meet the requirements of wafer-level hybrid bonding.

[0088] Optionally, the third polishing pad may be a soft polishing pad so as to remove the interface layer, reduce the surface height difference, and reduce the surface roughness.

[0089] Optionally, the grinding pressure for grinding the third wafer on the third grinding pad may be in the range of 1.2 psi to 1.6 psi. The combination of the soft grinding pad, the grinding liquid and the grinding pressure may quickly remove the interface layer and copper and reduce the surface roughness.

[0090] The embodiment of the present invention grinds the wafer surface three times, and the surface height difference can be repaired to maintain it within a stable range, thereby reducing the impact on hybrid bonding. The copper film above the groove can be removed by the first grinding, and a larger copper depression will be formed at this time; the dielectric layer, the barrier layer, and the copper in the groove with the same thickness as the dielectric layer are removed by the second grinding, and the amount of copper removed during the grinding process can be reduced, and the copper depression can be repaired, so that the height difference between the surface of the exposed interface layer and the surface of the copper in the groove is reduced; and the third grinding is performed to remove part of the interface layer and part of the copper in the groove, and the amount of copper removed during the grinding process can also be reduced, and the copper depression can be further repaired, so that the surface height of the interface layer is the same as the surface height of the copper in the groove, and the surface height difference of the wafer is reduced, thereby obtaining a flat and smooth surface.

[0091] In some embodiments, the grinding head is controlled to adsorb the first wafer to be surface-planarized, and the first wafer is ground on the first grinding pad to remove the copper film above the grooves of the first wafer to obtain the second wafer. The grinding head can be controlled to adsorb the first wafer to be surface-planarized first; then the first grinding liquid is pre-flowed on the first grinding pad; wherein the first grinding liquid is a grinding liquid for removing the copper film; then, the surface of the first wafer is ground for the first time on the first grinding pad, and the thickness of the copper film on the surface of the first wafer is monitored; again, when the thickness of the copper film reaches the first preset thickness, the surface of the first wafer is ground for the second time, and the thickness of the copper film is monitored; finally, when the thickness of the copper film reaches the second preset thickness, the surface of the first wafer is ground for the third time to remove the copper film above the grooves to obtain the second wafer; wherein the second preset thickness is less than the first preset thickness.

[0092] In this embodiment, the first round of grinding can be divided into three grinding steps to gradually remove the copper film.

[0093] In the first grinding, part of the copper film is removed first, and in the second grinding, part of the copper film is removed again. Through two grindings, most of the copper film can be removed, and the thickness of the remaining copper film at each position on the wafer is ensured to be the same, so as to avoid increasing the final copper depression.

[0094] Here, algorithms can be used to monitor the grinding process during the first grinding and the second grinding, and eddy current sensors can be used to detect the thickness of the copper film on the wafer surface. According to the detected thickness, the pressure in the corresponding zone of the grinding head can be adjusted in real time to achieve relatively consistent thickness changes of the copper film in different zones of the grinding head, until the thickness reaches the set target value.

[0095] In the third grinding, the remaining small portion of the copper film is removed to remove all the copper film above the trench.

[0096] Here, the laser sensor can be used to assist in the third grinding. The curve data obtained by optimizing the signal of the laser sensor and the algorithm-assisted judgment can be used to stop when all the copper film is removed.

[0097] Since the first round of grinding is mainly for removing the copper film, the grinding fluid used has a high removal rate for the copper film, but a very low removal rate for the barrier layer. Therefore, when the first round of grinding is completed, a large depression will be formed in the copper film in the groove, namely, Cu dishing.

[0098] Optionally, the first grinding can remove 45% to 55% of the copper film, and the second grinding can remove 35% to 40% of the copper film. Here, if the first grinding removes 45% of the copper film, the second grinding can remove 40% of the copper film; if the first grinding removes 55% of the copper film, the second grinding can remove 35% of the copper film, so that 10% to 15% of the copper film remains after the two grindings are completed.

[0099] In the third grinding, the remaining 10% to 15% of the copper film can be removed.

[0100] Optionally, the removal rate of the copper film in the third grinding is lower than that in the first grinding, and the removal rate of the copper film in the third grinding is lower than that in the second grinding.

[0101] In this embodiment, since the copper film remaining in the third grinding is less, and in order to reduce the Cudishing generated, a lower removal rate can be used in the third grinding. Here, the difference in removal rate can be achieved by adjusting the grinding pressure and the flow rate of the grinding liquid.

[0102] Optionally, the grinding pressure of the first grinding and the second grinding may range from 1.7 psi to 2.5 psi, and the grinding pressure of the third grinding may range from 1.2 psi to 1.7 psi.

[0103] The flow rate of the grinding liquid in the first grinding can range from 250mL / min to 300mL / min, the flow rate of the grinding liquid in the second grinding can range from 250mL / min to 300mL / min, and the flow rate of the grinding liquid in the third grinding can range from 200mL / min to 250mL / min.

[0104] Here, the range of the removal rate of the copper film during the first grinding and the second grinding can be The range of the removal rate of the copper film during the third grinding can be

[0105] In some embodiments, before controlling the grinding head to move to the second grinding pad and grinding the second wafer on the second grinding pad, the second grinding liquid can be determined based on a preset dielectric layer removal rate and a first selection ratio of copper removal rate; and the second grinding liquid can be pre-flowed on the second grinding pad.

[0106] Correspondingly, before controlling the grinding head to move to the third grinding pad and grinding the third wafer on the third grinding pad, the third grinding liquid can be determined according to the second selection ratio of the preset interface layer removal rate and the copper removal rate; and the third grinding liquid can be pre-flowed on the third grinding pad.

[0107] In this embodiment, before grinding the wafer, grinding liquid may be pre-flowed on the corresponding grinding pad to facilitate subsequent grinding.

[0108] Here, considering that the second round of grinding is mainly to remove the dielectric layer and copper and repair the copper depression in the groove, the grinding liquid can be selected according to the removal rate of the dielectric layer and copper. Correspondingly, considering that the third round of grinding is mainly to remove the interface layer and copper and further repair the copper depression in the groove, the grinding liquid can be selected according to the removal rate of the interface layer and copper.

[0109] Optionally, in this embodiment, the first selection ratio of the removal rate of the dielectric layer and the removal rate of copper may be in the range of 2.6 to 3.2, so that the polishing liquid can remove more dielectric layer and less copper, thereby achieving the repair of Cu dishing.

[0110] Here, the polishing liquid has a high removal rate for both the barrier layer and the dielectric layer. For example, the range of the removal rate can be In addition, the copper removal rate can range from

[0111] In addition, in the second round of grinding, the interface layer will also be touched, and the removal of the interface layer needs to be reduced. Therefore, a grinding liquid with a selectivity ratio between the removal rate of the dielectric layer and the removal rate of the interface layer of 2.2 to 2.6 can be selected. Correspondingly, the range of the removal rate of the interface layer can be

[0112] In this embodiment, the second selectivity ratio of the interface layer removal rate to the copper removal rate can be in the range of 2.0 to 2.5, which can make the polishing liquid remove more interface layer and less copper, thereby further repairing Cu dishing. The removal rate of the interfacial layer can range from

[0113] Here, a small amount of dielectric layer may remain on the wafer in the third round of grinding, and this part of the dielectric layer also needs to be removed. Therefore, when selecting the grinding liquid, the selection ratio between the removal rate of the dielectric layer and the removal rate of the interface layer can be 1.2 to 1.5. Among them, the removal rate of the dielectric layer can be

[0114] Optionally, in this embodiment, the flow rate of the second polishing liquid ranges from 200 mL / min to 300 mL / min, and the flow rate of the third polishing liquid ranges from 200 mL / min to 300 mL / min.

[0115] In some possible embodiments, see Figure 7 The schematic diagram of the structure of the wafer after wafer-level hybrid bonding is shown. Figure 7 The figure shows the situation after hybrid bonding of wafers obtained by the two methods provided by the present invention. Among them, after hybrid bonding, the wafer obtained by one repair (obtained by the hybrid bonding surface flattening process method of the first wafer provided by the embodiment of the present invention) is still less likely to produce bubble-type defects; after hybrid bonding, the wafer obtained by two repairs (obtained by the hybrid bonding surface flattening process method of the second wafer provided by the embodiment of the present invention) is basically free of bubble-type defects.

[0116] In other feasible embodiments, the second wafer hybrid bonding surface planarization process method provided in the embodiment of the present invention is used to grind wafers with copper pattern sizes of 0.9um×0.9um, 1.1um×1.1um and 1.3um×1.3um, and the data of copper depressions on the wafer surface after surface planarization are shown in Table 1:

[0117] Table 1 Data table of copper depressions on wafer surfaces of different sizes

[0118]

[0119] It can be seen from Table 1 that by grinding the wafer using the second wafer hybrid bonding surface planarization process method provided by the embodiment of the present invention, the copper depression on the wafer surface after the surface planarization can be kept within 1 nm.

[0120] Table 2 Data table of surface roughness of wafers of different sizes

[0121]

[0122] It can be seen from Table 2 that by grinding the wafer using the second wafer hybrid bonding surface planarization process method provided by the embodiment of the present invention, the surface roughness of the wafer after surface planarization can be maintained within 0.5 nm.

[0123] The embodiment of the present invention grinds the wafer surface three times, and the surface height difference can be repaired to maintain it within a stable range, thereby reducing the impact on hybrid bonding. The copper film above the groove can be removed by the first grinding, and a larger copper depression will be formed at this time; the dielectric layer, the barrier layer, and the copper in the groove with the same thickness as the dielectric layer are removed by the second grinding, and the amount of copper removed during the grinding process can be reduced, and the copper depression can be repaired, so that the height difference between the surface of the exposed interface layer and the surface of the copper in the groove is reduced; and the third grinding is performed to remove part of the interface layer and part of the copper in the groove, and the amount of copper removed during the grinding process can also be reduced, and the copper depression can be further repaired, so that the surface height of the interface layer is the same as the surface height of the copper in the groove, and the surface height difference of the wafer is reduced, thereby obtaining a flat and smooth surface.

[0124] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0125] The following is an embodiment of the device of the present invention. For details not described in detail therein, reference may be made to the corresponding method embodiment described above.

[0126] Figure 8 The structure diagram of the hybrid bonding surface planarization process device for wafers provided by an embodiment of the present invention is shown. For the convenience of explanation, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0127] The wafer hybrid bonding surface planarization process device 80 includes:

[0128] A first control module 81 is used to control the grinding head to absorb the first wafer to be surface flattened, and grind the first wafer on the first grinding pad to remove the copper film above the groove of the first wafer to obtain a second wafer;

[0129] A second control module 82 is used to control the grinding head to move to the second grinding pad, and grind the second wafer on the second grinding pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the groove with the same thickness as the dielectric layer, to obtain a third wafer with an exposed interface layer;

[0130] The third control module 83 is used to control the grinding head to move to the third grinding pad, and grind the third wafer on the third grinding pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than the hardness of the first grinding pad and the hardness of the second grinding pad.

[0131] In a possible implementation, the second control module 82 is specifically configured to:

[0132] Controlling the grinding head to absorb the first wafer to be processed for surface flattening;

[0133] Pre-flowing a first polishing liquid on a first polishing pad; wherein the first polishing liquid is a polishing liquid for removing a copper thin film;

[0134] Grinding the surface of the first wafer for the first time on the first grinding pad, and monitoring the thickness of the copper film on the surface of the first wafer;

[0135] When the thickness of the copper film reaches the first preset thickness, grinding the surface of the first wafer for the second time and monitoring the thickness of the copper film;

[0136] When the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the groove to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

[0137] In a possible implementation, the second control module 82 is further configured to:

[0138] Determining a second polishing liquid according to a first selection ratio of a preset removal rate of the dielectric layer and a removal rate of copper;

[0139] pre-flowing a second polishing liquid on the second polishing pad;

[0140] The third control module 83 is also used for:

[0141] Determining a third polishing liquid according to a preset interface layer removal rate and a second selection ratio of copper removal rate;

[0142] Pre-flow the third polishing liquid on the third polishing pad.

[0143] In a possible implementation, the removal rate of the copper film in the third grinding is lower than that in the first grinding, and the removal rate of the copper film in the third grinding is lower than that in the second grinding.

[0144] In a possible implementation, the first polishing pad and the second polishing pad are hard polishing pads, and the hardness of the first polishing pad is the same as the hardness of the second polishing pad;

[0145] The third polishing pad is a soft polishing pad.

[0146] In a possible implementation, the first selection ratio ranges from 2.6 to 3.2;

[0147] The second selection ratio ranges from 2.0 to 2.5.

[0148] In a possible implementation, the flow rates of the second polishing liquid and the third polishing liquid range from 200 mL / min to 300 mL / min.

[0149] In a possible implementation, the grinding pressure for grinding the first wafer on the first grinding pad ranges from 1.2 psi to 2.5 psi;

[0150] The grinding pressure of grinding the second wafer on the second grinding pad ranges from 1.3 psi to 2.0 psi;

[0151] The polishing pressure of polishing the third wafer on the third polishing pad ranges from 1.2 psi to 1.6 psi.

[0152] In a possible implementation, the first control module 81 is further used to control the grinding head to adsorb the first wafer to be surface flattened, and grind the first wafer on the first grinding pad to remove the copper film of a preset thickness above the groove of the first wafer to obtain a fourth wafer;

[0153] The second control module 82 is also used to control the grinding head to move to the second grinding pad, and grind the fourth wafer on the second grinding pad to remove the remaining thickness of the copper film above the groove of the fourth wafer to obtain a fifth wafer;

[0154] The third control module 83 is also used to control the grinding head to move to the third grinding pad, and grind the fifth wafer on the third grinding pad so that the interface layer of the fifth wafer is exposed, and the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface.

[0155] Fig. 9Schematic diagram of the chemical mechanical polishing equipment provided by the embodiment of the present invention. Fig. 9 As shown, the chemical mechanical polishing device 90 of this embodiment includes: a processor 91, a memory 92, and a computer program 93 stored in the memory 92 and executable on the processor 91. The chemical mechanical polishing device 90 also includes: a polishing head 94, a first polishing pad 95, a second polishing pad 96, and a third polishing pad 97. When the processor 91 executes the computer program 93, the steps in the above-mentioned hybrid bonding surface planarization process method of each wafer are implemented, such as Figure 3 Steps S301 to S303 shown, or, Figure 5 Alternatively, when the processor 91 executes the computer program 93, the functions of each module in the above-mentioned device embodiments are realized, for example, Figure 8 The functions of modules 81 to 83 are shown.

[0156] Exemplarily, the computer program 93 may be divided into one or more modules / units, one or more modules / units are stored in the memory 92 and executed by the processor 91 to implement the present invention. One or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program 93 in the chemical mechanical polishing device 90. For example, the computer program 93 may be divided into Figure 8 Modules 81 to 83 are shown.

[0157] The chemical mechanical polishing device 90 may include, but is not limited to, a processor 91 and a memory 92. Those skilled in the art will appreciate that Fig. 9 It is only an example of the chemical mechanical polishing device 90 and does not constitute a limitation of the chemical mechanical polishing device 90. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the chemical mechanical polishing device may also include input and output devices, network access devices, buses, etc.

[0158] The processor 91 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0159] The memory 92 may be an internal storage unit of the chemical mechanical polishing device 90, such as a hard disk or memory of the chemical mechanical polishing device 90. The memory 92 may also be an external storage device of the chemical mechanical polishing device 90, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the chemical mechanical polishing device 90. Further, the memory 92 may also include both an internal storage unit of the chemical mechanical polishing device 90 and an external storage device. The memory 92 is used to store computer programs and other programs and data required by the chemical mechanical polishing device. The memory 92 may also be used to temporarily store data that has been output or is to be output.

[0160] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0161] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0162] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0163] In the embodiments provided by the present invention, it should be understood that the disclosed device / chemical mechanical polishing equipment and method can be implemented in other ways. For example, the device / chemical mechanical polishing equipment embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0164] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0165] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0166] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable media can include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0167] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A wafer hybrid bonding surface planarization process method, characterized in that: include: Controlling the grinding head to absorb the first wafer to be surface-planarized, and grinding the first wafer on a first grinding pad to remove the copper film above the groove of the first wafer, thereby obtaining a second wafer; Controlling the grinding head to move to a second grinding pad, and grinding the second wafer on the second grinding pad to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer, and the copper in the groove with the same thickness as the dielectric layer, to obtain a third wafer with an exposed interface layer; The grinding head is controlled to move to a third grinding pad, and the third wafer is ground on the third grinding pad so that the surface height of the interface layer is the same as the surface height of the copper in the groove, thereby obtaining a wafer with a flattened surface; wherein the hardness of the third grinding pad is less than the hardness of the first grinding pad and the hardness of the second grinding pad.

2. The hybrid bonding surface planarization process method for wafers according to claim 1, characterized in that: The method comprises: controlling a grinding head to absorb a first wafer to be planarized, and grinding the first wafer on a first grinding pad to remove a copper film above a groove of the first wafer to obtain a second wafer, comprising: Controlling the grinding head to absorb the first wafer to be processed for surface flattening; Pre-flowing a first polishing liquid on the first polishing pad; wherein the first polishing liquid is a polishing liquid for removing a copper thin film; Grinding the surface of the first wafer for the first time on a first grinding pad, and monitoring the thickness of the copper film on the surface of the first wafer; When the thickness of the copper film reaches a first preset thickness, grinding the surface of the first wafer for a second time, and monitoring the thickness of the copper film; When the thickness of the copper film reaches a second preset thickness, the surface of the first wafer is ground for a third time to remove the copper film above the groove to obtain a second wafer; wherein the second preset thickness is less than the first preset thickness.

3. The hybrid bonding surface planarization process method of wafer according to claim 1, characterized in that: Before controlling the grinding head to move to the second grinding pad and grinding the second wafer on the second grinding pad, the method further includes: Determining a second polishing liquid according to a preset first selection ratio of the removal rate of the dielectric layer and the removal rate of copper; pre-flowing the second polishing liquid on the second polishing pad; Before controlling the grinding head to move to the third grinding pad and grinding the third wafer on the third grinding pad, the method further includes: Determining a third polishing liquid according to a preset second selection ratio of the interface layer removal rate and the copper removal rate; The third polishing liquid is pre-flowed on the third polishing pad.

4. The hybrid bonding surface planarization process method of wafer according to claim 2, characterized in that: The removal rate of the copper film in the third grinding is lower than that in the first grinding, and the removal rate of the copper film in the third grinding is lower than that in the second grinding.

5. The hybrid bonding surface planarization process method of wafer according to claim 1, characterized in that: The first polishing pad and the second polishing pad are hard polishing pads, and the hardness of the first polishing pad is the same as the hardness of the second polishing pad; The third polishing pad is a soft polishing pad.

6. The hybrid bonding surface planarization process method for wafers according to claim 3, characterized in that: The first selection ratio ranges from 2.6 to 3.2; The second selection ratio ranges from 2.0 to 2.

5.

7. The hybrid bonding surface planarization process method for wafers according to claim 3, characterized in that: The flow rates of the second polishing liquid and the third polishing liquid range from 200 mL / min to 300 mL / min.

8. The hybrid bonding surface planarization process method for a wafer according to any one of claims 1 to 7, characterized in that: The grinding pressure of grinding the first wafer on the first grinding pad ranges from 1.2 psi to 2.5 psi; The grinding pressure of grinding the second wafer on the second grinding pad is in the range of 1.3 psi to 2.0 psi; The grinding pressure of grinding the third wafer on the third grinding pad ranges from 1.2 psi to 1.6 psi.

9. A wafer hybrid bonding surface planarization process method, characterized in that: include: Controlling the grinding head to absorb the first wafer to be surface-planarized, and grinding the first wafer on a first grinding pad to remove the copper film of a preset thickness above the groove of the first wafer, to obtain a fourth wafer; Controlling the grinding head to move to the second grinding pad, and grinding the fourth wafer on the second grinding pad to remove the remaining thickness of the copper film above the groove of the fourth wafer to obtain a fifth wafer; The grinding head is controlled to move onto the third grinding pad, and the fifth wafer is ground on the third grinding pad so that the interface layer of the fifth wafer is exposed, and the surface height of the interface layer is the same as the surface height of the copper in the groove, so as to obtain a wafer with a flattened surface.

10. A chemical mechanical polishing device, comprising a polishing head, a first polishing pad, a second polishing pad, a third polishing pad, a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

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