Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the steps that a substrate is provided, the substrate comprises a substrate body, a pad oxide layer, a first pad nitride layer and a plurality of groove isolation structures, the pad oxide layer covers the portion, between every two adjacent groove isolation structures, of the substrate body, the first pad nitride layer covers the surface of the pad oxide layer, and the groove isolation structures are at least partially exposed out of the substrate body; removing the first pad nitride layer; performing ion implantation on the substrate; carrying out thinning treatment on the pad oxide layer; forming a second pad nitride layer on the surfaces of the trench isolation structure and the pad oxide layer; etching the second pad nitride layer, the pad oxide layer and the substrate by taking the patterned photoresist as a mask so as to form an opening in the substrate; and performing thermal oxidation treatment on the substrate in the opening to form an oxide layer. By adopting the preparation method of the semiconductor structure, the speed of a semiconductor device can be increased, and the circuit performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Local Oxidation of Silicon (LOCOS) is a technology used to manufacture insulating layers in semiconductor processes. The traditional local oxidation technology of silicon is to first grow a layer of pad oxide on the substrate, and then deposit a layer of silicon nitride as an oxidation barrier. Through photolithography and etching processes, the required pattern is etched into silicon nitride, and an active area in the oxidation process is formed on the substrate. Then a thermal oxidation process is performed to form a local oxide layer, and finally the silicon nitride layer is removed. In the process of growing the field oxide layer using LOCOS, especially in the formation of the high-voltage gate oxide layer (HV gate oxide) of the transistor, oxygen diffuses laterally into the active area covered by silicon nitride, oxidizing part of the underlying silicon, thereby forming a bird's beak. The emergence of the bird's beak effect reduces the effective width of the device, thereby reducing the speed of the device and greatly limiting the performance of the circuit. Summary of the invention

[0003] In view of the above shortcomings of the prior art, the present invention provides a method for preparing a semiconductor structure to improve the bird's beak effect in the semiconductor structure and enhance device performance.

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a semiconductor structure, the preparation method comprising: providing a substrate, the substrate comprising a substrate, a pad oxide layer, a first pad nitride layer and a plurality of trench isolation structures, the pad oxide layer covering the substrate between two adjacent trench isolation structures, the first pad nitride layer covering the surface of the pad oxide layer, and the plurality of trench isolation structures being at least partially exposed from the substrate; removing the first pad nitride layer; performing ion implantation on the substrate; performing thinning treatment on the pad oxide layer; forming a second pad nitride layer on the surface of the trench isolation structure and the pad oxide layer; etching the second pad nitride layer, the pad oxide layer and the substrate using a patterned photoresist as a mask to form an opening on the substrate; and performing thermal oxidation treatment on the substrate in the opening to form an oxide layer.

[0005] In one embodiment of the present invention, the first pad nitride layer is removed by wet etching, and phosphoric acid is selected as an etching solution, and the concentration of phosphoric acid is 10%-15%.

[0006] In one embodiment of the present invention, a wet etching process is used to thin the pad oxide layer, and hydrofluoric acid is selected as an etching solution, and the concentration of the hydrofluoric acid is 5%-10%.

[0007] In one embodiment of the present invention, the thickness of the first pad nitride layer is 190Å~210Å, and the thickness of the second pad nitride layer is 190Å~210Å.

[0008] In one embodiment of the present invention, the thickness of the pad oxide layer before thinning is 107Å~127Å, and the thickness of the pad oxide layer after thinning is 42Å~52Å.

[0009] In one embodiment of the present invention, the depth of the opening is 370Å~410Å.

[0010] In one embodiment of the present invention, the temperature of the thermal oxidation treatment is 900° C. to 1100° C., and the time of the thermal oxidation treatment is 10 h to 15 h.

[0011] In one embodiment of the present invention, providing the base includes: providing the substrate; depositing the pad oxide layer on the substrate; depositing the first pad nitride layer on the surface of the pad oxide layer; and forming a plurality of the trench isolation structures on the substrate.

[0012] In one embodiment of the present invention, ion implantation into the substrate comprises: performing a first ion implantation into the substrate to form a well region on the substrate; performing a second ion implantation into the substrate to form doped regions on both sides of the well region, respectively, wherein the well region and the doped region are isolated by the trench isolation structure.

[0013] In one embodiment of the present invention, the second pad nitride layer, the pad oxide layer and the substrate are etched using a patterned photoresist as a mask to form an opening on the substrate, and the process also includes etching the trench isolation structure on both sides of the opening.

[0014] In summary, the present invention provides a method for preparing a semiconductor structure, wherein a trench isolation structure is formed on a substrate, and after removing the first pad nitride layer, ion implantation can be performed on the substrate with a thicker pad oxide layer as a buffer layer, thereby forming a well region and a doped region on the substrate, and then the pad oxide layer is thinned and a second pad nitride layer is formed on its surface as a barrier for subsequent oxidation. The unexpected effect is that when the well region is subsequently locally oxidized, the lateral diffusion of oxygen into the doped region under the pad oxide layer is reduced, and the oxidation of the doped region by oxygen is reduced, thereby reducing the bird's beak length of the doped region, increasing the speed of the device, and improving the performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 It is a schematic diagram of forming a pad oxide layer and a first pad nitride layer on a substrate in one embodiment of the present invention; Figure 2 A schematic diagram of forming a first photoresist layer in one embodiment of the present invention; Figure 3 is a schematic diagram of forming a groove in one embodiment of the present invention; Figure 4 A schematic diagram of forming a trench isolation structure in one embodiment of the present invention; Figure 5 A schematic diagram of removing the first pad nitride layer in one embodiment of the present invention; Figure 6 A schematic diagram of forming a well region in one embodiment of the present invention; Figure 7 A schematic diagram of forming a doped region in one embodiment of the present invention; Figure 8 A schematic diagram of thinning the pad oxide layer in one embodiment of the present invention; Fig. 9 A schematic diagram of forming a second pad nitride layer in one embodiment of the present invention; Fig.10 A schematic diagram of forming a second photoresist layer in one embodiment of the present invention; Fig.11 A schematic diagram of forming an opening in one embodiment of the present invention; Fig.12 A schematic diagram of forming an oxide layer in one embodiment of the present invention; Fig.13 A schematic diagram of removing a pad oxide layer and a second pad nitride layer according to an embodiment of the present invention; Fig.14 A microscopic schematic diagram of a bird's beak of a semiconductor structure according to an embodiment of the present invention; Fig.15 It is a microscopic schematic diagram of the bird's beak of the semiconductor structure in the comparative example of the present invention.

[0017] Component number description: 10. Base; 100. Substrate; 110. Well region; 120. Doped region; 130. Opening; 140. Oxide layer; 200. Pad oxide layer; 300. First pad nitride layer; 400. Trench isolation structure; 410. Trench; 420. First trench isolation structure; 430. Second trench isolation structure; 440. Third trench isolation structure; 450. Fourth trench isolation structure; 500. First photoresist layer; 510. Trench region; 600. Second pad nitride layer; 700. Second photoresist layer; 710. Opening region. DETAILED DESCRIPTION

[0018] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0019] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0020] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0021] In this article, when it comes to numerical ranges, unless otherwise specified, the distribution of optional values ​​within the numerical range is considered continuous and includes the two numerical endpoints (i.e., the minimum value and the maximum value) of the numerical range, as well as every value between the two numerical endpoints. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be combined.

[0022] See also Figure 4As shown, in one embodiment of the present invention, when preparing a semiconductor structure, a substrate 10 is first provided. In this embodiment, the substrate 10 includes a substrate 100, a pad oxide layer 200, a first pad nitride layer 300 and a plurality of trench isolation structures 400, wherein the pad oxide layer 200 covers the substrate 100 between two adjacent trench isolation structures 400, the first pad nitride layer 300 covers the surface of the pad oxide layer 200, and the plurality of trench isolation structures 400 are at least partially exposed from the substrate 100. The substrate 100 may be any material suitable for forming a semiconductor structure, such as undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). The present invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate, and the doping type of impurities can be flexibly set according to the semiconductor structure to be formed. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0023] The base 10 may be a semi-finished product purchased from outside, or may be prepared by oneself. In one embodiment, the base 10 is prepared by oneself on the substrate 100. Figure 1 As shown, in one embodiment of the present invention, the preparation process of the base 10 includes: forming a pad oxide layer 200 on the substrate 100, and the pad oxide layer 200 can not only serve as a protective layer of the substrate 100, but also protect the substrate 100 covered by it in the subsequent process to prevent the substrate 100 from being damaged unnecessarily. The material of the pad oxide layer 200 can be silicon dioxide or other materials, and the pad oxide layer 200 can be formed by any one of the methods such as dry oxygen oxidation, wet oxygen oxidation or in-situ steam growth (ISSG). In this embodiment, for example, the pad oxide layer 200 is formed by dry oxygen oxidation. For example, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with the oxygen at high temperature to generate a dense pad oxide layer 200, and the quality of the generated pad oxide layer 200 is good. In this embodiment, the thickness of the pad oxide layer 200 is 107Å~127Å, for example, it can be any value between 107Å~127Å, such as 107Å, 110Å, 115Å, 120Å or 127Å.

[0024] See also Figure 1As shown, in one embodiment of the present invention, the preparation process of the substrate 10 further includes: after forming the pad oxide layer 200, forming a first pad nitride layer 300 on the pad oxide layer 200. The material of the first pad nitride layer 300 can be silicon nitride, nitride oxide, and in this embodiment, the first pad nitride layer 300 is, for example, silicon nitride. The first pad nitride layer 300 can be prepared by any process of low pressure chemical vapor deposition, normal pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or high density plasma chemical vapor deposition. The thickness of the first pad nitride layer 300 is, for example, 190Å~210Å, and specifically, for example, it can be any value in the range of 190Å~210Å, such as 190Å, 195Å, 200Å, 205Å or 210Å. By setting the first pad nitride layer 300, the substrate 100 can be protected from the influence of planarization processes such as chemical mechanical polishing (CMP) involved in the manufacturing process of the trench isolation structure 400. The first pad nitride layer 300 may also be used as a mask in the subsequent formation process of the trench isolation structure 400 to protect the substrate 100 from being damaged when etching the substrate 100 .

[0025] See also Figure 2 and Figure 3As shown, in one embodiment of the present invention, the preparation process of the substrate 10 also includes: after forming the first pad nitride layer 300, coating a photoresist on the first pad nitride layer 300 to form a first photoresist layer 500, the photoresist material type is not limited, it can be a common positive photoresist material or a negative photoresist material, and after coating the photoresist, the coated photoresist is patterned by photolithography processes such as mask exposure and development to expose the groove area 510. With the patterned photoresist layer as the mask layer, the first pad nitride layer 300, the pad oxide layer 200 and the substrate 100 are etched in sequence to form grooves 410. The number, position, depth, width and other parameters of the grooves 410 are set according to actual needs and are not limited here. Exemplarily, in this embodiment, the grooves 410 are shallow grooves, and in other embodiments, the grooves 410 can also be deep grooves. In this embodiment, the grooves 410 extend from the first pad nitride layer 300 to the substrate 100. The shape of the groove 410 is an inverted trapezoidal cross section that is wide at the top and narrow at the bottom, that is, the width of the top of the groove 410 is greater than the width of the bottom of the groove 410. Of course, in some embodiments, the shape of the groove 410 can also be rectangular. In this embodiment, the first pad nitride layer 300, the pad oxide layer 200 and part of the substrate 100 can be removed in sequence by dry etching to form the groove 410, and the etching gas, for example, includes chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), etc., or a combination of them and oxygen (O2). After the etching is completed, the first photoresist layer 500 is removed by wet cleaning or ashing.

[0026] See also Figure 4 As shown, in one embodiment of the present invention, the preparation process of the substrate 10 further includes: after forming the groove 410, depositing an insulating medium in the groove 410 until the insulating medium covers the surface of the first pad nitride layer 300. Before depositing the isolation medium, the groove 410 may be subjected to thermal oxidation treatment to round the corners of the bottom of the groove 410 to reduce the tip leakage phenomenon. The present invention does not limit the deposition method of the insulating medium, for example, a high-quality insulating medium may be formed by high-density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio ProcessCVD, HARP-CVD) and the like. After depositing the insulating medium, a high-temperature tempering process may be performed to increase the density and stress of the insulating medium. In this embodiment, the insulating medium is, for example, silicon oxide. In other embodiments, the insulating medium may also be other insulating materials suitable for isolation.

[0027] See also Figure 4As shown, in one embodiment of the present invention, the preparation process of the substrate 10 further includes: after preparing the insulating medium, the insulating medium is planarized to obtain the substrate 10. The planarization process, for example, utilizes chemical mechanical polishing to planarize the insulating medium, and the trench isolation structure 400 is at least partially exposed to the substrate 100. For example, a portion of the insulating medium is removed by grinding and the first pad nitride layer 300 is used as a grinding stop layer to obtain the trench isolation structure 400. The present invention does not limit the planarization of the insulating medium to a specific position, and it can be set at any position according to the design requirements of the semiconductor device, for example, the insulating medium in a portion of the shallow trench is planarized to be flush with the first pad nitride layer 300 on both sides. The present invention does not limit the number of trench isolation structures 400, and it is adjusted according to the requirements of the required semiconductor. The sizes of multiple trench isolation structures 400 may be equal or unequal. In the present embodiment, the substrate 10 includes four trench isolation structures 400 , which are respectively denoted as a first trench isolation structure 420 , a second trench isolation structure 430 , a third trench isolation structure 440 and a fourth trench isolation structure 450 . Exemplarily, the four trench isolation structures 400 have the same size.

[0028] See also Figure 5 As shown, in one embodiment of the present invention, the method for preparing the semiconductor structure of the present invention further includes: removing the first pad nitride layer 300 on the substrate 10. The present invention does not limit the method for removing the first pad nitride layer 300, such as removing by dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, wet etching is used to remove the first pad nitride layer 300. For example, phosphoric acid is used to remove the first pad nitride layer 300, and the concentration of phosphoric acid is 10% to 15%, such as 10%, 13% or 15%, and any value between 10% and 15%, and the etching time is 3min to 6min, such as any value between 3min, 4min, 5min or 6min.

[0029] See also Figure 6As shown, in one embodiment of the present invention, after removing the first pad nitride layer 300, the pad oxide layer 200 is used as an ion implantation buffer layer, and the substrate 100 is implanted with the first ion implantation, and a well region 110 is formed on the substrate 100, and the well region 110 is located between the second trench isolation structure 430 and the third trench isolation structure 440. In one embodiment of the present invention, the semiconductor structure is an N-type semiconductor structure, and the doping ions in the well region 110 are, for example, P-type doping ions, and for example, boron (B) or gallium (Ga). In another embodiment of the present invention, the semiconductor structure is, for example, a P-type semiconductor structure, and the doping ions in the well region 110 are N-type doping ions, and for example, phosphorus (P) or arsenic (As). After the first ion implantation, a rapid thermal annealing process (RTA) is performed on the well region 110, so that the ion implantation diffuses to a suitable depth. The present invention does not limit the ion implantation concentration and depth of the well region 110, for example, the ion implantation concentration and depth are set according to the specific semiconductor type.

[0030] See also Figure 7 As shown, in one embodiment of the present invention, the pad oxide layer 200 is used as an ion implantation buffer layer, and the substrate 100 is implanted with ions for the second time, and doping regions 120 are formed on both sides of the well region 110, that is, doping regions 120 are formed between the first trench isolation structure 420 and the second trench isolation structure 430 and between the third trench isolation structure 440 and the fourth trench isolation structure 450, respectively, and the well region 110 and the doping region 120 are isolated by the trench isolation structure 400. Among them, the type of ions implanted in the doping region 120 is opposite to the type of ions in the well region 110. When the semiconductor structure is an N-type semiconductor structure, the ions implanted in the doping region 120 are N-type impurities such as phosphorus (P) or arsenic (As), and when the semiconductor structure is a P-type semiconductor structure, the ions implanted in the doping region 120 are P-type impurities such as boron (B) or gallium (Ga). The present invention does not limit the ion implantation concentration and depth of the doping region 120, and the concentration and depth of the ion implantation are set according to the specific semiconductor structure type.

[0031] See also Figure 8As shown, in one embodiment, after the doping region 120 is formed in the substrate 100, the pad oxide layer 200 is thinned. The present invention does not limit the thinning method of the pad oxide layer 200, for example, dry etching, wet etching, or a combination of dry etching and wet etching are used to remove it. In this embodiment, wet etching is used to thin the pad oxide layer 200, and for example, wet etching is used to etch the pad oxide layer 200, and the wet etching etchant is, for example, hydrofluoric acid or buffered oxide etchant (BOE). Exemplarily, the pad oxide layer 200 is silicon oxide, and hydrofluoric acid is selected to thin the pad oxide layer 200, and the concentration of hydrofluoric acid is 5% to 10%, for example, 5%, 8% or 10%, and any value of 5 to 10%, and the etching time is 3min to 6min, for example, any value of 3min, 4min, 5min or 6min.

[0032] The thickness of the pad oxide layer 200 after thinning can be 42Å~52Å, for example, any value in the range of 42Å~52Å, such as 42Å, 45Å, 50Å or 52Å. Within this thickness range, the pad oxide layer 200 will not reduce the stress release effect, and can greatly increase the bonding force between the second pad nitride layer 600 formed subsequently and the substrate 100. The pad oxide layer 200 is thinned using a hydrofluoric acid solution, and the reaction of hydrofluoric acid and silicon oxide generates soluble H2SiF6, which is easily soluble in water to form a solution, which can well avoid the generation of particles.

[0033] See also Fig. 9 As shown, in one embodiment of the present invention, after the pad oxide layer 200 is thinned, a second pad nitride layer 600 is formed on the surface of a portion of the trench isolation structure 400 and the pad oxide layer 200. The thinning of the pad oxide layer 200 can increase the interlayer bonding force between the second pad nitride layer 600 and the substrate 100, thereby effectively reducing the lateral diffusion of oxygen. The material of the second pad nitride layer 600 can be silicon nitride, nitride oxide or metal nitride. The second pad nitride layer 600 can be prepared by any one of low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or high density plasma chemical vapor deposition. The thickness of the second pad nitride layer 600 is 190Å~210Å, and specifically can be any value of 190Å~210Å such as 190Å, 195Å, 200Å, 205Å or 210Å.

[0034] See also Fig.10 and Fig.11As shown, in one embodiment of the present invention, after forming the second pad nitride layer 600, a photoresist is coated on the second pad nitride layer 600 to form a second photoresist layer 700. The type of photoresist material is not limited, and it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the coated photoresist is patterned by photolithography processes such as mask exposure and development to expose the opening area 710. Then, the second pad nitride layer 600, part of the trench isolation structure 400, the pad oxide layer 200 and part of the substrate 100 are removed in sequence in the opening area 710 to form an opening 130 on the substrate 100. Further, when forming the opening 130 on the substrate 100, it also includes etching part of the second trench isolation structure 430 and part of the third trench isolation structure 440 to prevent the substrate 100 from being damaged during subsequent semiconductor processing. After forming the opening 130 on the substrate 100, the second photoresist layer 700 is removed by wet cleaning or ashing. In this embodiment, the depth of the opening 130 is 370Å-410Å, for example, it can be any value in the range of 370Å-410Å, such as 370Å, 390Å or 410Å.

[0035] See also Fig.12 As shown, in one embodiment of the present invention, after forming an opening 130 on the substrate 100, the substrate 100 in the opening 130 is subjected to thermal oxidation treatment to form an oxide layer 140. In this embodiment, taking a high-voltage device as an example, the pad oxide layer 200 is formed by, for example, dry oxygen oxidation. Exemplarily, the base 10 is placed in a furnace tube, oxygen is introduced, and the substrate 100 in the opening 130 reacts with oxygen at a high temperature to form an oxide layer 140. In this embodiment, the temperature of the thermal oxidation treatment is 900°C to 1100°C, for example, it can be any value in the range of 900°C to 1100°C, such as 900°C, 950°C, 1000°C, 1050°C or 1100°C. The time of the thermal oxidation treatment is 10h to 15h, for example, any value in the range of 10h to 15h, such as 10h, 12h, 14h or 15h. In other embodiments, wet oxygen oxidation can also be used to oxidize the substrate 100 at the opening 130 using H2 and O2 at a preset temperature.

[0036] See also Fig.13 As shown, in one embodiment of the present invention, after the oxide layer 140 is formed on the substrate 100 at the opening 130, the second pad nitride layer 600 is removed. The present invention does not limit the method for removing the second pad nitride layer 600 and the pad oxide layer 200, for example, they may be removed by dry etching, wet etching, or a combination of dry etching and wet etching. In the present embodiment, for example, the second pad nitride layer 600 is etched by an acid solution. After removing the second pad nitride layer 600, the pad oxide layer 200 is removed. In the present embodiment, for example, the pad oxide layer 200 is removed by wet etching, and the wet etching etchant is, for example, hydrofluoric acid or a buffered oxide etchant.

[0037] In one embodiment of the present invention, a semiconductor structure is prepared according to the above method. Taking the thinning of the pad oxide layer 200 to 47Å as an example, the prepared semiconductor structure has a bird's beak formed below the pad oxide layer 200 as shown in FIG. Fig.14 As a control, the other preparation conditions are kept the same, the pad oxide layer 200 is not thinned, and the thickness of the pad oxide layer 200 is kept at 107Å. The prepared semiconductor structure has a bird's beak formed under the pad oxide layer 200 as shown in FIG. Fig.15 It can be seen that the semiconductor structure prepared by the preparation method of the present application can greatly reduce the bird's beak length of the doped region when the substrate 100 is locally oxidized, which can effectively improve the performance of the semiconductor device.

[0038] In summary, the present invention provides a method for preparing a semiconductor structure, wherein a trench isolation structure is formed on a substrate, and after removing the first pad nitride layer, ion implantation can be performed on the substrate with a thicker pad oxide layer as a buffer layer, thereby forming a well region and a doped region on the substrate, and then the pad oxide layer is thinned and a second pad nitride layer is formed on its surface as a barrier for subsequent oxidation. The unexpected effect is that when the well region is subsequently locally oxidized, the lateral diffusion of oxygen into the doped region under the pad oxide layer is reduced, and the oxidation of the doped region by oxygen is reduced, thereby reducing the bird's beak length of the doped region, increasing the speed of the device, and improving the performance of the circuit.

[0039] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate, a pad oxide layer, a first pad nitride layer and a plurality of trench isolation structures, the pad oxide layer covers the substrate between two adjacent trench isolation structures, the first pad nitride layer covers the surface of the pad oxide layer, and the plurality of trench isolation structures are at least partially exposed from the substrate; removing the first pad nitride layer; Performing ion implantation on the substrate; Performing a thinning process on the pad oxide layer; forming a second pad nitride layer on the surface of the trench isolation structure and the pad oxide layer; Using the patterned photoresist as a mask, etching the second pad nitride layer, the pad oxide layer and the substrate to form an opening on the substrate; The substrate in the opening is subjected to thermal oxidation treatment to form an oxide layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first pad nitride layer is removed by wet etching, and phosphoric acid is selected as an etching solution, and the concentration of phosphoric acid is 10%-15%.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The pad oxide layer is thinned by a wet etching process, and hydrofluoric acid is used as an etching solution with a concentration of 5% to 10%.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the first pad nitride layer is 190Å~210Å, and the thickness of the second pad nitride layer is 190Å~210Å.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the pad oxide layer before thinning is 107Å~127Å, and the thickness of the pad oxide layer after thinning is 42Å~52Å.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The depth of the opening is 370Å~410Å.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The temperature of the thermal oxidation treatment is 900° C. to 1100° C., and the time of the thermal oxidation treatment is 10 h to 15 h.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The providing of a substrate comprises: providing the substrate; depositing the pad oxide layer on the substrate; Depositing the first pad nitride layer on the surface of the pad oxide layer; A plurality of the trench isolation structures are formed on the substrate.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: Performing ion implantation on the substrate includes: Performing a first ion implantation on the substrate to form a well region on the substrate; A second ion implantation is performed on the substrate to form doped regions on both sides of the well region, respectively. The well region and the doped regions are isolated from each other by the trench isolation structure.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that: Using the patterned photoresist as a mask, the second pad nitride layer, the pad oxide layer and the substrate are etched to form an opening on the substrate, and the process also includes etching the trench isolation structure on both sides of the opening.

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