Super-junction MOSFET device and preparation method thereof
By setting a wider polysilicon gate layer in the superjunction MOSFET device and forming an additional injection region, the problem of insufficient anti-interference ability and dynamic characteristics of existing devices is solved, and the source-drain breakdown voltage is improved and the anti-interference ability is achieved. enhancement.
Patent Information
- Application Number
- CN202411615627.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-02-18
AI Technical Summary
Existing superjunction MOSFET devices have shortcomings in their anti-interference capabilities and dynamic characteristics.
By setting a wider polysilicon gate layer in the superjunction MOSFET device and forming an additional injection region under it, the depletion under the gate polysilicon is improved, the source-drain breakdown voltage of the device is increased, and the Cgs capacitance is increased to Improve anti-interference ability.
The device's source-drain breakdown voltage is increased by about 20V, which enhances the anti-interference ability, and optimizes dynamic characteristics by adjusting the width of the polysilicon gate layer and the second injection region.
Smart Images
Figure CN119486191A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor power devices, and in particular to a super junction MOSFET device and a preparation method thereof. Background Art
[0002] Super junction MOSFET, also known as super junction metal oxide semiconductor field effect transistor (SJ-MOSFET), is a new type of power semiconductor device that is developing rapidly and widely used. It has been widely used in power supplies or adapters for consumer electronic products such as personal computers, laptops, netbooks, mobile phones, high-pressure gas discharge lamp products, LCD TVs, plasma TVs, and game consoles. However, the current super junction MOSFET devices still need to be improved in terms of anti-interference ability and dynamic characteristics. Summary of the invention
[0003] The present application provides a super junction MOSFET device and a preparation method, which can improve the anti-interference ability and dynamic characteristics of the super junction MOSFET device.
[0004] In order to achieve the above objectives, this application adopts the following technical solutions: The present application provides a super junction MOSFET device, the device comprising: A wafer substrate, a column structure located on the wafer substrate, a polysilicon gate layer located on the column structure, and a source region formed in the column structure, wherein the width of the polysilicon gate layer is: The column structure includes first columns of a first conductivity type and second columns of a second conductivity type, and the first columns and the second columns are arranged alternately; The polysilicon gate layer includes an inner first injection region and an outer second injection region, wherein the first injection region is a first conductivity type body region; The second injection region has a first conductivity type, is located in the column structure, and is connected to the first column.
[0005] As a possible implementation, the first column includes: an access column and a floating column, wherein the access column is a first column connected to the source region, and the floating column is a first column not connected to the source region; The second injection region is connected to the floating column and the access column respectively.
[0006] As a possible implementation manner, the pillar structure includes an oxide layer, the polysilicon gate layer is located on the oxide layer, and the first injection region and the second injection region are located under the oxide layer corresponding to the polysilicon gate layer.
[0007] As a possible implementation manner, the access pillar includes a heavily doped region of the first conductivity type, and the source region is formed in the heavily doped region.
[0008] As a possible implementation manner, the device further includes: a source metal, and the source region is connected to the source metal through a contact hole.
[0009] As a possible implementation manner, the device further includes a gate lead, and the polysilicon gate layer is connected to the gate lead.
[0010] As a possible implementation manner, an interlayer dielectric is included between the source metal and the second injection region.
[0011] As a possible implementation manner, an interlayer dielectric is included between the polysilicon gate layer and the gate lead.
[0012] As a possible implementation manner, the wafer substrate has a second conductivity type, and the wafer substrate has a first surface and a second surface opposite to each other; The device further includes a drain electrode formed on a first surface of the wafer substrate, and the pillar structure is disposed on a second surface of the wafer substrate.
[0013] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0014] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: The super junction MOSFET device provided in the embodiment of the present application comprises: a wafer substrate, a column structure located on the wafer substrate, a polysilicon gate layer located on the column structure, and a source region formed in the column structure, wherein the width of the polysilicon gate layer is: the column structure comprises a first column of a first conductivity type and a second column of a second conductivity type, and the first column and the second column are arranged alternately; the polysilicon gate layer comprises a first injection region of an inner circle and a second injection region of an outer circle, the first injection region is a body region of the first conductivity type; the second injection region has a first conductivity type, the second injection region is located in the column structure, and the second injection region is connected to the first column. The super junction MOSFET device provided in the embodiment of the present application forms a second injection region by setting a wider polysilicon gate layer and performing additional injection under the polysilicon gate layer, thereby improving the depletion condition under the gate polysilicon, improving the source-drain breakdown voltage of the device, and increasing the Cgs capacitance, so that Cgd / Ciss is smaller, and improving the anti-interference ability of the device. The additional second injection region surrounds the wafer and connects more second pillars of the terminal to the source, providing more paths for hole extraction at the terminal when the device body diode reverse recovers, thereby improving the reverse recovery of the device.
[0015] The source-drain breakdown voltage of the tested device is increased by about 20 V. Furthermore, by changing the width of the polysilicon gate layer and the width of the second injection region, a suitable Cgs capacitance can be selected to obtain a device with better dynamic characteristics. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A longitudinal cross-sectional view of a super junction MOSFET device provided in an embodiment of the present application at the position of the second injection region; Figure 2 A schematic diagram of an implantation region under a polysilicon gate layer of a super junction MOSFET device provided in an embodiment of the present application.
[0017] Reference numerals: 1-wafer substrate, 2-second column, 3-first column, 4-drain, 5-oxide layer, 6-polysilicon gate layer, 7-contact hole, 8-gate lead, 9-source metal, 10-source region, 11-second injection region. DETAILED DESCRIPTION
[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0019] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0020] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.
[0021] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0022] The present application embodiment provides a super junction MOSFET device, such as Figure 1 As shown, the device comprises: A wafer substrate 1, a column structure located on the wafer substrate 1, a polysilicon gate layer 6 located on the column structure, and a source region 10 formed in the column structure, wherein the width of the polysilicon gate layer 6 is: The crystalline silicon gate layer 6 in the present application is 1 to 3 cell widths wider than the crystalline silicon gate layer in the existing super junction MOSFET device.
[0023] The column structure includes first columns 3 of a first conductivity type and second columns 2 of a second conductivity type, wherein the first columns 3 and the second columns 2 are arranged alternately; The polysilicon gate layer 6 includes an inner first injection region and an outer second injection region 11, wherein the first injection region is a first conductivity type body region; The second injection region 11 has a first conductivity type, is located in the column structure, and is connected to the first column 3 .
[0024] in, Figure 1 It is a longitudinal cross-sectional view of the super junction MOSFET device at the second injection region 11. Figure 2Schematic diagram of the first injection region of the inner circle and the second injection region 11 of the outer circle under the polysilicon gate layer 6. Wherein, the ordinary super junction MOSFET device only includes the first injection region, and the present application sets a wider polysilicon gate layer 6, and performs additional injection under the outer edge of the polysilicon gate layer 6 to form the second injection region 11.
[0025] The super junction MOSFET device provided in the embodiment of the present application includes: a wafer substrate 1, a column structure located on the wafer substrate 1, a polysilicon gate layer 6 located on the column structure, and a source region 10 formed in the column structure, the width of the polysilicon gate layer 6 is: the column structure includes a first column 3 of a first conductivity type and a second column 2 of a second conductivity type, and the first column 3 and the second column 2 are arranged alternately; the polysilicon gate layer 6 includes an inner circle of a first injection region and an outer circle of a second injection region 11, the first injection region is a first conductivity type body region; the second injection region 11 has a first conductivity type, the second injection region 11 is located in the column structure, and the second injection region 11 is connected to the first column 3.
[0026] The super junction MOSFET device provided in the embodiment of the present application is provided with a wider polysilicon gate layer 6, and an additional injection is performed under the polysilicon gate layer 6 to form a second injection region 11, which can improve the depletion under the gate polysilicon, improve the source-drain breakdown voltage of the device, and increase the Cgs capacitance, so that Cgd / Ciss is smaller, which can improve the device's anti-interference ability. The additional second injection region 11 surrounds the wafer in a circle, and connects the second column 2 of the terminal to the source, providing more paths for the hole extraction of the terminal when the device body diode reverses, thereby improving the reverse recovery of the device.
[0027] The source-drain breakdown voltage of the tested device is increased by about 20 V. Furthermore, by changing the width of the polysilicon gate layer 6 and the width of the second implantation region 11 , a suitable Cgs capacitance can be selected to obtain a device with better dynamic characteristics.
[0028] Optionally, the first column 3 includes: an access column and a floating column, the access column is the first column 3 connected to the source region 10, and the floating column is the first column 3 not connected to the source region 10; the second injection region 11 is respectively connected to the floating column and the access column.
[0029] Optionally, the pillar structure includes an oxide layer 5 , the polysilicon gate layer 6 is located on the oxide layer 5 , and the first injection region and the second injection region 11 are located under the oxide layer 5 corresponding to the polysilicon gate layer 6 .
[0030] In addition, the access pillar includes a heavily doped region of the first conductivity type, and the source region 10 is formed in the heavily doped region.
[0031] The device further includes: a source metal 9 , and the source region 10 is connected to the source metal 9 through a contact hole 7 .
[0032] The device further comprises a gate lead 8 , and the polysilicon gate layer 6 is connected to the gate lead 8 .
[0033] An interlayer dielectric is provided between the source metal 9 and the second implantation region 11. An interlayer dielectric is provided between the polysilicon gate layer 6 and the gate lead 8.
[0034] Among them, the wafer substrate 1 has a second conductivity type, and the wafer substrate 1 has a first surface and a second surface relative to each other; the device also includes a drain 4, the drain 4 is formed on the first surface of the wafer substrate 1, and the column structure is arranged on the second surface of the wafer substrate 1.
[0035] Among them, the wafer substrate 1 has a first conductivity type, and the wafer substrate 1 has a first surface and a second surface relative to each other. The wafer substrate 1 serves as a carrier of the super junction MOSFET and mainly plays a supporting role. The material of the wafer substrate 1 can be a silicon substrate, a germanium substrate, or a germanium silicon substrate, etc. In this embodiment, the material of the wafer substrate 1 is preferably a silicon substrate, and silicon is the most common, cheap and stable semiconductor material.
[0036] The column structure is disposed on the second surface of the substrate, and includes first columns 3 having a first conductivity type and second columns 2 having a second conductivity type, wherein the first columns 3 and the second columns 2 are alternately arranged.
[0037] It is understandable that the material of the first column 3 may be silicon, and the material of the second column 2 may be SiC. The height of the first column 3 and the second column 2 is the same. Optionally, the doping concentration of the first column 3 and the second column 2 may be 1×10 14 ~8×10 15 cm -3 .
[0038] In addition, the minority carrier lifetime of the column of the super junction MOSFET can be 0.1μs to 100μs, for example, it can be 0.1μs, 0.5μs, 1μs, 5μs, 10μs, 20μs, 30μs, 40μs, 50μs, 60μs, 70μs, 80μs, 90μs or 100μs.
[0039] Among them, minority carriers are minority carriers, as opposed to majority carriers. There are two types of carriers in semiconductor materials: electrons and holes. If a certain type of carrier is in the minority in semiconductor materials and plays a minor role in conduction, it is called minority carrier. For example, in N-type semiconductors, holes are minority carriers and electrons are majority carriers; in P-type semiconductors, holes are majority carriers and electrons are minority carriers.
[0040] Optionally, the first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type.
[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
[0042] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.
Claims
1. A super junction MOSFET device, characterized in that: The device comprises: A wafer substrate, a column structure located on the wafer substrate, a polysilicon gate layer located on the column structure, and a source region formed in the column structure, wherein the width of the polysilicon gate layer is: The column structure includes first columns of a first conductivity type and second columns of a second conductivity type, and the first columns and the second columns are arranged alternately; The polysilicon gate layer includes an inner first injection region and an outer second injection region, wherein the first injection region is a first conductivity type body region; The second injection region has a first conductivity type, is located in the column structure, and is connected to the first column.
2. The device according to claim 1, characterized in that The first column includes: an access column and a floating column, wherein the access column is a first column connected to the source region, and the floating column is a first column not connected to the source region; The second injection region is connected to the floating column and the access column respectively.
3. The device according to claim 1, characterized in that The column structure includes an oxide layer, the polysilicon gate layer is located on the oxide layer, and the first injection region and the second injection region are located under the oxide layer corresponding to the polysilicon gate layer.
4. The device according to claim 2, characterized in that The access pillar includes a heavily doped region of the first conductivity type, and the source region is formed in the heavily doped region.
5. The device according to claim 4, characterized in that The device further comprises: a source metal, and the source region is connected to the source metal through a contact hole.
6. The device according to claim 5, characterized in that The device further comprises a gate lead, and the polysilicon gate layer is connected to the gate lead.
7. The device according to claim 5, characterized in that An interlayer dielectric is included between the source metal and the second implantation region.
8. The device according to claim 5, characterized in that An interlayer dielectric is provided between the polysilicon gate layer and the gate lead.
9. The device according to claim 1, characterized in that The wafer substrate has a second conductivity type, and the wafer substrate has a first surface and a second surface opposite to each other; The device further includes a drain electrode formed on a first surface of the wafer substrate, and the pillar structure is disposed on a second surface of the wafer substrate.
10. The device according to claim 1, characterized in that The first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type.